JPS59125638A - Manufacture of semiconductor element isolation - Google Patents
Manufacture of semiconductor element isolationInfo
- Publication number
- JPS59125638A JPS59125638A JP31483A JP31483A JPS59125638A JP S59125638 A JPS59125638 A JP S59125638A JP 31483 A JP31483 A JP 31483A JP 31483 A JP31483 A JP 31483A JP S59125638 A JPS59125638 A JP S59125638A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- oxide film
- groove
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はシリコン乗積回路における素子間の絶縁分離の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing insulation isolation between elements in a silicon product circuit.
従来よシ、素子間の絶縁分離法としては、選択酸化によ
る方法が広く用いられている。この方法では、７リコン
窒化腺をマスクにして、７リコン基板を部分的に熱ば化
する。Conventionally, selective oxidation has been widely used as a method for insulating and isolating elements. In this method, the 7 Licon substrate is partially heated using the 7 Licon nitriding gland as a mask.
第１図にこの健米孜術の断面図をボす。１はシリコン基
板、２はシリコン窒化膜である。熱准化すると、シリコ
ン従化鴛で憶わｎていない部分に酸化膜３が形成される
。この時、酸化膜の厚みイ目当のくい込み４が生じるた
め、杷縁分離領域が広がってしまう。従って、この方法
は倣ｌＩ＋Ｉ１１パターン形成には適さない。Figure 1 shows a cross-sectional view of this Kenbei Keijutsu. 1 is a silicon substrate, and 2 is a silicon nitride film. When thermally assimilated, an oxide film 3 is formed in the areas not covered by the silicon layer. At this time, since the oxide film is indented 4 by the thickness of the oxide film, the lobe edge separation region becomes wider. Therefore, this method is not suitable for copying II+I11 pattern formation.
第２図は従来技術であるアイングレーナー法の断面図で
ある。この場合、選択ば化する部分を、酸化膜の厚さの
約１／２だけエツチングして溝５を形成する。仄に熱酸
化す、ると、は化膜６の底面は、シリコン基板表面とほ
ぼ同一の高さになる。FIG. 2 is a sectional view of the conventional Einglener method. In this case, the groove 5 is formed by etching the selectively etched portion by about 1/2 of the thickness of the oxide film. When slightly thermally oxidized, the bottom surface of the oxide film 6 becomes approximately at the same height as the surface of the silicon substrate.
この方法においても、酸化膜のくい込み７が生ずるため
、微細パターン形成には適さない。This method also causes oxidation film penetration 7, and is therefore not suitable for forming fine patterns.
本発明の目的は、従来法の欠点である酸化膜のくい込み
を防止し、微細パターン形成を町Ｈ目にすると同時に、
フィールド領域に平担でかつ厚い酸化膜全形成する方法
を提供することである。The purpose of the present invention is to prevent the penetration of the oxide film, which is a drawback of the conventional method, and to improve the formation of fine patterns, while at the same time
It is an object of the present invention to provide a method for forming a flat and thick oxide film all over a field region.
不発明の特徴は、シリコン半導体装置の素子間絶縁分離
に関して、シリコン基板の素子分離領域となるべき領域
がエツチングされ、鉾が形成きれることと、前記シリコ
ン基板表面に、酸化Ｍをはさんでシリコン窒化膜がＭ、
涜されでいることと、前記シリコン窒化膜をマスクにし
て選択酸化する時、前記シリコン窒化膜内に酸化膜が後
人する距離とほぼ等しい巾だけ、ｎｕ記シリコン窒化膜
が削記碑の低部の周囲に残されるように、月１１記屑低
部の前記シリコン窒化膜がエツチングさ扛ていることと
、前記シリコン窒化膜をマスクにして、前記溝の深さの
約２借の厚めの熱酸化膜が形成されることと、前記溝お
よびｎ１１記熱酸化によって生ずる前記シリコン基板と
前記熱酸化膜間の溝が前記シリコン基板表面がはｅよ平
担になる様に他の酸化膜が埋め込まれている絶縁分離の
製造方法にある。The inventive feature is that, regarding insulation isolation between elements of a silicon semiconductor device, a region of the silicon substrate that should become an element isolation region is etched to form a ridge, and that silicon oxide is sandwiched between the silicon substrate surface and silicon oxide. The nitride film is M,
Also, when performing selective oxidation using the silicon nitride film as a mask, the silicon nitride film is removed by a width approximately equal to the distance that the oxide film leaves behind in the silicon nitride film. The silicon nitride film at the bottom of the scrap is etched away so that it remains around the groove, and using the silicon nitride film as a mask, etching is etched to a thickness approximately two times the depth of the groove. A thermal oxide film is formed, and another oxide film is formed so that the groove and the groove between the silicon substrate and the thermal oxide film caused by the thermal oxidation become flat as the surface of the silicon substrate. The manufacturing method of the embedded insulation isolation.
本発明は、溝堀シ分離あるいはトレンチ法と呼ばれてい
る。The present invention is called the Mizohori isolation or trench method.
シリコン基板に形成された鉤を絶縁物で埋め込む方法と
、前記選択酸化法の長所ｆｒ：組み合せることにより、
ｇ細パターンの分離と、厚い酸化膜で伎われたフィール
ド領域の形成を可能にするものである０厚いフィールド
鍍化膜は、この上に形成される配線の寄生容量全減少さ
せるのに効果がある◎配線の寄生容量による信号伝搬の
遅れは、最小寸法が１μｍ以下の乗値回路において顕著
である。By combining the method of embedding the hooks formed on the silicon substrate with an insulator and the advantages of the selective oxidation method,
A thick field plating film, which enables the isolation of thin patterns and the formation of a field region covered by a thick oxide film, is effective in reducing the total parasitic capacitance of the wiring formed on it. ◎Delay in signal propagation due to parasitic capacitance of wiring is noticeable in multiplier circuits with minimum dimensions of 1 μm or less.
本発明の実施例の素子断面図を第３図に製造工８唄を追
って示す。A cross-sectional view of an element according to an embodiment of the present invention is shown in FIG. 3 along with eight manufacturing steps.
第３図（ａ）において、１ｏｉｌ−ｉ、シリコン基板で
ある。In FIG. 3(a), 1 oil-i is a silicon substrate.
例えばフォトレジスト１１をマスクにして、プラズマ異
方性エツチングにょシシリコンｉｌ！；板に溝１２゜１
３が形成される。溝１２は素子間の狭い分離′領域に、
溝１３はフィールド領域に対応する。次にレジスト１１
をはくジしてから、熱酸化によシ、５００人前板のりす
い酸化膜１４を形成し、その上に１００ＯＡ程贋のシリ
コン窒化膜１５を気相成長により４着する（第３図（ｂ
））。次に、通常の７オトリングラフイーにより、フィ
ールド領域１６のシリコン窒化膜のみ、エツチングで除
去する。For example, using the photoresist 11 as a mask, plasma anisotropic etching is performed using silicon il! ;Groove 12゜1 on the plate
3 is formed. The grooves 12 are located in the narrow separation area between the elements.
Groove 13 corresponds to the field area. Next, resist 11
After peeling off the silicon nitride film 14, a 500-layer thick oxide film 14 is formed by thermal oxidation, and four fake silicon nitride films 15 of about 100 OA are deposited on it by vapor phase growth (see Fig. 3). b
)). Next, only the silicon nitride film in the field region 16 is removed by etching using normal 7-etching technique.
この時、溝のエツジに沿った部分の窒化膜１７は、選択
酸化膜が窒化膜内にくい込む長さだけ残しておく（第３
図（Ｃ））。仄に、選択酸化を行う。この時、溝１３の
深さの約２倍の厚みを持つ熱酸化膜１８Ｔｈ形成する（
第３図（ｄ））。こうすると、シリコン基板表面とフィ
ールド酸化膜１８０表面とがほぼ同一の高さになる。次
に、窒化膜をエツチングする。そして、溝１２あるいは
溝１９が完全に埋この酸化形美には、ステップカバレッ
ジの艮い、プラ、（マｃＶＤ Ｓｉｎ、、スパッターｓ
ｉｏ、６るいは元ＣＶ Ｄ Ｓ １０２告が適する。こ
の酸化膜厚は、溝１２ろるいは１９の巾の１／２よジも
厚いことが必要である。最後に、この酸化膜を丁度厚さ
分だけエツチングする。At this time, the portion of the nitride film 17 along the edge of the groove is left with a length that allows the selective oxide film to sink into the nitride film (third
Figure (C)). In addition, selective oxidation is performed. At this time, a thermal oxide film 18Th having a thickness approximately twice the depth of the trench 13 is formed (
Figure 3(d)). In this way, the surface of the silicon substrate and the surface of field oxide film 180 become approximately at the same height. Next, the nitride film is etched. Then, to completely fill the grooves 12 or 19 with oxidation, step coverage, plastic, (McVD Sin, sputtering) etc.
io, 6 or former CV D S 102 notification is suitable. The thickness of this oxide film needs to be about 1/2 the width of the groove 12 or 19. Finally, this oxide film is etched to just the desired thickness.
こうすることによシ、第３図（ｆ）に示される様に、表
面が平担な絶縁分離領域が形成される。By doing this, an insulating isolation region with a flat surface is formed as shown in FIG. 3(f).
本発明の特徴は、微細な素子分離領域と、厚い酸化膜で
伝われたフィールド・領域が同時に形成できることと、
基板表面が平担であることにある。The features of the present invention are that a fine element isolation region and a field/region propagated through a thick oxide film can be simultaneously formed;
The reason is that the substrate surface is flat.
又、通常の選択酸化汰全そのまま用いているため、シリ
コン基板にストレスを発生させたジ、結晶欠陥を誘起さ
せたシすることがない。In addition, since all the usual selective oxidation is used as is, stress on the silicon substrate and crystal defects are not induced.
本発明を笑施することによシ、微細分離領域による高乗
積密度と、ノ４いフィールド絶縁膜によるを主容量の減
少が実現できる。By implementing the present invention, a high product density due to the fine isolation region and a reduction in main capacitance due to the small field insulating film can be realized.
第１図および第２図は従来法による素子分離法を説明す
るための素子断面図、第３図は、本発明の詳細な説明す
るための素子断面図である。
尚、図において、
ｌ・・・・・・シリコンｉ板、２・・自・・シリコンｉ
化膜、３．６・・・・・・フィールド熱酸化膜、４，７
・・・・・・酸化膜のくい込み、５・・・・・・溝、１
０・・・・・・シリコン基板、１１・・・・・・フォト
レジスト、１２・・・・・・狭い素子分離溝、１３・・
・・・・フィールド溝、１４・・・・・・熱酸化膜、１
５・・・・・・７リコン窒化膜、１６・・・・・・フィ
ールド領ｄ、１７・・・・・・シリコｙｆｆｌ（ＩＪＬ
１８・・・・・・フィールド熱酸化膜、１９・・・
・・・溝、２０・・・・・・酸化膜、２１・・・・・・
フィールド歇化膜、２２・・・・・・累子分離′碩域で
ある。1 and 2 are device cross-sectional views for explaining a conventional device isolation method, and FIG. 3 is a device cross-sectional view for explaining the present invention in detail. In the figure, l...Silicon i plate, 2...Self...Silicon i
oxide film, 3.6...Field thermal oxide film, 4,7
...... Oxide film penetration, 5... Groove, 1
0...Silicon substrate, 11...Photoresist, 12...Narrow element isolation trench, 13...
...Field groove, 14...Thermal oxide film, 1
5...7 silicon nitride film, 16... field region d, 17... silicon yffl (IJL
18...Field thermal oxide film, 19...
...Groove, 20...Oxide film, 21...
Field temporization film, 22... is a gradation separation'segregation area.
Claims (1)
する工程と、前記シリコン基板衆囲に、酸化族をはさん
でシリコン電化膜が破着する工程と、前記シリコン窒化
膜をマスクにして選択酸化する時、前記シリコン窒化膜
内に酸化膜が侵入する距離とほぼ等しい巾だけ、前記シ
リコン窒化膜が前記溝の低部の周囲に残されるように、
前記溝低部の前記シリコン窒化膜をエツチングする工程
と、前記シリコン窒化膜をマスクにして熱酸化膜を形成
する工程と、前記溝および前ｄＣ熱酸化によって生ずる
前記シリコン基板と前記熱は化膜間の溝に前記シリコン
基板表面がほぼ平担になる様に他の酸化膜を埋め込む工
程とを有すること全特徴とする半導体素子分離の製造方
法。A step of forming an enzyme on the silicon substrate which is to become an element isolation region, a step of adhering a silicon electrified film around the silicon substrate with an oxide group in between, and a step of making a selection using the silicon nitride film as a mask. When oxidizing, the silicon nitride film is left around the bottom of the trench by a width approximately equal to the distance that the oxide film penetrates into the silicon nitride film,
a step of etching the silicon nitride film at the bottom of the trench; a step of forming a thermal oxide film using the silicon nitride film as a mask; A method for manufacturing semiconductor element isolation, comprising the step of embedding another oxide film in the groove between the silicon substrates so that the surface of the silicon substrate becomes substantially flat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31483A JPS59125638A (en) | 1983-01-05 | 1983-01-05 | Manufacture of semiconductor element isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31483A JPS59125638A (en) | 1983-01-05 | 1983-01-05 | Manufacture of semiconductor element isolation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59125638A true JPS59125638A (en) | 1984-07-20 |
| JPS6351537B2 JPS6351537B2 (en) | 1988-10-14 |
Family
ID=11470446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31483A Granted JPS59125638A (en) | 1983-01-05 | 1983-01-05 | Manufacture of semiconductor element isolation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59125638A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0252450A2 (en) * | 1986-07-07 | 1988-01-13 | Texas Instruments Incorporated | Integrated circuit isolation process |
| US4892614A (en) * | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
| JPH09153542A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Method of manufacturing semiconductor device |
| KR100329606B1 (en) * | 1995-06-02 | 2002-10-25 | 주식회사 하이닉스반도체 | Method for forming isolation layer in semiconductor device |
| KR100361762B1 (en) * | 1995-11-06 | 2003-02-11 | 주식회사 하이닉스반도체 | Isolation method of semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02179246A (en) * | 1988-12-28 | 1990-07-12 | Fanuc Ltd | Stator construction of built-in motor |
| JPH0635652Y2 (en) * | 1989-02-06 | 1994-09-14 | 神鋼電機株式会社 | Core retainer plate for semi-finished stator that separates cutting chips |
| JPH0617345U (en) * | 1992-07-22 | 1994-03-04 | 東洋電機製造株式会社 | Alternator stator without frame |
-
1983
- 1983-01-05 JP JP31483A patent/JPS59125638A/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0252450A2 (en) * | 1986-07-07 | 1988-01-13 | Texas Instruments Incorporated | Integrated circuit isolation process |
| JPS6340337A (en) * | 1986-07-07 | 1988-02-20 | テキサス インスツルメンツ インコ−ポレイテツド | Method of isolating integrated circuit |
| US4892614A (en) * | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
| KR100329606B1 (en) * | 1995-06-02 | 2002-10-25 | 주식회사 하이닉스반도체 | Method for forming isolation layer in semiconductor device |
| KR100361762B1 (en) * | 1995-11-06 | 2003-02-11 | 주식회사 하이닉스반도체 | Isolation method of semiconductor device |
| JPH09153542A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6351537B2 (en) | 1988-10-14 |
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