JPH01251641A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01251641A JPH01251641A JP7591888A JP7591888A JPH01251641A JP H01251641 A JPH01251641 A JP H01251641A JP 7591888 A JP7591888 A JP 7591888A JP 7591888 A JP7591888 A JP 7591888A JP H01251641 A JPH01251641 A JP H01251641A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- wiring
- forming
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 238000007747 plating Methods 0.000 abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052697 platinum Inorganic materials 0.000 abstract description 5
- 229910052719 titanium Inorganic materials 0.000 abstract description 5
- 239000010936 titanium Substances 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 abstract 2
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 abstract 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に多層配線構
造における配線層間の平坦化を図った半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that achieves planarization between wiring layers in a multilayer wiring structure.
従来、多層配線構造を有する半導体装置では、上側配線
の加工精度の向上、耐マイグレーシヨンの改善、及び断
線防止等の目的のために、下側配線上に形成する眉間絶
縁膜の平坦化を図っている。Conventionally, in semiconductor devices having a multilayer wiring structure, the glabella insulating film formed on the lower wiring has been flattened for the purpose of improving processing accuracy of the upper wiring, improving migration resistance, and preventing disconnection. ing.
この場合、一般的な方法としては、下側配線上に形成し
た眉間絶縁膜の凹凸面上に絶縁膜を塗布し、かつこの絶
縁膜と眉間絶縁膜とをエツチングバックすることにより
眉間絶縁膜の上面を平坦化する方法が用いられている。In this case, the general method is to apply an insulating film on the uneven surface of the glabellar insulating film formed on the lower wiring, and to etch back this insulating film and the glabellar insulating film. A method of flattening the top surface is used.
上述した従来の方法では、眉間絶縁膜上に塗布した絶縁
膜の上面が平坦でないと、エツチングバックを行っても
眉間絶縁膜の上面を平坦にすることが難しい。また、配
線間隔が狭くなって眉間絶縁膜に生じる凹凸面が微小に
なると、この微小凹部内に空洞を生じさせることなく絶
縁膜を塗布することが難しくなり、絶縁性の高い眉間絶
縁膜を形成することができないという問題がある。In the conventional method described above, if the upper surface of the insulating film coated on the glabellar insulating film is not flat, it is difficult to flatten the upper surface of the glabellar insulating film even if etching back is performed. In addition, when the wiring spacing becomes narrower and the uneven surface that occurs in the glabellar insulating film becomes minute, it becomes difficult to apply the insulating film without creating cavities within these minute recesses, forming a highly insulating glabellar insulating film. The problem is that it cannot be done.
本発明は上述した問題を解消し、平坦性及び絶縁性に優
れた眉間絶縁膜を有する半導体装置の製造方法を提供す
ることを目的としている。An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device having a glabellar insulating film with excellent flatness and insulation properties.
本発明の半導体装置の製造方法は、半導体基板上に絶縁
膜を形成する工程と、この絶縁膜をフォトレジスト膜を
用いて選択エツチングし、下側配線形成箇所に配線用溝
を形成する工程と、この配線用溝を含む全面に導体膜を
形成して配線用溝に導体膜を埋設する工程と、前記フォ
トレジスト膜を剥離除去して配線用溝以外の導体膜を除
去する工程と、全面に第2絶縁膜を成長させる工程とを
含んでいる。The method for manufacturing a semiconductor device of the present invention includes a step of forming an insulating film on a semiconductor substrate, and a step of selectively etching the insulating film using a photoresist film to form a wiring groove at a lower wiring formation location. , a step of forming a conductive film on the entire surface including the wiring groove and embedding the conductive film in the wiring groove; a step of peeling off the photoresist film to remove the conductive film other than the wiring groove; and a step of growing a second insulating film.
上述した方法では、平坦な絶縁膜に形成した配線用溝内
に下側配線を埋設状態に形成し、この上に第2絶縁膜を
形成することにより、眉間絶縁膜をエツチング処理する
ことなく平坦化を達成する。In the method described above, the lower wiring is buried in a wiring groove formed in a flat insulating film, and the second insulating film is formed on top of the lower wiring, thereby flattening the glabella insulating film without etching. achieve the goal of
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図乃至第6図は本発明の一実施例を製造工程順に示
す断面図である。1 to 6 are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps.
先ず、第1図のように、半導体基板1上に気相成長法に
よって窒化シリコン(S iz N4 ) 、酸化シリ
コン(SiOz)等の絶縁膜2を成長させる。また、こ
の上にアルミニウム膜3をスパッタ法により形成する。First, as shown in FIG. 1, an insulating film 2 made of silicon nitride (S iz N4 ), silicon oxide (SiOz), or the like is grown on a semiconductor substrate 1 by vapor phase growth. Furthermore, an aluminum film 3 is formed thereon by sputtering.
次いで、第2図のように、フォトレジスト膜4を塗布形
成し、このフォトレジスト膜4をマスクにしたりソグラ
フィ法によって下側配線を形成する箇所のアルミニウム
膜3と絶縁膜2をエツチングし、配線用溝5を形成する
。Next, as shown in FIG. 2, a photoresist film 4 is applied and formed, and the aluminum film 3 and insulating film 2 at the locations where the lower wiring is to be formed are etched using the photoresist film 4 as a mask or by lithography to form the wiring. A groove 5 is formed.
続いて、第3図のように、全面にチタン、白金等をスパ
ッタし、少なくとも前記配線用溝5の底面及び側面にチ
タン・白金膜6を形成する。その後、フォトレジスト膜
4を剥離除去することにより、所謂リフトオフ法によっ
て第4図のように配線用溝5以外のチタン・白金膜6が
除去される。Subsequently, as shown in FIG. 3, titanium, platinum, or the like is sputtered over the entire surface to form a titanium/platinum film 6 at least on the bottom and side surfaces of the wiring trench 5. Thereafter, by peeling off the photoresist film 4, the titanium/platinum film 6 other than the wiring groove 5 is removed by a so-called lift-off method, as shown in FIG.
次いで、第5図のように、再度フォトレジスト膜7を塗
布し、かつ先に用いたフォトマスクを再度利用してこれ
をパターン形成し、配線用溝5の箇所を開口する。そし
て、金メツキ処理することにより、配線用溝5内に金メ
ツキ層を埋設状態に形成し、下側配線層8を形成する。Next, as shown in FIG. 5, a photoresist film 7 is applied again, and the previously used photomask is again used to form a pattern to open the wiring groove 5. Then, by performing a gold plating process, a gold plating layer is buried in the wiring groove 5 to form a lower wiring layer 8.
この場合、金メツキ層は前記絶縁膜2の厚さと同じ厚さ
となるようにメツキ処理を管理することが肝要である。In this case, it is important to manage the plating process so that the gold plating layer has the same thickness as the insulating film 2.
そして、第6図のように、前記フォトレジスト膜7を除
去し、かつアルミニウム膜3をウェットエツチングして
除去し、この上に絶縁膜2と同じ或いは異なる第2絶縁
膜9を成長させることにより、上面の平坦な眉間絶縁膜
を構成できる。Then, as shown in FIG. 6, the photoresist film 7 is removed, the aluminum film 3 is removed by wet etching, and a second insulating film 9 that is the same as or different from the insulating film 2 is grown thereon. , it is possible to form a glabella insulating film with a flat upper surface.
なお、この眉間絶縁膜の上に上側配線を形成することは
言うまでもない。Note that it goes without saying that the upper wiring is formed on this glabellar insulating film.
したがって、この製造方法では、眉間絶縁膜の上面に絶
縁膜を塗布する工程や、これら絶縁膜と眉間絶縁膜をエ
ツチングバックする工程が不要となり、これらの工程に
おける上述したような問題が生じることはない。これに
より、平坦性及び絶縁性に優れた眉間絶縁膜を得ること
ができ、かつ上側配線の加工精度を向上させ、耐マイグ
レーションの改善、及び断線の防止が達成できる。Therefore, this manufacturing method eliminates the need for the step of applying an insulating film on the upper surface of the glabellar insulating film and the step of etching back these insulating films and the glabellar insulating film, and eliminates the above-mentioned problems in these steps. do not have. As a result, it is possible to obtain a glabellar insulating film with excellent flatness and insulation, improve the processing accuracy of the upper wiring, improve migration resistance, and prevent disconnection.
なお、アルミニウム膜、チタン・白金膜等は他の材質で
構成できることは勿論である。It goes without saying that the aluminum film, titanium/platinum film, etc. can be made of other materials.
以上説明したように本発明は、平坦な絶縁膜に形成した
配線用溝内に下側配線を埋設状態に形成し、かつこの上
に第2絶縁膜を形成することにより、眉間絶縁膜上に絶
縁膜を塗布する工程、及び眉間絶縁膜をエツチング処理
する工程を不要にする一方で眉間絶縁膜の平坦化を図り
、上側配線の加工精度の向上、耐マイグレーションの改
善、及び断線防止を達成できる。As explained above, the present invention embeds the lower wiring in a wiring trench formed in a flat insulating film, and forms a second insulating film on top of the lower wiring, thereby forming a layer on the glabella insulating film. While eliminating the need for the process of applying an insulating film and the process of etching the glabellar insulating film, the glabellar insulating film can be made flat, improving the processing accuracy of the upper wiring, improving migration resistance, and preventing disconnection. .
第1図乃至第6図は本発明を製造工程順に示す断面図で
ある。
1・・・半導体基板、2・・・絶縁膜、3・・・アルミ
ニウム膜、4・・・フォトレジスト膜、5・・・配線用
溝、6・・・アルミニウム膜、7・・・フォトレジスト
膜、8・・・下側配線(金メツキ層)、9・・・第2絶
縁膜。
第1図
色 (1
第4図
第5図1 to 6 are cross-sectional views showing the present invention in the order of manufacturing steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Aluminum film, 4... Photoresist film, 5... Wiring groove, 6... Aluminum film, 7... Photoresist Film, 8... Lower wiring (gold plating layer), 9... Second insulating film. Figure 1 Color (1 Figure 4 Figure 5
Claims (1)
膜をフォトレジスト膜を用いて選択エッチングし、下側
配線形成箇所に配線用溝を形成する工程と、この配線用
溝を含む全面に導体膜を形成して配線用溝に導体膜を埋
設する工程と、前記フォトレジスト膜を剥離除去して配
線用溝以外の導体膜を除去する工程と、全面に第2絶縁
膜を成長させる工程とを含むことを特徴とする半導体装
置の製造方法。1. A process of forming an insulating film on a semiconductor substrate, a process of selectively etching this insulating film using a photoresist film, and forming a wiring groove at a lower wiring formation location, and a process of forming an entire surface including this wiring groove. a step of forming a conductive film on the substrate and embedding the conductive film in the wiring trench; a step of peeling off the photoresist film to remove the conductive film other than the wiring trench; and growing a second insulating film over the entire surface. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7591888A JPH01251641A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7591888A JPH01251641A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01251641A true JPH01251641A (en) | 1989-10-06 |
Family
ID=13590177
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7591888A Pending JPH01251641A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01251641A (en) |
-
1988
- 1988-03-31 JP JP7591888A patent/JPH01251641A/en active Pending
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