JPS6053045A - Dielectric isolation method - Google Patents

Abstract

PURPOSE:To obtain an extremely microscopic dielectric isolation structure of excellent surface flatness as well as to accomplish the state of high density and microscopic formation of a VLSI (very large scale integrated circuit) by a method wherein, after an insulating material has been buried in a groove by performing a bias sputtering method, the insulating material formed on the area other than an insulated region is selectively removed in a self-matching manner. CONSTITUTION:A resistor pattern 4 is formed on an Si substrate 1 excluding insulated regions 2 and 3 by performing an ordinary lithographic method, and a dry etching is performed vertically on the Si substrate 1 using said resist pattern 4 as a mask. After the resist pattern 4 has been removed, an insulating material 5 is coated on the whole surface by performing a bias sputtering. Then, a dry or wet etching is performed on the whole surface of the SiO2 5, and the etching is finished at the point of time when the upper end part 6 of the isolation groove is exposed. Subsequently, a photoresist 7 is coated on the whole surface, and the part 8 located within the region other than isolated regions 2' and 3' is selectively removed. Then, SiO2 films 9 and 9' on the area other than the isolation region is removed by performing a wet etching, and then the photoresist is removed. Through the above-mentioned procedures, SiO2 can be simply buried into the isolation grooves 2' and 3' having different width in a self-matching manner.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for insulating and separating semiconductor integrated circuits.

[The background of the invention]

A method of forming a groove in a semiconductor substrate and filling it with an insulating material is being developed using technology for highly fragile elements of semiconductor integrated circuits. The main challenges in such a method are to simplify the manufacturing process and to flatly embed the different grooves; As a typical embedding method, CV D (Ch
5io2 by chemical vapor deposition) method or HLD (high temperature and low pressure chemical vapor deposition) method
However, this method has problems in that the step of selectively removing 810□ adhered to areas other than the insulation isolation region is complicated, and the flatness of the buried surface tends to be poor.

[Purpose of the invention]

It is an object of the present invention to provide an element insulation isolation method that eliminates all the drawbacks of the conventional method described above, removes impurities other than the isolation region by self-alignment, and has good flatness.

[Summary of the invention]

The present invention is characterized in that an insulating material is buried in a trench in an isolation region formed in a substrate by a bias sputtering method. In particular, when filling an insulating material by a bias sputtering method, a thin insulating film is formed at the upper end of the trench. Insulators outside the isolation area can be removed using self-alignment using gold! [Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings.

Actual gun example 1 FIG. 1 is a process diagram showing a practical example 11 of the present invention.

As shown in FIG. 1 (1), a resist pattern 4 is formed on the SI substrate 1 in areas other than the insulating regions 2 and 3 by a normal sonography method, and using the resist pattern 4 as a mask, a resist pattern 4 is formed on the SI substrate 1 using a fc dryer. I made it vertically by etching. At this time, reactive sputter etching using a mixed gas of CCt4 and 02 was used for dry etching.

Incidentally, in this case, if the etching mask is insufficient for the four-year resist pattern layer, 8102 or the like may be inserted between the resist 4 and the 3i substrate 1 as appropriate. After removing the resist pattern 4, as shown in FIG. 41 (2), the bias sputtering method is used to destroy the common color edges 1 and 5f on the entire surface.

In this example, the insulator was 5lo2. It is desirable that the approximate thickness of 5iuzN5 be equal to or thicker than the depths of the separation grooves 2' and 3'.What is bias sputtering? In this example, the target density acting on the deposition was set as L k 2 W,/crd, and the substrate power acting on the esoboung was set as 0.3 W/ca. The deposition speed of 8102 at this time was 20 nm 7 minutes. Furthermore, the narrower the separation groove width is, the more difficult it is for 5I02 to be buried in the groove, but this can be solved by increasing the substrate mixed force density I. Thereafter, the entire surface is etched by dry or wet etching, and the etching is terminated when the lrA portion 6 above the separation groove is exposed. Through the above steps, the embedding of 8102 into the isolation trenches 2' and 3' is completed, and the Si substrate 1 is exposed at the interface between the isolation trenches 2' and 3' and other areas, and is separated by self-alignment. be done. Thereafter, as shown in FIG. 1 (3), a photoresist 7 is deposited on the entire surface by a normal method, and the separated region 2 is
A portion 87il in the area other than /, 3/ is selectively removed. After that, wet etching for 9 minutes (・j
[Remove the 5i02 film 9.9' i outside the ¥ area.

After that, the photoresist gold is removed. Through the above steps, as shown in FIG. 1 (4), separation grooves 2/ of different widths,
5102 could be easily inserted into a,/ with self-alignment. In addition, in the above actual example, separation regions 2' and 3
'! 'The sandwiched region 10 is narrow (for example, 1 μm
In the following case), the 5i02 film formed by bias sputtering on the region 10 is thin and has a substantially flat surface with the S'02 surface of the separation region.

Therefore, the 5102 on the region 10 is completely removed by the 5I02 whole surface etching process after the bias sputtering, and the subsequent 5I02 removal process becomes unnecessary.

Example 2 FIG. 2 is a process diagram showing another example of the present invention. Second
As shown in Figure (1), a 5L3N4 film 11 is formed on a Noricon substrate 1, and then a resist butter/4 is formed in areas other than the insulating regions 2 and 3 by a normal lamination method, and the resist pattern 4 is masked. as S'3N4
Processed in the usual way. Thereafter, the Si substrate 1 was vertically processed by dry etching in the same manner as the left-hand processing 1. After that, as shown in FIG. 2 (2), the implementation ρ111
Similarly, the insulator 5 was deposited over the entire surface by bias sputtering.

scold f12, :l! Etched the entire surface by dry or wet etching of °I-V+'+ for 5io2s;
5L3N411A of upper 11' side of separation groove r'X++ 6
Etching is finished when 11 is exposed. Thereafter, as shown in FIG. 2(3), the Si3
Etching proceeds from the crest of N4, and 9 and 9' are removed by 1 by so-called lift-off. The etch speed 1 at this time is 14 nm 7 minutes 810 for 513N4
2Oy5nm/min. Note that FIG. 2 (3) shows an intermediate stage of lift-off. Through the above steps, the process shown in Figure 2 (
As shown in 4), an excellent insulation isolation structure was achieved.

Although S'aN4 is used here as the lift-off insertion film, it is not limited to this, and any material and etching method that has a sufficiently high etch rate for 8102 and Si can be applied.

The greatest feature of the present invention explained above in Examples 1i- and 2 is that 8102 deposited by bias sputtering is etched on the entire surface until the upper end of Usumizo is exposed. The separation region and other regions can be separated by self-alignment in a simple process. Therefore, for other matters, such as the shape of the separation groove, the etching method is not limited to the round shape, the groove shape is not limited to the blood pattern, and the etching method is also applicable to groove shapes such as 7-shapes, squares, and U-shapes, and the etching method is the etching method.

SIO2 was used for indigo and fried foods, but SIO2 is not limited to this.
It is applicable to any type of proboscis such as i3N4°A t 203. It should be noted that it is necessary to prevent the generation of parasitic channels on both sides of the bottom surface 9 of the lifting platform and grooves 2/ and 3/ in which such a structure is used to separate various types of semiconducting yarn, but during the process of the present invention, It cannot be said that it is easy to cut a chamfer by implanting ions or diffusing impurities into the inner surface of the groove. In order to prevent contamination from entering the Si substrate 1 during the bias sputtering process, after forming the grooves 2' and 3',
pSlo by standard methods. Alternatively, it is effective to coat the entire surface with 513N4 or the like.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to uniformly inject the insulating material regardless of the size of the groove width, and furthermore, it is possible to perform self-alignment to remove the insulating material other than the insulating area (C). Therefore, it is possible to obtain a separation groove structure without good surface flatness.Therefore, by application of the present invention, it is possible to achieve a VLSI with high efficiency, high density, and miniaturization. .

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are process diagrams showing different embodiments of the present invention, respectively. l...Silicon substrate, 2, 3...Isolation region, 5...
・Zero membrane (SIO2: bias supanota), 4.7...
・“2″3′ Continuation of 2nd page 1 [stock] ・Inventor Hisare Tokuo Kokubunji City Higashikoi・
T-kubo 1-28, Central Research Institute, Hitachi, Ltd. = 99

Claims (1)

[Claims] In an element isolation method in which a groove is formed in an element isolation region of a semiconductor substrate and an insulator is buried in the groove, there are two steps: burying an insulator in the groove by bias sputtering, and removing the insulator formed outside the isolation region. Does it include a process of selective removal through self-alignment? Features: A method for insulating and separating semiconductor elements.