JPS59115553A - 抵抗素子の形成方法 - Google Patents

抵抗素子の形成方法

Info

Publication number
JPS59115553A
JPS59115553A JP58127057A JP12705783A JPS59115553A JP S59115553 A JPS59115553 A JP S59115553A JP 58127057 A JP58127057 A JP 58127057A JP 12705783 A JP12705783 A JP 12705783A JP S59115553 A JPS59115553 A JP S59115553A
Authority
JP
Japan
Prior art keywords
layer
forming
substrate
resistive
resistive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58127057A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0228901B2 (enExample
Inventor
ハ−サラン・シン・バ−テイア
ヤコブ・ライズマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS59115553A publication Critical patent/JPS59115553A/ja
Publication of JPH0228901B2 publication Critical patent/JPH0228901B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)
JP58127057A 1982-12-13 1983-07-14 抵抗素子の形成方法 Granted JPS59115553A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US449122 1982-12-13
US06/449,122 US4464212A (en) 1982-12-13 1982-12-13 Method for making high sheet resistivity resistors

Publications (2)

Publication Number Publication Date
JPS59115553A true JPS59115553A (ja) 1984-07-04
JPH0228901B2 JPH0228901B2 (enExample) 1990-06-27

Family

ID=23782949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127057A Granted JPS59115553A (ja) 1982-12-13 1983-07-14 抵抗素子の形成方法

Country Status (4)

Country Link
US (1) US4464212A (enExample)
EP (1) EP0113405B1 (enExample)
JP (1) JPS59115553A (enExample)
DE (1) DE3380613D1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01110727A (ja) * 1987-10-23 1989-04-27 Nec Corp 半導体装置の製造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722908A (en) * 1986-08-28 1988-02-02 Fairchild Semiconductor Corporation Fabrication of a bipolar transistor with a polysilicon ribbon
KR920004957B1 (ko) * 1988-11-12 1992-06-22 현대 전자산업 주식회사 산화물 측면벽의 폴리실리콘 스페이서를 이용한 고저항 부하 제조방법
US5151376A (en) * 1990-05-31 1992-09-29 Sgs-Thomson Microelectronics, Inc. Method of making polycrystalline silicon resistors for integrated circuits
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5177027A (en) * 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5122848A (en) * 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5273934A (en) * 1991-06-19 1993-12-28 Siemens Aktiengesellschaft Method for producing a doped region in a substrate
US5182627A (en) * 1991-09-30 1993-01-26 Sgs-Thomson Microelectronics, Inc. Interconnect and resistor for integrated circuits
EP1403909A1 (en) * 2002-09-30 2004-03-31 STMicroelectronics S.r.l. Process for manufactoring integrated resistive elements with silicidation protection

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5563827A (en) * 1978-11-03 1980-05-14 Ibm Method of forming narrow mask opening in silicon substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332070A (en) * 1977-01-19 1982-06-01 Fairchild Camera & Instrument Corp. Method for forming a headless resistor utilizing selective diffusion and special contact formation
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
FR2445617A1 (fr) * 1978-12-28 1980-07-25 Ibm France Resistance a tension de claquage amelioree obtenue par une double implantation ionique dans un substrat semi-conducteur et son procede de fabrication
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5563827A (en) * 1978-11-03 1980-05-14 Ibm Method of forming narrow mask opening in silicon substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01110727A (ja) * 1987-10-23 1989-04-27 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0113405B1 (en) 1989-09-20
US4464212A (en) 1984-08-07
JPH0228901B2 (enExample) 1990-06-27
DE3380613D1 (en) 1989-10-26
EP0113405A3 (en) 1986-07-23
EP0113405A2 (en) 1984-07-18

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