DE3380613D1 - Method for making semiconductor resistors - Google Patents

Method for making semiconductor resistors

Info

Publication number
DE3380613D1
DE3380613D1 DE8383110966T DE3380613T DE3380613D1 DE 3380613 D1 DE3380613 D1 DE 3380613D1 DE 8383110966 T DE8383110966 T DE 8383110966T DE 3380613 T DE3380613 T DE 3380613T DE 3380613 D1 DE3380613 D1 DE 3380613D1
Authority
DE
Germany
Prior art keywords
making semiconductor
semiconductor resistors
resistors
making
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383110966T
Other languages
English (en)
Inventor
Harsaran Singh Bhatia
Jacob Riseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3380613D1 publication Critical patent/DE3380613D1/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20Resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)
DE8383110966T 1982-12-13 1983-11-03 Method for making semiconductor resistors Expired DE3380613D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/449,122 US4464212A (en) 1982-12-13 1982-12-13 Method for making high sheet resistivity resistors

Publications (1)

Publication Number Publication Date
DE3380613D1 true DE3380613D1 (en) 1989-10-26

Family

ID=23782949

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383110966T Expired DE3380613D1 (en) 1982-12-13 1983-11-03 Method for making semiconductor resistors

Country Status (4)

Country Link
US (1) US4464212A (de)
EP (1) EP0113405B1 (de)
JP (1) JPS59115553A (de)
DE (1) DE3380613D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722908A (en) * 1986-08-28 1988-02-02 Fairchild Semiconductor Corporation Fabrication of a bipolar transistor with a polysilicon ribbon
JPH01110727A (ja) * 1987-10-23 1989-04-27 Nec Corp 半導体装置の製造方法
KR920004957B1 (ko) * 1988-11-12 1992-06-22 현대 전자산업 주식회사 산화물 측면벽의 폴리실리콘 스페이서를 이용한 고저항 부하 제조방법
US5151376A (en) * 1990-05-31 1992-09-29 Sgs-Thomson Microelectronics, Inc. Method of making polycrystalline silicon resistors for integrated circuits
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5177027A (en) * 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5122848A (en) * 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5273934A (en) * 1991-06-19 1993-12-28 Siemens Aktiengesellschaft Method for producing a doped region in a substrate
US5182627A (en) * 1991-09-30 1993-01-26 Sgs-Thomson Microelectronics, Inc. Interconnect and resistor for integrated circuits
EP1403909A1 (de) * 2002-09-30 2004-03-31 STMicroelectronics S.r.l. Verfahren zur Herstellung integrierter Widerstandselemente mit Silizidationsschutz

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332070A (en) * 1977-01-19 1982-06-01 Fairchild Camera & Instrument Corp. Method for forming a headless resistor utilizing selective diffusion and special contact formation
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
FR2445617A1 (fr) * 1978-12-28 1980-07-25 Ibm France Resistance a tension de claquage amelioree obtenue par une double implantation ionique dans un substrat semi-conducteur et son procede de fabrication
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques

Also Published As

Publication number Publication date
EP0113405A3 (en) 1986-07-23
EP0113405B1 (de) 1989-09-20
JPH0228901B2 (de) 1990-06-27
JPS59115553A (ja) 1984-07-04
US4464212A (en) 1984-08-07
EP0113405A2 (de) 1984-07-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee