JPS5892242A - セラミツク多層基板 - Google Patents

セラミツク多層基板

Info

Publication number
JPS5892242A
JPS5892242A JP19113981A JP19113981A JPS5892242A JP S5892242 A JPS5892242 A JP S5892242A JP 19113981 A JP19113981 A JP 19113981A JP 19113981 A JP19113981 A JP 19113981A JP S5892242 A JPS5892242 A JP S5892242A
Authority
JP
Japan
Prior art keywords
ceramic
metallized
pad
board
plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19113981A
Other languages
English (en)
Japanese (ja)
Other versions
JPS636143B2 (enrdf_load_stackoverflow
Inventor
Katsuhiro Ono
克弘 大野
Kazuo Kawahara
河原　一雄
Toshihiro Fusayasu
房安　俊広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19113981A priority Critical patent/JPS5892242A/ja
Publication of JPS5892242A publication Critical patent/JPS5892242A/ja
Publication of JPS636143B2 publication Critical patent/JPS636143B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP19113981A 1981-11-27 1981-11-27 セラミツク多層基板 Granted JPS5892242A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19113981A JPS5892242A (ja) 1981-11-27 1981-11-27 セラミツク多層基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19113981A JPS5892242A (ja) 1981-11-27 1981-11-27 セラミツク多層基板

Publications (2)

Publication Number Publication Date
JPS5892242A true JPS5892242A (ja) 1983-06-01
JPS636143B2 JPS636143B2 (enrdf_load_stackoverflow) 1988-02-08

Family

ID=16269530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19113981A Granted JPS5892242A (ja) 1981-11-27 1981-11-27 セラミツク多層基板

Country Status (1)

Country Link
JP (1) JPS5892242A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61236148A (ja) * 1985-04-11 1986-10-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション メタライゼーシヨン・パターンへのろう付け方法
JPS6263454A (ja) * 1985-09-14 1987-03-20 Narumi China Corp 半導体装置用容器及びその製造方法
JPS62211805A (ja) * 1986-03-12 1987-09-17 富士通株式会社 グリ−ンシ−ト多層セラミツク基板の製造方法
JPH0388354A (ja) * 1989-08-31 1991-04-12 Ibiden Co Ltd 半導体パッケージ
JPH0846121A (ja) * 1995-08-09 1996-02-16 Hitachi Ltd 樹脂封止型半導体装置
JPH0846120A (ja) * 1995-08-09 1996-02-16 Hitachi Ltd 樹脂封止型半導体装置およびその製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433422U (enrdf_load_stackoverflow) * 1977-08-10 1979-03-05
JPS5473529A (en) * 1977-11-24 1979-06-12 Fujitsu Ltd Bonding pad forming method for bubble memory chip
JPS5547779U (enrdf_load_stackoverflow) * 1978-09-25 1980-03-28
JPS5523190Y2 (enrdf_load_stackoverflow) * 1975-09-23 1980-06-02
JPS5778651U (enrdf_load_stackoverflow) * 1980-10-30 1982-05-15

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5523190Y2 (enrdf_load_stackoverflow) * 1975-09-23 1980-06-02
JPS5433422U (enrdf_load_stackoverflow) * 1977-08-10 1979-03-05
JPS5473529A (en) * 1977-11-24 1979-06-12 Fujitsu Ltd Bonding pad forming method for bubble memory chip
JPS5547779U (enrdf_load_stackoverflow) * 1978-09-25 1980-03-28
JPS5778651U (enrdf_load_stackoverflow) * 1980-10-30 1982-05-15

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61236148A (ja) * 1985-04-11 1986-10-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション メタライゼーシヨン・パターンへのろう付け方法
JPS6263454A (ja) * 1985-09-14 1987-03-20 Narumi China Corp 半導体装置用容器及びその製造方法
JPS62211805A (ja) * 1986-03-12 1987-09-17 富士通株式会社 グリ−ンシ−ト多層セラミツク基板の製造方法
JPH0388354A (ja) * 1989-08-31 1991-04-12 Ibiden Co Ltd 半導体パッケージ
JPH0846121A (ja) * 1995-08-09 1996-02-16 Hitachi Ltd 樹脂封止型半導体装置
JPH0846120A (ja) * 1995-08-09 1996-02-16 Hitachi Ltd 樹脂封止型半導体装置およびその製造方法

Also Published As

Publication number Publication date
JPS636143B2 (enrdf_load_stackoverflow) 1988-02-08

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