JPS587833A - 回路装置組立体 - Google Patents

回路装置組立体

Info

Publication number
JPS587833A
JPS587833A JP57081724A JP8172482A JPS587833A JP S587833 A JPS587833 A JP S587833A JP 57081724 A JP57081724 A JP 57081724A JP 8172482 A JP8172482 A JP 8172482A JP S587833 A JPS587833 A JP S587833A
Authority
JP
Japan
Prior art keywords
substrate
layer
circuit chip
solder
chip device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57081724A
Other languages
English (en)
Inventor
サムナス・バタチヤリア
ニコラス・ジヨ−ジ・ク−プマン
ポ−ル・アンソニ−・トツタ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS587833A publication Critical patent/JPS587833A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、絶縁体基板と薄膜装置との間に相互接続を形
成するだめの手段に係る。
本発明の目的は、絶縁体基板と薄膜装置とを相互接続す
るための改良された手段を提供すふことである。
薄膜を用いて形成された回路チップ装置と基板との組立
体は、一般的にはんだ付は又は硬ろう付けによる相互接
続を含んでいる。今日知られている薄膜回路組立体に於
ては、例えばスパッタされた二酸化シリコン、アルミナ
、セラミック、又はガラスから形成され得る絶縁体基板
上に、薄膜複合金属によって引張り応力が加えられる。
その様な応力は、特に基板がもろい材料から成る場合に
、基板表面に亀裂又はスポーリング（ｓｐａ　Ｉ　Ｉ　
ｉｎｇ）を生じ得る。それらの応力は又、上記表面に引
張り応力を予め与えておくことにもなシ、異なる膨張、
熱サイクル、又は衝撃から誘起される応力の如き、小さ
な応力が更に加えられた場合には、上記表面が容易に破
壊されることになる。
本発明に於て、始めは許容範囲内であった応力が、はん
だ又は硬ろうの合金の付着後、はんだと端子金属との界
面に金属間化合物が形成されることによって、著しく変
化し得ることが解っへ薄膜金属の変換によシ形成された
上記金属間化合物は、該金属間化合物が形成された構成
要素の金属とは全く異なる構造、容量及び膨張率を有す
る。その１つの例は、スパッタされた二酸化シリコン絶
縁体上に鉛−錫のはんだパッド及びクロム−銅−金の端
子金属（ｍｅｔａｌｌｕｒｇｙ）を用いている、チップ
装置と基板との組立体である。蒸着されたときは、その
様な構造体は安定であるが、装置が再溶融及び結合され
た後には、構造的変化が生じる。
下の二酸化シリコンに極めて亀裂を生じ易くする程の応
力を予め加えておくことになる。
更に、本発明に於て、最終的な端子の構造は、該装置に
於ける始めの端子構造に依存しないだけでなく、基板に
も依存しないことが解った。例えば、基板の端子からの
Ａｕの如き元素は、再溶融及び固体化の際に、溶解して
チップ端子へと移動しそしてＡｕ５ｕ又はＡｕＣｕ５ｎ
の金属間化合物としてエピタキシャルに固体化し得る。
従って、形成される接続部が安定であるためには、その
最終的な量及び分布並びに応力レベルが規定される必要
がある。これを達成するために最も簡単且つ最も有効な
方法は、始めの端子及びはんだに於ける銅及び金の全体
量を制限することであり、従ってそれらが反応及び移動
するとき、それらのすべてが１つの端子に集中した場合
であっても、応力の問題を生じる程の金属間化合物は存
在していない。
最終的な金属間化合物の分布が重要であることが解った
ので、上記問題に対する他の解決方法が考えられ得る。
例えば、再溶融及び結合のために極めて短かいサイクル
時間を用い５ることによって、形成される金属間化合物
の量を制限する方法が試みられ得る。しかしながら、こ
の方法は、その様な迅速なサイクルが達成された場合に
は極端な熱衝撃が生じる点で、非実際的である。又、Ｐ
ｄの如き他の元素を接続部に加えることによって、多く
の再溶融により誘起されたスポーリング又は溶液により
助長されたスポーリングにより金属間化合物を解体し得
る。更に、応力が問題にならないことがある接続部の冷
たい側（多層セラミックの側）に応力形成元素をドライ
ブするために、パッドが溶融される間、温度勾配を与え
ることも可能である（第３図参照）。
次に、図面を参照して、本発明をその好実施例について
詳細に説明する。第１図に於て、多層セラミックの如き
基板１２０表面上に導体１０のノくターンが形成されて
いる。その導体ノ（ターンは半導体回路チップ装置１４
を受取るための接続点を有し、例えばモリブデンから形
成され得る導体１０が周知の方法で端子（ＮｉＡｕ）５
２に接続されている。
各回路チップ装置１４の製造中に、オーム接点を設ける
ために、アルミニウム・ランド１８が該回路チップ装置
の各半導体領域上に付着される。
次に、周囲雰囲気から保護するために、回路チップ装置
１２０表面上体にＳｉｏ２層２０が付着される。後の金
属化工程のためにアルミニウム・ランド１８が露出され
る様に、貫通孔２２が上記ランド１８の真上に於てＳｉ
ｏ２層２０中２０中される。
この実施例に於ては、金属化工程は、アルミニウム・ラ
ンド１８に電気接点を設けるために、クロム層２４、銅
層２６及び金層２８の連続的薄膜層を真空付着すること
を含む。１２００乃至１８００んの厚さを有するクロム
層２４は接着剤として働き、ガラス−金属間を封止して
、該接点領域を周囲雰囲気から保護する。銅層２６及び
金層２８は、クロム層２４への金属の付着を可能にする
。
それから、鉛及び錫から形成された略１２５μｍの全体
の厚さを有するはんだの山３０が、金層２８に接触する
様にマスクを経て真空付着される。はんだの山３０は、
回路チップ装置１４と導体１０のパターンとの間に良好
な機械的及び電気的相互接続を達成するとともに、回路
チップ装置１４と基板１２との間を離隔させる様に働（
。
はんだの山３０が真空付着された後、そのはんだの山が
再溶融される様に組立体全体が焼成される。その結果、
比較的小さい応力を受けていた銅層２６及び金層２８が
、Ｃｕ３Ｓｎ、　Ａｕｔｕｍｎ、及びＡｕＳｎの如き、
Ａｕ及び（ｕとＳｎとにより形成された金属間化合物の
極めて大きな応力を受ける層２９に変換される。それか
ら、回路チップ装置１４が基板に適切に結合され得る様
に、基板１２が清浄化されそして導体１００〕（ターン
にフラノクス処理が施される。回路チップ装置が再溶融
処理により基板に融着され、それからはんだを固体化す
るために熱サイクルの終りに基板が冷却され・′る。
本発明の実施に於ては、銅層２６が８００乃至２　ｓ　
ｏ　ｏ　叉゛の範囲の厚さに付着される。本発明に於て
、金属間化合物をエピタキシャル付着しそして変換され
たはんだ付けされ得る膜表面上に隣接して残され得る、
Ａｕ、　Ｃｕ及びＳｎ　の如き元素の量を制限すること
により、即ち銅層及び金層の厚さを規定された厳密な範
囲内に薄く形成することにより、はんだの再溶融及び基
板への回路チップ装置の結合の結果鋼層及び金層の変換
とともに生じる金属間応力が実質的に減少され又は除去
されることが解った。銅層な８００乃至２　ｓ　ｏ　Ｏ
Ｘ−の厚さに付着することによって、石英の絶縁体に於
ける亀裂が相当に減少される。更に、相互接続を強化す
るために、金層２８は基板中の他のすべてのＡｕととも
に、２５００Ｘ′以下の全体的厚さに形成される。
た層の厚さに制限することによって、回路チップ装置を
支持するために用いられた基板の亀裂の発生に於て著し
い減少が達成された。
半導体回路チップ装置を基板にはんだ接続する間に生じ
得る基板の亀裂を防ぐための他の方法は、金属間化合物
をスポール・オフさせそして再溶融を延長することによ
りその材料をはんだ中に分散させる方法である。しかし
ながら、この方法は、回路チップ装置と基板との間の相
互接続に於て銅及び金の量を制御する方法程、有効では
ない。
第３図に於て、５ｊｏ２に応力を加える金属間化合物の
厳密な位置が領域Ａに示されている。金属間化合物が領
域Ｂ又はＣに存在する場合には、応力の問題は何ら生じ
ない。
以上に於て、本発明をその特定の好実施例について説明
したが、本発明は何らそれらによって限定されないこと
を理解されたい。例えば、多くのはんだ付は及び硬ろう
付は操作に於て生じる如く、実質的に液状の他の金属と
反応し、そしてエピタキシャル付着して基板に隣接して
残される硬くもろい表面を形成する、接続部中のすべて
の金属が、該接続部及び絶縁体に亀裂を生ぜしめる程の
応力を予め加え得る。その様な亀裂を防ぐために、該接
続部に於けるその様な材料の量を制限する必要かめるこ
とが解った。
【図面の簡単な説明】
第１図は導体のパターンが形成されている超小型誘電体
基板を示す平面図、第２図は再溶融される前のはんだの
山を有しているチップ装置を部分的に破断して示す断面
図、第３図は本発明によるチップ装置と基板との完全な
接続を示す断面図でるる。 １０・・・・導体、１２・・・・絶縁体基板、１４・・
・・回路チップ装置、１８・・・・アルミニウム・ラン
ド、２０・・・・ＳｔＯ層、２２・・・・貫通孔、２４
・・・・クロム層、２６・・・・銅層、２８・・・・金
層、２９・・・・金属間化合物層、５０・・・・はんだ
の山、３２・・・・端子（Ｎ　ｉ　Ａ　ｕ　）。 −１（

Claims (1)

  1. 【特許請求の範囲】 絶縁体基板と、 上記基板上に形成された導体のパターンと、上記導体の
    パターン上に付着されたはんだ付は可能な金属手段と、 上記導体に電気的に接続される様に上記基板に結合され
    た回路チップ装置とを有し、 上記のはんだ付は可能な金属手段が、金属間応力が最小
    にされる様な所定の厚さを有している、回路装置組立体
    。
JP57081724A 1981-06-30 1982-05-17 回路装置組立体 Pending JPS587833A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27893081A 1981-06-30 1981-06-30
US278930 1981-06-30

Publications (1)

Publication Number Publication Date
JPS587833A true JPS587833A (ja) 1983-01-17

Family

ID=23066992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57081724A Pending JPS587833A (ja) 1981-06-30 1982-05-17 回路装置組立体

Country Status (3)

Country Link
EP (1) EP0068091B1 (ja)
JP (1) JPS587833A (ja)
DE (1) DE3278896D1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01308167A (ja) * 1988-05-31 1989-12-12 Shindengen Electric Mfg Co Ltd Ｄｃ−ｄｃコンバータ
JP2002280417A (ja) * 2001-01-15 2002-09-27 Nec Corp 半導体装置及びその製造方法並びに半導体製造装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3788263T2 (de) * 1986-09-25 1994-03-24 Toshiba Kawasaki Kk Verfahren zum elektrischen Verbinden von zwei Objekten.
US5118584A (en) * 1990-06-01 1992-06-02 Eastman Kodak Company Method of producing microbump circuits for flip chip mounting
CA2075462C (en) * 1992-01-27 1999-05-04 George Erdos Bump structure and method for bonding to a semi-conductor device
DE102005040686A1 (de) * 2005-08-26 2006-11-16 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5123074A (ja) * 1974-08-21 1976-02-24 Hitachi Ltd
JPS567482A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Manufacturing of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4113578A (en) * 1973-05-31 1978-09-12 Honeywell Inc. Microcircuit device metallization
CA1122856A (en) * 1978-09-20 1982-05-04 Nicholas G. Koopman Process for in-situ modification of solder composition
US4434434A (en) * 1981-03-30 1984-02-28 International Business Machines Corporation Solder mound formation on substrates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5123074A (ja) * 1974-08-21 1976-02-24 Hitachi Ltd
JPS567482A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Manufacturing of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01308167A (ja) * 1988-05-31 1989-12-12 Shindengen Electric Mfg Co Ltd Ｄｃ−ｄｃコンバータ
JP2002280417A (ja) * 2001-01-15 2002-09-27 Nec Corp 半導体装置及びその製造方法並びに半導体製造装置
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0068091A3 (en) 1984-11-14
EP0068091A2 (en) 1983-01-05
DE3278896D1 (en) 1988-09-15
EP0068091B1 (en) 1988-08-10

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