JPS5871646A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS5871646A JPS5871646A JP56171641A JP17164181A JPS5871646A JP S5871646 A JPS5871646 A JP S5871646A JP 56171641 A JP56171641 A JP 56171641A JP 17164181 A JP17164181 A JP 17164181A JP S5871646 A JPS5871646 A JP S5871646A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- ceramic substrate
- semiconductor device
- semiconductor
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56171641A JPS5871646A (ja) | 1981-10-24 | 1981-10-24 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56171641A JPS5871646A (ja) | 1981-10-24 | 1981-10-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5871646A true JPS5871646A (ja) | 1983-04-28 |
JPS6224948B2 JPS6224948B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1987-05-30 |
Family
ID=15926965
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56171641A Granted JPS5871646A (ja) | 1981-10-24 | 1981-10-24 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5871646A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58127357A (ja) * | 1981-12-31 | 1983-07-29 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 集積回路チツプ・モジユ−ル |
JPS63102399A (ja) * | 1986-10-20 | 1988-05-07 | 富士通株式会社 | 多層プリント配線基板 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0516106U (ja) * | 1991-08-05 | 1993-03-02 | 株式会社小松製作所 | 切粉処理装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5030474A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1973-07-17 | 1975-03-26 |
-
1981
- 1981-10-24 JP JP56171641A patent/JPS5871646A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5030474A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1973-07-17 | 1975-03-26 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58127357A (ja) * | 1981-12-31 | 1983-07-29 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 集積回路チツプ・モジユ−ル |
JPS63102399A (ja) * | 1986-10-20 | 1988-05-07 | 富士通株式会社 | 多層プリント配線基板 |
Also Published As
Publication number | Publication date |
---|---|
JPS6224948B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1987-05-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5394303A (en) | Semiconductor device | |
US7009293B2 (en) | Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument | |
JPS5839048A (ja) | フレキシブル領域接着テ−プ | |
EP0318209B1 (en) | Interconnection technique using dielectric layers | |
JPH04273451A (ja) | 半導体装置 | |
JP2001177050A (ja) | 半導体装置 | |
TW200421587A (en) | Multi-chip module | |
US4731700A (en) | Semiconductor connection and crossover apparatus | |
JPS5871646A (ja) | 半導体装置 | |
CN110112113B (zh) | 半导体封装件 | |
JPS60105269A (ja) | ハイブリツド回路の製造方法 | |
JPS59222947A (ja) | 半導体装置およびその製造方法 | |
JPH02230749A (ja) | 半導体チップ及び該チップを用いた半導体装置 | |
JPH01309362A (ja) | マルチチツプ半導体装置 | |
JP2001085600A (ja) | 半導体チップ、マルチチップパッケージ、半導体装置、並びに電子機器 | |
JPH05343602A (ja) | 高集積半導体装置及びそれを用いた半導体モジュール | |
TW200910573A (en) | Stacked semiconductor package structure with metal contact through via | |
JPS60220939A (ja) | 半導体集積回路装置 | |
JP2970595B2 (ja) | Bga型半導体装置 | |
CN1332445C (zh) | 一种高频集成电路多排线打线结构 | |
JPS58184735A (ja) | 集積回路チツプ | |
TWI314030B (en) | Method for making cable with a conductive bump array, and method for connecting the cable to a task object | |
JPS6240734A (ja) | 半導体装置 | |
CN116960091A (zh) | 芯片结构、芯片制造方法和固态硬盘 | |
KR100381844B1 (ko) | 반도체패키지용써킷테이프 |