JPS5854496B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the shape of a mask alignment pattern and means for mask alignment in a semiconductor manufacturing process.

An object of the present invention is to facilitate the mask alignment process in semiconductor manufacturing, reduce the mutual deviation between semiconductor constituent patterns accumulated in each mask alignment process, and improve precision in the manufacturing process. The present invention relates to a semiconductor manufacturing process that aims to achieve this.

Generally, in the mask alignment process, a pattern as shown in Figure 1a is formed on the layer manufactured in the following process, and the mask alignment process as shown in Figure 1 is included in the mask used in the process of forming the next layer. Alignment between each layer is achieved by overlapping the patterns.

The pattern shape for mask matching in the conventional mask matching process has a shape as shown in FIG. Then, the pattern 4 that is mounted on the third mask is superimposed on the pattern 3 that is simultaneously formed on the semiconductor device using the second mask, and the mask alignment of the third mask is performed. Similarly, mask alignment of the fourth, fifth, etc. masks is performed.

However, if this method is used, since all the mask alignment patterns in each mask alignment process have the same shape, it becomes unclear to determine the mask alignment position in the process operation, and it is difficult to confirm by comparing with the internal semiconductor configuration pattern. This results in a decrease in work efficiency.

On the other hand, as a preventive measure, a pattern for mask alignment is formed at the same location as shown in FIG. 3 in order to compensate for the drawbacks mentioned above.
A method is also used in which a pattern 10 included in a second mask is superimposed on a pattern 9 formed by the first mask, and a pattern 11 included in a third mask is sequentially superimposed on the pattern 10.

However, since the mask alignment means simply performs mask alignment based on the pattern formed by the mask used in the previous step, errors due to deviations that occur in each mask alignment as the manufacturing process progresses are accumulated,
The worst value of the cumulative error is (error caused by one mask alignment) x (total number of masks - 1).

As a specific example, a part of the manufacturing process of a complementary MO8 field effect transistor will be described.

A complementary MO8 field effect transistor generally has a structure as shown in FIG. 4. In order to obtain the structure shown in FIG. 7 to form each of the N+ diffusion layer 15 forming the channel source/drain, the gate insulating layer 16, the contact portion 17 between the diffusion layer and the metal electrode, the metal electrode 18, and the window opening on the input/output butt of the surface protection film. Since the N+ diffusion layer usually has a smaller diffusion coefficient than the P10 diffusion layer, it is assumed that the N+ diffusion layer is formed after the P10 diffusion layer and that each is formed in the above order.

As mentioned above, during mask alignment in the conventional complementary MO8 field effect transistor manufacturing process, the mask used in any manufacturing process is simply the mask formed by the mask used one step before the process. Since mask alignment is performed using the alignment pattern as a reference, when manufacturing the MO8 field effect transistor, the mask used as a reference for mask alignment when forming the P-channel source/drain diffusion layer 14 is the mask that forms the N-channel substrate 13. It is a mask with a pattern that
The mask alignment standard when forming the drain diffusion layer 15 is a mask having a pattern for forming the P channel source/drain diffusion layer 14, and the mask alignment standard when forming the gate insulating layer 16 &^N channel source/drain diffusion layer 14. This is a mask having a pattern for forming a drain diffusion layer 15.

Since mask alignment is similarly performed in all subsequent steps using the mask used one step before the step as a reference, errors occurring in each mask alignment can be accumulated.

As an example, if we consider the case where the channel part consisting of the source/drain diffusion layer 14, the gate insulating layer 16, and the metal electrode 18 is arranged as shown in FIG. If a deviation occurs in one direction during the alignment process, the error due to the deviation will accumulate and result in a 5th error in the pattern design, as shown in Figure 6.
As shown in the figure, it is not possible to obtain the considered overlap between the source/drain diffusion layer 14 and the metal electrode 18, making it difficult to form a channel.

Therefore, in order to improve the semiconductor production yield, it is necessary to design a pattern with a margin in consideration of the accumulated errors caused by the alignment accuracy, which is a cause of a decrease in the degree of integration and further a decrease in productivity.

The present invention eliminates such drawbacks, and uses a pattern for mask alignment having a shape as shown in FIG. 8 as an example.
A method is adopted in which the pattern shown in the figure is overlapped with the pattern formed as shown in the figure a, and as shown in Figure 9, each mask alignment has a different shape, and in the mask alignment process, the shape The work efficiency of this process is improved by clearly determining the position at which the parts should be overlapped.

Furthermore, the advantage of the shape of the mask matching pattern according to the present invention as shown in FIGS. 8 and 9 is that not only can masks be matched on the outside edges of the pattern, but also masks can be matched on the inside edges. This facilitates mask alignment operations and improves alignment accuracy.

Another form of the mask matching pattern according to the present invention is a number shape as shown in FIG. It becomes easy to determine the alignment position in the process, and at the same time, it becomes possible to confirm the mask to be used.

However, the same result can be obtained by making the pattern not in the form of numbers but in the form of letters and using letters that indicate the type of mask.

On the other hand, the method of mask alignment according to the present invention in the manufacturing process of complementary MO8 field effect transistors uses the pattern shown in FIG. According to the process of manufacturing an effect transistor, the mask used for forming the P channel source/drain diffusion layer is aligned with the pattern included in the mask for forming the first ON channel substrate, and the N After the step of forming the channel source/drain diffusion layer, the third to seventh masks are all performed using the mask alignment pattern formed by the second mask as a reference.

Therefore, errors caused by the alignment operations in the first to seventh steps can be accumulated, and as a result, the alignment accuracy in manufacturing the transistor is improved, there is no need to take an excessive margin in the design, and the design is improved. The degree of freedom increases and the degree of integration can be improved.

As a specific example, in the arrangement shown in FIG. 5 in the previous example, when forming the gate insulating layer 16 as shown in FIG. 7, the mask that serves as the reference for mask alignment is the source/drain diffusion layer This mask has a pattern for forming the metal electrode 14, and also when forming the metal electrode 18, the source
Since the mask having the pattern for forming the drain diffusion layer 14 is used as a reference, even if the maximum deviation occurs in each mask alignment process, errors due to the deviation will not be accumulated.
A predetermined pattern configuration can be obtained by designing with a margin for error in one process.

Adopting the shape of the mask matching pattern according to the present invention,
Furthermore, in manufacturing complementary MO8 field effect transistors, by using the second mask as a reference for mask alignment, work efficiency in the mask alignment process can be improved, and the degree of integration can be improved.
Furthermore, productivity can be improved.

The present invention is effective not only for manufacturing complementary MO8 field effect transistors, but also for all semiconductor devices requiring at least three different types of masks.

Furthermore, since the present invention uses different shapes and numbers for each process, it has the advantage that it is possible to quickly find out which of the plurality of patterns formed on the wafer should be matched.

[Brief explanation of the drawing]

Figure 1 shows the shape of a conventional mask alignment pattern. Figure 2 shows an example of a conventional mask alignment method. Figure 3 shows
Another example of traditional mask matching method. FIG. 4 is a structural cross-sectional view of a general complementary MO8 field effect transistor. FIG. 5 is an example of a layout diagram of source/drain diffusion layers and gate metal in the channel portion of a complementary MO8 field effect transistor. FIG. 6 shows a channel portion in FIG. 5 that has been misaligned due to conventional mask alignment means. FIG. 7 shows the channel portion in FIG. 5 when using the mask alignment means according to the present invention. FIG. 8 shows the shape of a pattern for mask alignment according to the present invention. FIG. 9 shows a mask matching method with different shapes according to the present invention. FIG. 10 shows a mask matching method with numbers according to the present invention. 1.9...Mask alignment pattern formed by the first mask. 2, 3.10... Mask alignment pattern formed by the second mask. 4゜5.11...Mask joining pattern formed by the third mask. 6, 7.12... Mask alignment pattern formed by the fourth mask. 8... Mask alignment pattern formed by the fifth mask. 13...N channel substrate. 14...P diffusion layer forming a P channel source/drain. 15...N-channel source/drain diffusion layer. 16...Gate insulating layer. 17... Junction between the diffusion layer and the metal electrode. 18...Gold layer electrode. 19...Insulating layer.

Claims (1)

[Claims] 1. In a semiconductor manufacturing method in which a semiconductor is manufactured using a plurality of different masks, a first mask is used to form a pattern shape for mask alignment into a plurality of shapes corresponding to the number of subsequent masks. , each of the plurality of pattern shapes is formed in a different shape, and each mask matching pattern included in a subsequent mask performs mask matching by overlapping each of the plurality of pattern shapes. A method for manufacturing semiconductors. 2 Click on the method for manufacturing a semiconductor forming a complementary transistor, perform mask alignment of the second mask using the mask alignment pattern formed by the first mask as a reference, and form the shape of the mask alignment pattern using the second mask. A plurality of patterns are formed corresponding to the number of subsequent masks, the shape of the plurality of patterns is formed by a number corresponding to the order of each mask, and each mask combination pattern included in the subsequent masks is formed according to the number of the plurality of masks. A method for manufacturing a semiconductor device, characterized in that mask alignment is performed by overlapping each number in a pattern shape.