JPS60263433A - Alignment mark for semiconductor device - Google Patents

Abstract

PURPOSE:To attempt reduction in an area occupied by marks by using a same alignment mark on each chip in two layer masks. CONSTITUTION:A mark 2B on a chip and a mark 217 on a mask are used for alignment of a No.2 mask and a No.1 mask. In this time, marks 236 and 245 are simultaneously formed on the chip for alignment after this. Next, a No.3 mask is aligned using the mark 236 on the chip and a mark 3A on the mark. A No.4 mask is aligned using the mark 245 on the chip and a mark 4B on the mask. A No.5 mask is aligned using the mark 245 and a mark 5B on the mask. A No.6 mask is aligned using the mark 236 and a mark 6B on the mask with them shifted by half the deviation between the mark 236 and the mark 3B while observing thereof. A No.7 mask is aligned using the mark 217 on the chip and a mark 7B on the mask. In this way, masks for two layers are aligned by utilizing the inside and the outside of the mark.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of alignment marks contained in each chip used when aligning a wafer and a mask in the manufacturing process of semiconductor devices.

Conventionally, one mark on the chip corresponded to one mark on one mask. For this reason, as the number of processes increases, as in recent manufacturing processes, the number of marks increases, and the area occupied by the marks also increases. For example, basic P-MOEi engineering a
uses 5 masks, but the recent 0-M08IC uses 10 or more masks even in Ryolumigate. For this reason, the number of marks increased from 4 to more than 9 in response to the increase.
The area occupied by the mark has also become so large that it cannot be ignored.

Below is a simple Rumi game)0-MO8工Ot- example, *
A conventional embodiment will now be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of the generally known 0-MO8 process C. FIG. 2 shows nine examples using conventional alignment marks.

P = WsAtl is the first mask, the source 21 and drain 22U of the P channel transistor C (abbreviated as Tr)
No. 2 mask, source 31, drain 3 of N-channel Tf
2 is the No. 8 mask for gate oxidation, @4 is the No. 4 mask) The contact hole 5 is the No. 5 mask, the gate 61 of the P channel Tγ and the gate 62 of the N channel Tr, etc. are the No. 6 mask, and the electrode exit is the No. 6 mask. I decided to butter it using mask number 7. In the conventional alignment mark, alignment mark IA is formed on the chip during patterning of the first mask.

To align the 2nd mask and the 1st mask, use the alignment mark IA on the chip and the alignment mark 21A on the 2nd mask.
This is done by matching k. After this time IN
Alignment marks 13A, Z4A, 25 for alignment
A, 26A, and 27A are also formed on the chip at the same time.

Next, the No. 8 mask is aligned using the alignment mark 23A on the chip and the IW alignment mark 3Ai on the mask. Mask number 4 is the alignment mark 24 of the tip.
Alignment is performed using A and alignment mark 4A-i on the mask. Mask number 5 is alignment mark 25 on the chip.
Alignment is performed using the alignment mark 26A on the chip and the alignment mark 5A' (,-) on the mask. For mask No. 6, alignment is performed using the alignment mark 26A on the chip and the alignment mark 6h-2 on the mask.7 The mask is aligned using the alignment mark 27A on the chip and the alignment mark 7A-i on the mask. An example of alignment marks is shown in Fig. 2.The number of marks formed on a chip in this way is generally (N-1), where the number of masks used for etching is iN.
The area occupied by the mark increases as the building C becomes taller.

The present invention addresses these drawbacks, and FIG. 8 shows alignment marks on a chip according to an embodiment of the present invention. In the first mask, a mark IB' is formed on the chip. The positioning of the second mask and the first mask is performed using the mark IB on the chip and the mark 217 on the mask. At this time, marks 286 and 245 are also formed on the chip at the same time for subsequent alignment.

Next, mask number 8 is mark 286 on the chip and mark 8B' on the mask! Perform alignment using r. Mask number 4 has mark 245 on the chip and mark 4Bff on the mask.
: Use to perform alignment. Mask No. 5 performs alignment using mark 245 on the chip and mark 5Bi on the mask. For the No. 6 mask, alignment is performed by using the mark 286 on the chip and the mark 6B'ic- on the mask, and while checking the deviation between the mark 286 and the mark 8B, shift by half of the deviation. Mask number 7 is mark 2 on the chip
17 and marks 7B-j on the mask for alignment. By aligning the masks in this manner, it is possible to align two scrap masks using the inside and outside of the alignment mark on one chip. For this reason, the area occupied by the alignment marks on the chip is halved, as can be seen from FIGS. 2 and 8. Also, as in this embodiment, when aligning the No. 6 mask f and the No. 2 mask, while checking the deviation of the No. 8 mask with respect to the No. 2 mask, consider the deviation and correct it while aligning.
By performing P-channel Tr and N-channel Tr
Both improve the integrity of the gate, source and drain,
All the shortcomings of aluminum gate can be improved.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a general 0-MO8Ryo Lumigate C, Fig. 2 is a plan view showing an embodiment of a conventional alignment mark, and Fig. 8 is a plan view showing an embodiment of the alignment mark of the present invention. It is a diagram. 1,, P-WetL 5-21°, source 22 of P-channel Tr. Drain 31 of the P-channel 'rr. N-channel Tr source 32, N-channel Tr drain 4°. Gate oxide film 5. Contact hole 61°. Getat electrode of P channel transistor 62°. Gate electrodes 12A, 23A- of N-channel transistors
27 is two reference alignment marks for mask alignment - 7A is alignment mark aligned with the reference mark 217, 286, 246 is reference alignment mark for mask alignment 2B - 7B are alignment marks aligned with the reference mark Person Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Tsutomu Mogami 61

Claims (2)

[Claims] (1) An alignment mark for a semiconductor device, characterized in that the same alignment mark in each chip is used in a two-layer mask in the manufacture of a semiconductor device. (2) The semiconductor device according to claim 1, wherein the semiconductor device is configured to be able to correct the mask alignment in the subsequent step without checking for the deviation in the previously performed alignment. alignment marks.