JPS5963728A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5963728A
JPS5963728A JP57175036A JP17503682A JPS5963728A JP S5963728 A JPS5963728 A JP S5963728A JP 57175036 A JP57175036 A JP 57175036A JP 17503682 A JP17503682 A JP 17503682A JP S5963728 A JPS5963728 A JP S5963728A
Authority
JP
Japan
Prior art keywords
exposure mask
mark
alignment mark
mask
alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57175036A
Other languages
Japanese (ja)
Inventor
Kazuhiko Hotta
和彦 堀田
Takeshi Umegaki
梅垣 武士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP57175036A priority Critical patent/JPS5963728A/en
Publication of JPS5963728A publication Critical patent/JPS5963728A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To perform positioning of high accuracy by using the first exposure mask and the second exposure mask which has a projected part extending from the reduced main part and the main part of an alignment mark for the former mask over the alignment mark. CONSTITUTION:The alignment mark 4 for the second exposure mask 7 is projected out of the algnment mark 5 for the first exposure mask 6 at the parts 10, and is small except them. The mark 4 is made to coincide, by the mark 5 for the mask 6, with a target mark formed on a semiconductor substrate. In other words, the center 8 of the mark 5 is made to agree with the center 9 of the mark 4. When the dimensional difference between the target mark on the semiconductor substrate and the projected parts 10 are determined with high accuracy, the masks can be superposed with high accuracy by the projected parts 10. Besides, the using order of the first and second masks can be exchanged to each other.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は写真蝕刻作業を複数回必要とする半導体装置の
製造方法、さらに詳しくは、複雑且つ高精度の露光マス
クの位置合わせが要求される半導体装置に使用される合
わせマークを有する露光マスクを用いる製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device that requires multiple photo-etching operations, and more specifically, to a method of manufacturing a semiconductor device that requires complex and highly accurate alignment of an exposure mask. The present invention relates to a manufacturing method using an exposure mask having alignment marks used in

従来例の構成とその問題点 一般に、半導体装置の製造技術では、たとえばバイポー
ラトランジスタの例でみると、ベース拡散、エミッタ拡
散、コンタクト孔形成、電極配線等を行うために上記し
た各工程で写真蝕刻作業を行い、その度に各工程の異な
る露光マスクを用い半導体基板と位置合わせをする必要
がある。
Conventional Structures and Problems In general, in the manufacturing technology of semiconductor devices, for example, in the case of bipolar transistors, photolithography is used in each of the above steps to perform base diffusion, emitter diffusion, contact hole formation, electrode wiring, etc. Each time the work is performed, it is necessary to align the position with the semiconductor substrate using a different exposure mask for each process.

従来の各工程の多数種の露光マスクを位置合わせする方
法を、第1図および第2図を用いて説明する。先ず、第
1番目の露光マスクを用いて写真蝕刻処理を行うと、第
1図に示すよう忙、半導体基板表面の絶縁膜1に径小な
四角形の第1孔2が形成される。次にこの第1孔2を基
準にして第2番目の露光マスクの合わせマーク3に合わ
せて、写真蝕刻処理を施す。このとき、第1図の場合は
合わせマーク3の外側の絶縁膜を残すためにはポジ型フ
ォトレジストをm−るが、合わせマーク3は第1孔2よ
り大きくしなければ第1孔2が見えなくなり合わせられ
ない。また、第2図の場合は第1孔2の外側の絶縁膜を
残すためにはネガ型フォトレジストを用い、次に第2番
目の露光合わせマーク3は第1孔2より小さくしなけれ
ば両マーク同士の目合わせができない。
A conventional method for aligning multiple types of exposure masks for each process will be explained using FIGS. 1 and 2. First, when a photolithography process is performed using a first exposure mask, a first rectangular hole 2 with a small diameter is formed in an insulating film 1 on the surface of a semiconductor substrate, as shown in FIG. Next, photolithography is performed using the first hole 2 as a reference and aligning it with the alignment mark 3 of the second exposure mask. At this time, in the case of Fig. 1, a positive photoresist is applied to leave the insulating film outside the alignment mark 3, but the alignment mark 3 must be made larger than the first hole 2. I can't see it and can't match it. In the case of FIG. 2, a negative photoresist is used to leave the insulating film outside the first hole 2, and the second exposure alignment mark 3 must be made smaller than the first hole 2. I can't make eye contact between the marks.

従来の露光マスクの合わせマークは上述のように、使用
するフォトレジストの型により大小関係が決定されるた
め、第2露光マスクを第1露光マスクより以前に使用す
ることが出来なかった。この欠点を除去するために、従
来、同一露光マスク上に複数個の合わせマークを有し、
それら合わせマークは次番の露光マスクの合わせマーク
とは大小関係を異にし、ひとつの合わせマークは第1マ
スクの合わせマークより大きく、他のひとつの合わせマ
ークは第1マスクの合わせマークより小さくしたものが
用いられてきた。しかしながら、この方法では合わせマ
ークが複数個を要し、合わせマーク用面積が増大する。
As described above, the size of the alignment marks on conventional exposure masks is determined by the type of photoresist used, so the second exposure mask cannot be used before the first exposure mask. In order to eliminate this drawback, conventionally, multiple alignment marks are provided on the same exposure mask.
These alignment marks were different in size from the alignment marks of the next exposure mask, one alignment mark was larger than the alignment mark of the first mask, and the other alignment mark was smaller than the alignment mark of the first mask. things have been used. However, this method requires a plurality of alignment marks, which increases the area for alignment marks.

発明の目的 本発明は上記の欠点に鑑みてなされたものであり、合わ
せマークが最小であり、且つ、第2露光マスクを第1露
光マスクより以前に使用しだい場合に於いて高精度にマ
スク合わせを行なうことを可能にした半導体装置の製造
方法を提供せんとするものである。
OBJECT OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and is capable of minimizing alignment marks and highly accurate mask alignment when the second exposure mask is used before the first exposure mask. It is an object of the present invention to provide a method for manufacturing a semiconductor device that makes it possible to perform the following steps.

発明の構成 本発明は、第1の露光マスクに付した合せマークに対し
て、第2の露光マスクの合せマークを、前記第1の露光
マスクの合せマークを比例縮少させた要部とこの要部か
ら前記第1の露光マスクの合せマークを越える寸度のは
み出し部とを有する露光マスクを用いることを特徴とす
る半導体装置の製造方法を提供するものである。この構
成によれば、第1および第2の露光マスクを重ねだとき
、相方の合せマークが縮少要部とはみ出し部とで互いに
内法、外法を形作るので、雨露光マスクの合せ順序を互
いに入れ替えて用いることも可能になる。
Structure of the Invention The present invention provides an alignment mark on a second exposure mask that is proportionally reduced in proportion to the alignment mark on the first exposure mask, and a main part in which the alignment mark on the first exposure mask is proportionally reduced. The present invention provides a method for manufacturing a semiconductor device, characterized in that an exposure mask having a protruding portion extending beyond the alignment mark of the first exposure mask from the main portion is used. According to this configuration, when the first and second exposure masks are overlapped, the alignment marks of the other pair form the inner and outer edges of the reduced main part and the protruding part, so the alignment order of the rain exposure masks can be changed. It is also possible to use them interchangeably.

実施例の説明 第3図は本発明実施例の露光マスクの合せマークの様相
を示すもので、第2の露光マスクの合せマーク4を、第
1の露光マスクの合せマーク6に重ねだものである。す
なわち、第2の露光マスクの合せマーク4は、第1の露
光マスクの合せマーク6に対して、その比例縮少要部4
aと、はみ出し部4bとをもったものである。
DESCRIPTION OF THE EMBODIMENTS FIG. 3 shows the alignment mark of the exposure mask according to the embodiment of the present invention, in which alignment mark 4 of the second exposure mask is superimposed on alignment mark 6 of the first exposure mask. be. That is, the alignment mark 4 of the second exposure mask is proportionally reduced with respect to the alignment mark 6 of the first exposure mask.
a and a protruding portion 4b.

第4図と第6図は本発明の一実施例である露光マスクの
重ね合わぜを示す図であり、第4図において6は第1の
露光マスクであり、7は第2の露光マスクである。第5
図は第4図で使用した各露光マスクと同一であり、重ね
合わせ順序を逆にしだものである。
4 and 6 are diagrams showing the overlapping of exposure masks according to an embodiment of the present invention. In FIG. 4, 6 is a first exposure mask, and 7 is a second exposure mask. . Fifth
The figure is the same as each exposure mask used in FIG. 4, but the overlapping order is reversed.

まず、第4図(a)は第1の露光マスク6の合せマーク
部分を示し、合わせマーク6に対応しだ半導 。
First, FIG. 4(a) shows the alignment mark portion of the first exposure mask 6, and the semiconductor layer corresponding to the alignment mark 6 is shown.

体基板上の合せヤーク、すなわち的マークは写真蝕刻法
によって形成する。マスク合せの操作は、同図(b)に
示す様に、第2の露光マスク7の合せマーク4を前記第
1の露光マスク6に付された合わせマーク6によって所
定半導体基板に蝕刻形成された的マークにマスク合わせ
を行なう。このと1第1露光マスク60合わせマーク6
の中心点8と第2露光マスク70合わせマーク4の中心
点9は同一点になっており、合わせマーク4は第1露光
マスク60合わせマーク5より、はみ出し部10がはみ
出し、これ以外は小さくなっている。このはみ出し部1
0は、半導体基板上の的マークとの差の寸法を高精度に
定めておくことにより、このはみ出し部1Qによって、
その的マークに対して高精度に重ね合わせることが可能
となる。
The alignment marks or target marks on the body substrate are formed by photolithography. The mask alignment operation is performed by etching the alignment mark 4 of the second exposure mask 7 onto a predetermined semiconductor substrate using the alignment mark 6 attached to the first exposure mask 6, as shown in FIG. Align the mask to the target mark. This and 1 first exposure mask 60 alignment mark 6
The center point 8 of the alignment mark 4 of the second exposure mask 70 and the center point 9 of the alignment mark 4 of the second exposure mask 70 are the same point. ing. This protruding part 1
0 is achieved by precisely determining the dimension of the difference from the target mark on the semiconductor substrate, and by this protruding portion 1Q,
It becomes possible to superimpose the target mark with high precision.

一方、第5図(a)は第4図(b)K示しだ第2露光マ
スクと同一のマスクであり、これを用いて、半導体基板
上に、この合わせマーク4と同形の的マークを写真蝕刻
法によって形成する。ついで、第5図(b)において、
第4図(2L)に示しだ第1露光マスク6と同一のマス
クを使用し、重ね合わせを行なう。
On the other hand, FIG. 5(a) is the same mask as the second exposure mask shown in FIG. 4(b)K, and using this mask, a target mark having the same shape as this alignment mark 4 is photographed on a semiconductor substrate. Formed by etching. Then, in FIG. 5(b),
Superposition is performed using the same mask as the first exposure mask 6 shown in FIG. 4 (2L).

このとき、第4図と同様に各マスク合わせマークの中心
点9,8は同一点になっている。この第5図(b)にお
いては合わせマークのはみ出し部分が11となり、この
はみ出し部11によって半導体基板上の的マークに高精
度に重ね合わせることが可能となる。
At this time, as in FIG. 4, the center points 9 and 8 of each mask alignment mark are the same point. In FIG. 5(b), the protruding portion of the alignment mark is 11, and this protruding portion 11 makes it possible to overlap the target mark on the semiconductor substrate with high precision.

なお、この実施例において、重ね合わせに使用するフォ
トレジストの型は何ら問題とはならない。
In this example, the type of photoresist used for overlaying does not matter at all.

発明の効果 以上のように本発明は、第1露光マスクと第2露光マス
クの重ね合わせ順序を逆にすることができるとともに高
精度に重ね合わせを行なうことが可能となり、すぐれた
実用的効果を有するものである。
Effects of the Invention As described above, the present invention makes it possible to reverse the overlapping order of the first exposure mask and the second exposure mask, and to perform overlapping with high precision, thereby achieving excellent practical effects. It is something that you have.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の露光マスクと的マークを重
ね合わせた平面図、第3図は本発明を実施例に適した第
1.第2露光マスクの合ぜマーク同士を重ね合わせた平
面図、第4図(a)(b)および第6図(a)(b)は
本発明の詳細な説明するだめの平面工程図である。 4.6・・・・・・露光マスクの合わせマーク、4a・
・・・・・比例縮少要部、4b・・・・・・はみ出し部
、6・・・・・・第1露光マスク、7・・・・・・第2
露光マスク、8,9・・・・・・合わせマークの中心点
、10,11・・・・・・合せマークのはみ出し部分。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図    第2図 第3図 第4図 第5図
1 and 2 are plan views in which a conventional exposure mask and a target mark are superimposed, and FIG. 3 is a plan view of a conventional exposure mask and a target mark, and FIG. A plan view of the alignment marks of the second exposure mask superimposed on each other, and FIGS. 4(a) and 6(b) and FIGS. 6(a) and 6(b) are planar process drawings that are not intended to explain the present invention in detail. . 4.6... Exposure mask alignment mark, 4a.
...Proportional reduction main part, 4b...Protrusion part, 6...First exposure mask, 7...Second
Exposure mask, 8, 9... Center point of the alignment mark, 10, 11... Protruding portion of the alignment mark. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 第1の露光マスクに付した合せマークに対して、前記第
1の露光マスクの合せマークを比例縮少させた要部とこ
の要部から前記第1の露光マスクの合せマークを越える
寸度の突出部とを有する構成の第2の露光マスクを用い
てマスク用合せすることを特徴とする半導体装置の製造
方法。
With respect to the alignment mark attached to the first exposure mask, a main part that is proportionally reduced in proportion to the alignment mark of the first exposure mask, and a part that exceeds the alignment mark of the first exposure mask from this main part. 1. A method for manufacturing a semiconductor device, characterized in that mask alignment is performed using a second exposure mask configured to have a protrusion.
JP57175036A 1982-10-04 1982-10-04 Manufacture of semiconductor device Pending JPS5963728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57175036A JPS5963728A (en) 1982-10-04 1982-10-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57175036A JPS5963728A (en) 1982-10-04 1982-10-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5963728A true JPS5963728A (en) 1984-04-11

Family

ID=15989091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57175036A Pending JPS5963728A (en) 1982-10-04 1982-10-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5963728A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS616824A (en) * 1984-06-20 1986-01-13 Nec Corp Alignment of semiconductor substrate
JPS61100817A (en) * 1984-10-22 1986-05-19 Canon Inc Positioning method
JPH0323618A (en) * 1989-06-21 1991-01-31 Matsushita Electron Corp Alignement of substrate with mask for exposure use
KR100801665B1 (en) 2006-12-24 2008-02-11 한국생산기술연구원 Machine vision system and method for align mark cognition

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS616824A (en) * 1984-06-20 1986-01-13 Nec Corp Alignment of semiconductor substrate
JPH0347570B2 (en) * 1984-06-20 1991-07-19 Nippon Electric Co
JPS61100817A (en) * 1984-10-22 1986-05-19 Canon Inc Positioning method
JPH0323618A (en) * 1989-06-21 1991-01-31 Matsushita Electron Corp Alignement of substrate with mask for exposure use
KR100801665B1 (en) 2006-12-24 2008-02-11 한국생산기술연구원 Machine vision system and method for align mark cognition

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