JPS62229923A - Metiod of forming mark on semiconductor chip - Google Patents

Abstract

PURPOSE:To provide marks at different positions of chips which are formed by dividing a wafer into the same shape efficiently by a method wherein a mask pattern in which patterns are arranged with a different pitch from the pitch of the chips is transcripted on the chips. CONSTITUTION:Coordinates graduation patterns 2 are arranged in 1st mask 1 with a pitch of 5000 mum. One graduation length of the coordinates pattern is 10 mum. This is the same as the pitch of the patterns on chips 8.The coordinates graduation patterns 2 are transcripted on semiconductor chips 8. The pitch of dots arranged on 2nd mask 3 is 5010mum. The mask patterns (dots 4) are transcripted on the chips. Marks (dots 5) are formed on the respective chips 8 at the positions different from each other and the respective positions on a semiconductor substrate 6 are indicated. For making the mask 3, one reticle is sufficient. Therefore, the manufacturing cost of the mask can be reduced. This is the same as the pitch of the patterns on chips 8.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an improvement in a method for forming marks that enable identification of semiconductor chips (hereinafter referred to as chips) that are divided and provided in the same shape on a semiconductor substrate. Regarding.

[Prior art]

In order to provide chips with the same shape on a semiconductor substrate and build the necessary circuits or functional elements there, so-called PEP is used.
The process is usually performed multiple times, and in this PEP process, a mask in which patterns of the same shape are arranged at a constant pitch in both the vertical and horizontal directions is used to transfer this mask pattern onto the semiconductor chip. method is adopted.

By the way, recent semiconductor devices, as typified by VLSI, are becoming more highly integrated and have higher performance.
i! The A-manufacturing process has become increasingly complex and varied, and the influence of the cleanliness of the manufacturing atmosphere on the yield has become extremely large. In addition to these manufacturing constraints,
Naturally, there is also a demand for improved reliability, and therefore it is naturally necessary to investigate the characteristics of functional elements or circuits formed on semiconductor chips.

From this point of view, the resistivity distribution in the semiconductor substrate,
Investigations of threshold voltages, current distributions, etc., as well as failure analysis are being carried out more frequently, and in this case, it would be more convenient if the position of each semiconductor chip on the semiconductor substrate was known. A known method for this purpose is to use a mask with a different display mark for each semiconductor chip, and to transfer the display mark through conventional exposure, development, and etching steps.

[Problem that the invention seeks to solve]

A reduction projection exposure device, or stepper, is usually used to create this mask, and specifically, a reticle with the required pattern is used to successively reduce and project the pattern of the reticle onto a mask coated with photoresist. A method of exposure is being used.

Therefore, in order to give different marks to each semiconductor chip, it is necessary to create reticles for the number of chips required, which has the drawback of inefficiency and, in other words, high cost.

[Means for solving problems]

In the present invention, a mask is prepared in which a pattern with a pitch different from that of the chips is arranged, and by transferring the pattern of this mask onto the chips, marks are created at different positions of the chips divided into the same shape on the wafer. It is something.

(Function) When exposure is performed using a mask with patterns arranged at a pitch different from that of the chip pattern to be formed on the semiconductor substrate, and the mask pattern is transferred onto the substrate, the On the chips next to each other,
As you can see, if you consider that the mask pattern is transferred to a location that is shifted by the difference in pitch between the chip pattern and the mask pattern, all chips on a semiconductor substrate have different patterns depending on the position of each chip on the substrate. In other words, a mask pattern, or in other words, a mark indicating the position, can be formed in different parts.

Therefore, the electrical characteristics of each chip can be investigated efficiently and at low cost.

〔Example〕

The present invention will be explained in detail with reference to FIGS. 1 to 12.

Figures 1 to 3 show the positions of the chips on the substrate.
An example of display using a coordinate scale pattern and dots is shown below.

As shown in FIG. 2, the first mask 1 has five coordinate scale patterns 2 for reading the position of each chip on the substrate.
They are arranged at a pitch of 0.000 -, which is the same as the pitch of the chip pattern into which functional elements and the like are to be built.

The distance for one scale of this coordinate pattern is 10 ro. After coating the semiconductor substrate with a photoresist layer, this first mask 1 is brought into contact with the semiconductor substrate, and after exposure to deep ultraviolet rays, a development process is performed.
Furthermore, using this photoresist layer as a mask, each semiconductor chip is etched to transfer this coordinate scale pattern 2. Next, a second mask 3 shown in FIG. 3 is prepared in order to form dots on the coordinate scale pattern to indicate the positions of the chips on the wafer. The pitch of the dots arranged on this mask 3 is 5010 mm, which is longer than the pitch of the coordinate scale pattern 2 by 10 JuIt, which corresponds to the length of one division of the coordinate scale pattern. Then, similar to the first mask 1, a PEP process and an etching process are performed to form a mask pattern (dot 4).
Transfer onto the chip. This state is shown in FIG. Marks (dots 5) are placed on each chip 8 at different positions.
) are formed, and their positions on the semiconductor substrate 6 are indicated. In addition, in order to manufacture the mask 3 used here, one reticle is sufficient, so compared to the conventional example where reticles corresponding to each chip must be manufactured for the number of chips. Mask manufacturing costs can be significantly reduced.

In addition, the second embodiment increases the area occupied by the functional elements by reducing the area occupied by the coordinate scale pattern on the chip.
This will be explained with reference to FIGS. 9 to 9.

First, after forming an oxide film (S!Oz) on the surface of the semiconductor substrate, negative photoresists 1 to 7 (hereinafter referred to as photoresists) are formed.
S;) is applied, and then the coordinate scale pattern 9 is transferred onto the semiconductor substrate by a PEP process using a mask 10 provided with the coordinate scale pattern 9 shown in FIG. The shaded areas in FIG. 4 do not transmit light, and the areas without hatching transmit light (the same applies hereafter), so after this PEP process, the coordinate scale pattern 9 is transferred as an opening onto the semiconductor substrate. be done.

A cross-sectional view is shown in FIG. Here, the mask 10 shown in FIG.
The pitch of the pattern was set to 5000 tan, and the length of one division of the coordinate scale pattern was set to 10.

Subsequently, the oxide film 12 is etched using the photo 9921 to layer 13 as a mask, resulting in a cross section 11 shown in FIG. Further, after removing this photoresist layer 13, a new photoresist is applied.

Subsequently, as shown in FIG. 7, a mask 17 having patterns 16 arranged at a pitch of 5010-, which is 10 times larger than the length of one division of the coordinate scale pattern 9, is prepared, exposed and developed, and the mask 17 is exposed and developed. 17 patterns 16 are transferred onto the substrate.

This u5 becomes the state shown in FIG. 8, and the opening 1 of the oxide film
The semiconductor substrate 21 is exposed only in a portion 20 where 8 and the opening 19 of the photoresist layer overlap.
When the semiconductor substrate 21 is etched using the upper resist layer as a mask and the resist is removed, the state shown in FIG. 9 is obtained, and the position on the semiconductor substrate 23 is displayed on each chip 22 in the cutting direction and the cutting direction. A mark 24 is formed.

In this way, according to this example, the area occupied by the coordinate scale pattern 25 can be reduced.

Furthermore, with reference to FIGS. 10 to 14, another embodiment in which the area occupied by the coordinate scale pattern is reduced will be described.

First, an oxide film (Sigh) is formed on the semiconductor substrate,
Apply Regis I~. After performing exposure and development using a mask 27 equipped with a coordinate scale pattern 26 with a pattern pitch of 5000 JiIn as shown in FIG. 10, the oxide film is etched with ammonium fluoride using the resist as a mask. After exposing the substrate surface, the resist is removed. A cross-sectional view is shown in FIG.

Here, the length of one division of the coordinate scale pattern 26 on the mask 27 is 10JIft in both the vertical and horizontal directions.

Next, as shown in FIG. 12, a mask 31 is prepared which includes patterns 30 arranged at a pitch of 5010 Mt, which is larger by the pitch 10p of one division of the coordinate scale pattern 26. The pattern 30 formed on this mask 31 is
As shown in FIG. 12, it is a combination of figures whose negative sides are 10 squares.

When this mask 31 is brought into contact with a semiconductor substrate coated with a resist and exposed and developed, the state shown in FIG. The semiconductor substrate 35 is exposed on the surface (illustrated). When the semiconductor substrate 35 is etched using the resist as a mask and the resist is removed, a state as shown in FIG. 14 is obtained. Here, mark 3 formed on semiconductor substrate 35
6 represents the position of the chip 38 on the substrate. That is, the position of the mark 36 in the coordinate scale pattern 37 represents the work coordinate, and the length of the mark 36 represents the 7 coordinates.

Although the three embodiments have been described above, the shape of the position display mark and the coordinate scale pattern may be any shape, and the method of forming the position display mark and the coordinate scale pattern on the substrate is to etch the substrate. Do not use any method such as etching the insulating film or depositing a metal film.

(Effects of the Invention) As described above, by incorporating the method of the present invention when building functional elements or circuits into semiconductor chips, it is possible to know where each semiconductor chip was located on the original semiconductor substrate using a low mask cost. As a result, the electrical characteristics of each chip can be investigated efficiently and at low cost.

[Brief explanation of drawings]

1 is a top view of a semiconductor substrate, FIGS. 2 to 4 are top views of a mask used in the present invention, FIGS. 5 and 6 are cross-sectional views of a semiconductor chip showing the manufacturing process of the method of the present invention, and FIG. The figure is a top view of a mask used in the present invention, Figures 8 and 9 are top views of a semiconductor substrate, Figure 10 is a top view of a mask used in the present invention, and Figure 11 is a semiconductor manufacturing process showing the method of the present invention. 12 is a top view of a mask used in the present invention, and FIGS. 13 and 14 are top views of a semiconductor substrate.

Claims (1)

[Claims] Forming a mark on a semiconductor chip, characterized in that when exposing a photoresist covering semiconductor chips that are dividedly provided in the same shape on a semiconductor substrate, mask patterns having mutually different pitches are transferred onto the semiconductor chips. how to.