JPS59161033A - Photo mask - Google Patents

Abstract

PURPOSE:To reduce remarkably the occupying area of positioning patterns without reducing precision of positioning between a photo mask and a wafer by a method wherein first and second positioning patterns are provided to the photo mask and the wafer, and the positions to be provided with the first positioning patterns are specified. CONSTITUTION:Positioning patterns 3, 3' of the plural number of pieces for rough alignment are arranged in the arbitrary positions 4, 4' in a photo mask 1, and positioning patterns 5 for precise alignment are built in respective chips 2. The positioning patterns 3, 3' on the photo mask 1 and the positioning patterns of the same kind on a wafer 10 are made to coincide with each other through objectives 12, 12' according to an automatically photo mask positioning device. Then the objectives 12, 12' are transferred in the directions X, X' or Y, Y', and the positioning patterns 5 built in the arbitrary chips and the positioning patterns of the same kind on the wafer 10 are made to coincide.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a 7-photomask for photolithography used in the manufacturing process of semiconductor devices. This relates to an improved photomask.

[Background of the invention]

When alignment is performed using a conventional automatic photomask alignment device, the alignment pattern on the photomask must be aligned with the alignment pattern on the wafer by mechanical operation, and the accuracy of the coarse alignment function or Due to the non-uniformity of the wafer shape, it is necessary to use a 500X alignment pattern between photomasks.
A size of 500 μm2 or more is required.

Also, using the alignment pattern, a photomask
As a method for aligning the sea urchin, one method is to incorporate the alignment pattern 3 into each chip 2 of the photomask 1, as shown in FIG. Second, as shown in FIG. There is a method for aligning the otomask and wafer.

From the point of view of alignment accuracy, the above-mentioned second method is effective when producing a photomask.In the current mask manufacturing equipment, the reticle used for chip 2 (having a pattern 10 times larger than that printed on the wafer) and the reticle at an arbitrary location This method is inferior to the first method described above in that the reticle used for the alignment pattern arranged in No. 4 must be replaced at the time of repeating, and positional deviation on the apparatus is added at that time. On the other hand, the first method described above has the disadvantage that the effective area occupied by the integrated circuit is small because the alignment pattern with a size of 500 x 500 μm2 or more is built into each chip, and the number of chips obtained is small. has.

[Object of the Invention] An object of the present invention is to provide a 7-otomask for photolithography that can significantly reduce the area occupied by alignment patterns without deteriorating the alignment accuracy between multiple photomasks and wafers. .

[Summary of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a photo-etching photomask capable of accurately aligning a photomask and a wafer and significantly reducing the area occupied by the alignment pattern.

The present invention has a first alignment pattern, a second alignment pattern, and a first alignment pattern.
Good alignment is achieved by specifying the position of the alignment pattern.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 shows a photomask for explaining the alignment method between a photomask and a wafer using the present invention.

As shown in the figure, any location 4 within the photomask 1,
4', for example, 500x5 for rough alignment.
Alignment pattern 3 with a size of about 00 μm2 or more,
Furthermore, each chip 2 has a built-in alignment pattern 5 of, for example, about 50×50 μm 2 for high-precision alignment. In order to perform alignment between the photomask and the wafer using this photomask, first, the alignment patterns 3.
3' and the same type of alignment pattern on the wafer. Then, by mechanical operation of an automatic photomask alignment device, an arbitrary chip, e.g.
Align the alignment butter 15 built into the chip a' with the same type of alignment pattern on the wafer.

According to the above-described alignment method between a photomask and a wafer, alignment accuracy decreases due to positional deviation due to alignment using alignment patterns 3 and 3', which was a drawback of the conventional technology. is corrected by the subsequent positioning using a fine alignment alignment pattern built into the chip, and the area occupied by the alignment pattern built into the chip is 50XjOμm2.
The disadvantage of the prior art, which is that the number of chips obtained per wafer is small, is overcome.

FIG. 4 schematically shows an apparatus for specifically implementing the photomask-wafer alignment method described in FIG. 3. 10 is wafer, 11 is 3,3
Apparatus for recognizing alignment patterns consisting of ' and 5, 1
2.12' is a device that directly recognizes the above-mentioned alignment pattern, and indicates, for example, an objective lens with a magnification of about 10 times. The method of performing alignment using the photomask-wafer alignment apparatus shown in FIG. 4 is as follows: First, the alignment pattern 3. 3',! : wafer 10
Align the alignment pattern of the above four lines through the objective lens 12 and 12'. Next, the objective lens 12 is used for mechanical operation of the automatic photomask positioning device.
, 12' as x, x' or Y in Figure 4,
Move in the direction of Y' and select an arbitrary chip, for example a,
The alignment pattern 5 built into the chip a' or b, b' is aligned with the alignment pattern of the same type on the wafer 10.

In the alignment device shown in FIG. 4, an objective lens with a magnification of about 10 times is used as an example of a device that directly recognizes the alignment pattern. The size of is 50X
Since the size is as small as about 50 μm2, recognition may become difficult. In this case, a device as shown in FIG. 5 is used as a device for recognizing the alignment pattern. In the figure, 12.12' is an objective lens with a magnification of about 10 times, which is used to align the large alignment pattern 3 of about 500×500 μm 2 in FIG. 4.

13.13' is an objective lens with a magnification of, for example, 50 times or more, and is used to align the small alignment pattern 5 of about 50×50 μm 2 in FIG. 4.

The distances A and B of 12.12' and 13.13' are
It is determined according to the arrangement of alignment patterns used for alignment. The method for performing alignment using the photomask-to-wafer alignment device shown in Figure 5 is to first perform alignment at 12.12' and then mechanically operate the automatic photomask alignment device. , rotate the alignment pattern recognition device 11 in the Z direction, and perform alignment at J3.131.

The gist of the present invention is to perform alignment using a plurality of alignment patterns arranged within a photomask, and then,
The scope of application of the present invention is not limited to the above-mentioned embodiments, but the scope of application of the present invention is not limited to the above-mentioned embodiments. It goes without saying that various applications can be made without departing from the spirit of the invention. For example, the positioning pattern can be freely placed within the photomask or within the chip as long as alignment is possible. Furthermore, it goes without saying that the apparatus that can be used to implement the above-mentioned alignment method is not limited to the above-mentioned embodiments, and can be applied in various ways without departing from the spirit of the present invention.

[Effects of the Invention] According to the present invention described above, pattern alignment between a photomask and a wafer can be performed with high precision without deteriorating alignment accuracy, and the alignment pattern can also be made smaller. Therefore, the number of chips obtained per wafer is increased, which is an advantage not found in the conventional technology.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a conventional example, and FIGS. 3, 4, and 5 are diagrams showing an embodiment of the present invention. Explanation of symbols 1...Photomask, 2...Semiconductor chip corresponding part,
3... Alignment pattern, 4... Chip part provided with alignment pattern, 5... Alignment pattern for high precision alignment, ]0... Wafer, ]1... Recognition device base, ] 2.
12://13, ]31... Recognition device. Manko S2 Audience 3 Drifting on the River 4

Claims (1)

[Scope of Claims] 1. A photomask comprising a semiconductor element forming pattern and a first alignment pattern, wherein the semiconductor element forming pattern has a second alignment pattern, and the semiconductor element forming pattern has a second alignment pattern; A photomask characterized in that the first alignment pattern is provided such that at least a portion thereof is included in a square inscribed in a circle inscribed in the outer edge of the photomask. 2. A photomask comprising a semiconductor element forming pattern and a first alignment pattern, wherein the semiconductor element forming pattern has a second alignment pattern, and the first alignment pattern has a second alignment pattern; A photomask characterized in that the pattern is provided so that at least a part of the pattern is included in a square inscribed in a semiconductor wafer exposed by the photomask.