JPS61234036A - Positioning method and device - Google Patents

Abstract

PURPOSE:To preferably position by providing the first and second positioning patterns, and specifying the position for providing the first positioning pattern. CONSTITUTION:A plurality of positioning patterns 3, 3' of the size such as, approx. 500X500mum<2> for rough alignment are disposed at arbitrary positions 4, 4' in a photomask 1, and a positioning pattern 5 of the size such as, approx. 50X50mum<2> for accurate alignment is contained in each chip 2. In order to position between photomask wafers by the photomask, the patterns 3, 3' on the photomask and the positioning pattern of the same type on the wafer are matched by the mechanical operation of an automatic photomask positioning device. Then, an arbitrary chip such as, positioning pattern 5 contained in chips a, a' and a positioning pattern of the same type on the wafer are matched by the mechanical operation of the automatic photomask positioning device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for aligning photomask wafers for photolithography used in the manufacturing process of semiconductor devices, and an improvement in an alignment device. be.

[Conventional technology]

When alignment is performed using a conventional automatic photomask alignment device, the alignment pattern on the photomask must be aligned with the alignment pattern on the wafer by mechanical operation, and the accuracy of the coarse alignment function or Due to the non-uniformity of the wafer shape, the alignment pattern between photomasks is inevitably
xso.

A size larger than sm is required.

Also, using the alignment pattern, a photomask
One way to align wafer applications is to
As shown in FIG. 1, the alignment pattern 3 is built into each chip 2 of the photomask l, and a plurality of alignment patterns are used to align the photomask and the wafer. As shown in FIG. 2, there is a method of aligning the photomask and the wafer by placing a plurality of alignment patterns 3 at a given chip location 4 within the photomask l.

From the point of view of alignment accuracy, the above-mentioned second method is difficult to use when manufacturing photomasks, and in current mask manufacturing equipment, the reticle used for chip 2 (having a pattern 10 times larger than that printed on the wafer) and the arbitrary This method is inferior to the first method described above in that the reticle used for the alignment pattern placed at location 4 must be replaced at the time of repeating, and positional deviation on the apparatus is added at that time. On the other hand, the above g
Method x has the disadvantage that since each chip incorporates an alignment pattern with a size of s 500 x 500 am or more, the effective area occupied by the integrated circuit becomes small and the number of chips obtained per wafer is reduced.

[Problem that the invention seeks to solve]

An object of the present invention is to provide a photomask for photolithography in which the area occupied by alignment patterns can be significantly reduced without deteriorating the accuracy of alignment between a plurality of photomasks and wafers.

[Means and effects for solving the problems] One aspect of the present invention is to provide a photolithography method for photolithography that achieves accurate alignment between a photomask and a wafer using the above-mentioned prior art and significantly reduces the area occupied by the alignment pattern. Provide masks.

The present invention has an eleventh second alignment pattern, and the first
Good alignment is achieved by specifying the position where the alignment pattern is provided.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 shows a photomask for explaining the alignment method between a photomask and a wafer using the present invention.

As shown in the figure, any location 4,
4', for example, 500x5 for rough alignment.
Alignment pattern 3 with a size of about 00mm” or more,
Further, each chip 2 has a built-in positioning pattern 5 having a size of, for example, 50×59 sm for high-precision alignment. To perform alignment between the photomask and the wafer using this photomask, first, the alignment patterns 3 and 3 on the photomask are mechanically operated by an automatic photomask alignment device.
3' and the same type of alignment pattern on the wafer. Then, by mechanical operation of an automatic photomask alignment device, an arbitrary chip, e.g.
The alignment pattern 5 built into the chip a' is aligned with the alignment pattern of the same type on the wafer.

The above-described alignment method between a photomask and a wafer has drawbacks in the prior art.

The decrease in alignment accuracy due to positional deviation caused by alignment using alignment pattern 3.3' is as follows:
The alignment is then corrected by the alignment pattern 5 for fine alignment built into the chip, and since the area occupied by the alignment pattern built into the chip is as small as about 50 x 50 jm, the number of chips per wafer is The drawback of the prior art that the number of acquisitions is small is eliminated.

FIG. 4 schematically shows an apparatus for concretely realizing the alignment method between the photomask and the wafer explained in FIG.
Apparatus for recognizing alignment patterns consisting of ' and 5, 1
2.12' is a device that directly recognizes the above-mentioned alignment pattern, and indicates, for example, an objective lens with a magnification of about 10 times. The method of alignment using the photomask-to-wafer alignment device shown in FIG. and the same type of alignment pattern on the wafer IO are aligned through an objective lens 12 and 12'. Then, the objective lens 12.12' is aligned by mechanical operation of an automatic photomask positioning device.
is moved in the x, x' or Y, Y' directions in FIG.
Align like alignment patterns on wafer lO.

In the alignment device shown in FIG. 4, an objective lens of about 10 times is used as a device to directly recognize the alignment pattern. The size of is 50
Since the size is as small as 50 am", recognition may be difficult. In this case, a device such as the one shown in Fig. 5 may be used to recognize the alignment pattern.
In the same figure, 12.12' is an objective lens of about 10 times, which is used to align the large alignment pattern 3 of about 500×500 sm'' in FIG.

13.13' is an objective lens with a magnification of, for example, 50 times or more, and is used to align the small alignment pattern 5 of about 50 x 5 Qsm'' in FIG. 4 (12.12'
The distances 13 and 13' to the right and B are determined according to the arrangement of the alignment patterns used for alignment. The method for performing alignment using the photomask-wafer alignment apparatus shown in FIG.
After alignment is performed in step 2', the alignment pattern recognition device 11 is rotated in two directions by mechanical operation of the automatic photomask alignment device, and the device 11 is rotated in two directions.
' to align.

The gist of the present invention is to perform alignment using a plurality of alignment patterns arranged within a photomask, and then,
The present invention is not limited to the above-mentioned embodiments, and the scope of application of the present invention is not limited to the above-described embodiments. It goes without saying that various applications can be made without departing from the concept. For example, the positioning pattern can be freely placed within the photomask or within the chip as long as alignment is possible. Furthermore, it goes without saying that the device for realizing the above-described alignment method is not limited to the above-described embodiments, and can be applied in various ways without departing from the spirit of the present invention.

〔Effect of the invention〕

According to the present invention described above, pattern alignment between a photomask and a wafer can be performed with high accuracy without deteriorating the alignment accuracy, and since the alignment pattern is also small, the number of chips per wafer can be reduced. It has an advantage that the conventional technology does not have, that is, the number of acquisitions increases.

[Brief explanation of drawings]

1 and 2 are diagrams showing a conventional example, and FIGS. 3, 4, and 5 are diagrams showing an embodiment of the present invention. l...Photomask, 2...Semiconductor chip compatible part,
3... Alignment pattern, 4... Chip part provided with alignment pattern, 5... Alignment pattern for high precision alignment, 10... Wafer, 11... Recognition 7th section chrysanthemum 2 diagram

Claims (1)

[Claims] 1. In alignment between a photomask and a wafer used in the semiconductor device manufacturing process, at least two first alignment patterns provided within the chip pattern area of the photomask and a a first step of aligning at least two first alignment patterns provided in a chip area using at least two pattern recognition devices, and each chip pattern provided in a photomask; aligning a second alignment pattern built into the wafer and a second alignment pattern provided in each chip on the wafer in at least two different chips using at least two pattern recognition devices; A positioning method characterized by comprising a second step. 2. A patent claim characterized in that the alignment of the first alignment pattern and the alignment of the second alignment pattern are performed successively by moving at least two pattern recognition devices. The alignment method described in item 1. 3. In an alignment device that aligns a photomask and a wafer used in the semiconductor device manufacturing process, alignment of at least two first alignment patterns provided within a chip area and alignment of at least two first alignment patterns provided within each chip are performed. at least two pattern recognition devices that perform alignment of at least two second alignment patterns, and the first and second alignment patterns are successively performed by movement of the pattern recognition device. A positioning device characterized by: 4. The pattern recognition devices include at least two first recognition devices that align the first alignment pattern, and at least two second recognition devices that align the second alignment pattern. 4. The alignment device according to claim 3, wherein the second recognition device has a magnification higher than the first recognition device.