JPH02246313A - Target pattern and window pattern for mask alignment of aligner - Google Patents

Abstract

PURPOSE:To enable fine work patterning with high precision by a method wherein alignment targets on a substrate are subjected to dark field illumination from windows arranged on an exposure mask, and reflected and scattered light from the target edges is detected, thereby performing the alignment of the substrate and the exposure mask. CONSTITUTION:On a substrate, square targets 11a for alignment are arranged at specific intervals, in the longitudinal and the transversal directions; at the positions of edges constituting four sides, windows 13xx and windows 13yy are arranged. The targets 11a on the substrate are subjected to dark field illumination from the window 13xx and 13yy arranged on an exposure mask, and the light reflected and scattered from the edges of the target 11a is detected, thereby performing the alignment of the substrate and the exposure mask, while edges Y1-Y6 are used in the case of longitudinal direction alignment, and edges X1-A12 are used in the case of transversal direction alignment. The edges Y1-Y6 and the edges X1-X12 therefore form a lattice pattern; the edges both in the longitudinal direction and in the transversal direction are obtained in the same plane; the length of edge becomes long, and the scattered light is increased; as a result, alignment sensitivity increases. Thereby fine work patterning with high precision is enabled.

Description

[Detailed Description of the Invention] [Summary] To realize a pattern with high alignment sensitivity regarding a pattern for mask alignment in photolithography for forming a predetermined resist pattern on a substrate in the process of manufacturing wafers such as integrated circuits. With the aim of realizing an exposure system that can perform fine patterning with high accuracy, the target for alignment on the substrate is illuminated with dark field through a window provided in the exposure mask. When aligning the substrate and the exposure mask by detecting light reflected and scattered from the edges of the substrate, square targets are placed at predetermined intervals in the vertical and horizontal directions on the substrate as alignment targets. A window for dark-field illumination is provided at each of the edges of the four sides of the target.

[Industrial application field]

The present invention relates to a pattern for mask alignment in photolithography for forming a predetermined resist pattern on a substrate in a wafer manufacturing process for integrated circuits and the like.

[Photolithography and Mask Alignment] (1) Photolithography When forming an integrated circuit on a semiconductor substrate (wafer), processes such as oxide film formation, etching, impurity diffusion, or electrode film formation are carried out at specified locations on the wafer. It is necessary to do it in the position part.

These wafer treatments are performed by exposing only a predetermined portion of the wafer and masking the other portions.

Further, the process of forming the mask on the wafer is called patterning, and the patterning and wafer processing are repeated to fabricate the required integrated circuit board.

There are various methods for patterning, and photolithography is a technique that involves exposing a photoresist (photosensitive resin) to light.

Photolithography proceeds in the following steps.

■Coat photoresist on the wafer.

■Expose the photoresist using a patterning mask.
.

■Develop the exposed photoresist.

In the developed photoresist, only the portion exposed to light becomes a polymer and remains. Therefore, regarding other parts,
It becomes possible to perform wafer processing such as etching work.

(2) Mask Alignment When forming an integrated circuit on a wafer, patterning and wafer processing are repeated to sequentially form necessary semiconductor layers, insulating layers, electrode layers, etc.

Therefore, it is necessary to match the relative positions of the exposure patterning masks between each patterning process. This is mask alignment.

On the other hand, with the rapid miniaturization of integrated circuits, this mask alignment has become particularly important.

[Conventional technology]

(1) Stepper exposure and alignment equipment Currently, stepper exposure equipment is widely used as an exposure equipment for patterning.

In stepper exposure, a reticle pattern (reticle pattern), which is several times larger than the original size pattern, is reduced and projected onto a wafer.

Mask alignment in this case is performed using a target pattern for alignment on the wafer.
rn) and the window pattern (Wi
This is done by matching the positions of the ndow Pattern).

FIG. 3 is a diagram illustrating the optical system of the alignment device.

This alignment device uses illumination light 7 from the illumination system to align the alignment window of the reticle 6.
t Window) 6a is irradiated onto the wafer 1 through the lens system 4 (dark field irradiation). At this time, the scattered light 8 generated at the edge of the alignment target pattern on the wafer 1 is PMT (
Mask alignment is performed by detecting with Photomultiplier Tube) 9.

In other words, wafer 1! ! w, slightly move the X stage 2 and Y stage 3 in the X-axis direction and the Y-axis direction,
The point where the scattered light 8 is the strongest is determined.

Further, the alignment target pattern provided on the wafer is provided at a dividing scribe line between chips.

FIG. 4 is a plan view illustrating the projection position of the target pattern. In the figure, the gap between the chips 15 of the wafer 1 is a scribe line 16.

(2) Principle of Alignment FIG. 5 is a diagram explaining the principle of the alignment method.

(a) is a cross-sectional view showing the relative positional relationship between the target pattern 11 provided on the wafer 1 and the reticle 6, and (b)
) is a graph illustrating the relationship between the PMT output voltage Vp and the wafer position ΔD.

That is, this is the change in the PMT output voltage when the reticle 6 is fixed and the wafer 1 is moved in the direction of arrow M.

In the figure, reticle window patterns 13a, 1
The light irradiated onto the wafer 1 from the wafer 3b is scattered at the edge portion of the target pattern 11 of the wafer 1.

Therefore, the reticle window pattern 13a, 1
When the center position 14 of the wafer 3b coincides with the edge position 12 of the target pattern 11 of the wafer, the amount of scattered light is the greatest, and the output voltage of the PMT is maximum, and gradually decreases at positions before and after the center position 14 of the wafer.

That is, the position where the PMT output voltage is maximum is the position of the target pattern 11 of the wafer and the reticle 6 - the point of failure.

Therefore, in the X-axis direction and Y-axis direction in FIG.
By determining the maximum point of the MT output voltage, the positions of each mask pattern can be matched in the patterning process.

(3) Reticle window pattern and wafer target pattern Figure 6 is a plan view illustrating the reticle window pattern and wafer target pattern. This part is masked and does not allow light to pass through. Further, (b) shows the target pattern of the wafer, and the cross-hatched portion in the figure is the target pattern.

Conventional wafer target patterns include strip-shaped target patterns 11x and 1 in the vertical and horizontal directions, respectively.
1y is provided, and the target pattern 11x performs horizontal positioning in the figure, and the target pattern 11y performs vertical positioning in the figure.

Further, its size is approximately 110 μ-1 in the vertical direction and 130 μ-1 in the horizontal direction.

On the other hand, the window patterns 13x and 13y of the reticle are provided to match the side edges of the band-shaped target pattern, and there are windows at two locations on both sides of each target. In addition, the reticle window pattern 13x,
13y is provided in the alignment window 6a shown in FIG.

Then, these window patterns and target patterns are created in pairs and serve as a reference for alignment.

[Problem to be solved by the invention]

As integrated circuits become more highly integrated, their microfabrication is rapidly progressing, and the width of processed evaporation is rapidly becoming narrower.

Therefore, high precision is also required for mask alignment during patterning.

In order to achieve high precision alignment in conventional target patterns and window patterns, the length of the band-shaped target pattern is increased to increase the amount of scattered light generated at the edges of the target pattern, thereby increasing the PMT output voltage. It is necessary to increase the sensitivity of the alignment.

However, the wafer target provided in the scribe line naturally has a size limit, which is a factor that limits the ability to achieve high sensitivity. Similar limitations also apply to reticles for patterning wafers.

The technical problem of the present invention is to solve the above-mentioned problems in the target pattern and window pattern for mask alignment, to obtain a large amount of scattered light even in the same area, and to achieve high precision by realizing a pattern with high alignment sensitivity. The object of the present invention is to realize an exposure apparatus that can perform fine patterning.

[Means to solve the problem]

FIG. 1 is a plan view illustrating the basic principle of the present invention.
) indicates the window pattern of the reticle, and the cross-hatched areas in the figure indicate mask areas through which no light passes. Moreover, (b) shows the target pattern of the wafer, and the cross-hunting part in the figure is the target pattern.

The pattern of the present invention is characterized by the use of a square pattern that allows all edges of the pattern to be effectively utilized.

That is, the alignment target 11a on the substrate is
Window 13XX, t3yy provided on the exposure mask
When aligning the substrate and the exposure mask by performing dark field illumination from the edge of the target 11a and detecting light reflected and scattered from the edge of the target 11a, a square target 11a is used as the alignment target. are arranged at predetermined intervals in the vertical and horizontal directions on the substrate.

On the other hand, as windows for dark-field illumination, windows 13xx+13FF are provided at respective positions of edges constituting four sides of the target 11a.

[Effect]

The target pattern of the present invention is a square.

On the other hand, the reticle window pattern is provided at each of the four edges of the target pattern.

Therefore, all four sides of the square can be used as edges to obtain scattered light.

That is, edges Y1 to Y6 are used for alignment in the vertical direction on the drawing, and edges XI-X12 are used for alignment in the horizontal direction on the drawing.

As a result, edges Y1 to Y6 and edges XI to X12 form a lattice pattern, and edges in both the vertical and horizontal directions can be obtained within one plane. Therefore, the edge length becomes longer (and the amount of scattered light increases), resulting in higher alignment sensitivity.

Incidentally, in the case of the pattern shown in FIG. 1, an edge length approximately 1.8 times that of the conventional pattern can be obtained.

(Example) Fig. 2 is a plan view illustrating an example, in which (a) shows the window pattern of the reticle, and the cross-hatched part in the figure shows the mask part through which no light passes. .Furthermore, (b) shows the target pattern of the wafer, and the cross-hatched portion in the figure is the target pattern.

Furthermore, an example is given in which aluminum is vapor-deposited to a thickness of lpm+ on the wafer surface, and then patterning is performed.

The target pattern of this example has a -side length of 4μ-
15 square target patterns 11b are arranged horizontally and 4 vertically, and the spacing between them is 6 μ- both horizontally and vertically.

Therefore, the horizontal length of the entire pattern is 144μ, and the vertical length is 34u*.

On the other hand, the window pattern has -side length of 4μ-
A window pattern 13c having a width of 2 μm is provided around the square mask portion, and the surrounding area is also masked.

The above window pattern is arranged in 15 pieces horizontally and 4 pieces vertically, with an interval of 2p both horizontally and vertically.
It's haze.

In the case of this embodiment, the length of one side of the target pattern 11b is 4#-1, while the inner diameter of the window pattern 13c is 4 .mu.m and the outer diameter is 8 .mu.m.

Therefore, the edge of the target pattern 11b does not align with the center position of the window pattern 13c.

This is because aluminum is vapor-deposited to a thickness of 1 μm on the wafer surface and then patterned.

That is, if 1 μm of aluminum is vapor-deposited, each side of the wafer target 11b becomes thicker by 1 μm.

Therefore, during patterning work after aluminum vapor deposition, the length of one side of the target pattern 11b is 6〃■
Therefore, the edge position of the target pattern 11b is lost at the center of the window pattern 13c.

Incidentally, the edge length of this example is approximately 1
．． It will be about twice as much.

〔Effect of the invention〕

As described above, according to the present invention, by arranging square targets at predetermined intervals in the vertical and horizontal directions, all edges of the targets can be effectively utilized.

Therefore, it is possible to obtain a long edge length for alignment within a certain area, and the alignment sensitivity can be increased.

As a result, it is possible to realize an exposure apparatus that can perform fine patterning with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a plan view illustrating the basic principle of the present invention.
) is the window pattern of the reticle, (b) is the target pattern of the wafer, FIG. 4 is a plan view illustrating the projection position of the wafer target; FIG. 5 is a diagram illustrating the principle of the alignment method; FIG. 6 is a diagram illustrating the reticle FIG. 3 is a plan view illustrating the window pattern and the target pattern of the wafer, in which (a) is the window pattern of the reticle, and (b) is the target pattern of the wafer. In the figure, 1 is a wafer, 2 is an X stage, 3 is a Y stage, 4 is a lens system, 5 is a fixed mirror 6 is a reticle,
6a is an alignment window, 7 is an irradiation light, 8 is a scattered light, 9 is a PMT, 10 is a reflector, IL11b-11x,
11y is the target pattern, 11a is the target,
12 is the edge position of the target, 13a, 13b, 13
c, 13x, 13y are window patterns, 13xx,
13yy indicates a window, 14 indicates the center position of the window pattern, 15 indicates a chip, and 16 indicates a scribe line. Patent Applicant Fujitsu Limited Kyushu Fujitsu Electronics Sub-Agent Patent Attorney Yasushi Fukushima Text No. 1 Completion Table 15 Riki Yuu Publishing - ' %3 Figure Goulis Soto J Magoon ■ Design Illusion Input System 4 Figure 7 Rayman's Shield Sato Figure 5 (b)

Claims (1)

[Claims] In an exposure apparatus that forms a predetermined resist pattern on a substrate by photolithography, an alignment target (11a) on the substrate is positioned through windows (13xx) and (13yy) provided in an exposure mask. When aligning the substrate and the exposure mask by performing dark field illumination and detecting light reflected and scattered from the edge of the target (11a), a square target (11a) is used as an alignment target. are arranged at predetermined intervals in the vertical and horizontal directions on the substrate, and the target (1
A target pattern and a window pattern for mask alignment of an exposure apparatus, characterized in that windows (13xx) and (13yy) are provided at respective positions of the edges constituting the four sides of 1a).