JPH0318012A - Reticle for reducing-projection exposure apparatus - Google Patents

Abstract

PURPOSE:To improve throughput and accuracy in pattern exposure on a wafer in semiconductor manufacturing and to reduce a cost by arranging an alignment mark or a PCM at parts corresponding to the scribing lines of a main body chip when a reticle is formed. CONSTITUTION:An alignment mark 21 and a PCM 31 are arranged on scribing lines which are regions that are not especially used. Thus, a reticle can be designed without enlarging the area of a main body chip 4 and without providing a region for the PCM 31 on the reticle. Since the area of the main body chip 4 is not changed, the number of picked-up pieces is not decreased. The number of the chips which can be arranged on the reticle is increased. The efficiency per one shot 5 of a reducing-projection type exposure apparatus is improved. The main body chip 4 can be exposed at a part wherein the PCM 31 is exposed in the conventional apparatus on the wafer. Therefore, the number of the picked-up pieces per wafer is increased. In this way, the position aligning accuracy is improved, the throughput of the reducing-projection type exposure apparatus is improved and the reduction in cost can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reticle that is an exposure original plate for a reduction projection exposure apparatus that exposes a semiconductor integrated circuit pattern onto a wafer during semiconductor manufacturing.

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has increased dramatically, and it has become mainstream to form a pattern on a wafer using a reduction projection exposure apparatus.

The reticle, which is the exposure original plate, usually requires the arrangement of an integrated circuit for the main body, a process control module (PCM), and alignment marks for mask alignment.

Conventionally, as shown in FIG. 3, areas where the main chip 6 and the PCM 8 are placed are provided separately, and the alignment marks 7
It is arranged in the arrangement area of the PCM or inside the main body chip.

Problems to be Solved by the Invention In the conventional alignment mark arrangement, when an alignment mark is placed in the PCM placement area, the location on the wafer where the alignment mark is placed is the PCM as shown in FIG. Since only the portions exposed are exposed, and there are few locations where alignment marks are present, soft alignment accuracy deteriorates and alignment takes time. In addition,
In FIG. 4, 9 is the main chip, 10 is one shot using the reticle of FIG. 3, and 11 is a PCM arrangement area.

When placing alignment marks inside the main chip, it takes up extra space inside the chip, increasing the chip size, which reduces the number of chips that can be taken on the wafer and the number of chips that can be placed on the reticle. Decreased,
This will lead to increased costs and decreased throughput.

In the conventional PCM arrangement, as shown in FIG. 4, it is necessary to specify the location where the PCM is to be exposed in the control file of the reduction projection exposure apparatus.

Furthermore, as shown in FIG. 3, it is necessary to reserve an area on the reticle for forming the PCM, which reduces the number of chips that can be placed on the reticle. Furthermore, the number of chips removed on the wafer is also reduced.

The present invention solves the above-mentioned conventional problems, and improves the alignment accuracy, improves the throughput of the reduction projection exposure system, and reduces costs by devising the placement locations of the alignment mark and PCM on the reticle. The purpose is to

Means for Solving the Problems In a reticle, an alignment mark and a PCM are arranged at positions corresponding to the scribe line of the main chip.

If you put this on the reticle side when designing the reticle,
There is no need to consider this when designing the main body chip. (The scribe line part of the main chip is cut out, and the reticle designed using this method is overlapped and exposed on an electron beam exposure device to manufacture the reticle.) Functional alignment marks and PCM have not been particularly used until now. By arranging it on the scribe line, which is a region, the reticle can be designed without increasing the main chip area and without providing a region for PCM on the reticle. As a result, the number of chips does not decrease because the main chip area remains unchanged.

Furthermore, since there is no need to provide an area for PCM, the number of chips that can be placed on the reticle increases, and the efficiency per shot of the reduction projection exposure apparatus increases.

In addition, the area 1 on the wafer where PCM was previously exposed
1 also allows the main chip to be exposed, increasing the number of wafers per eight wafers.

By placing the alignment mark around the main chip, the alignment mark is uniformly present on every part of the wafer, making it possible to create a control file for the reduction projection exposure apparatus with very few restrictions.

Furthermore, since the nearest alignment mark can be used, there is less movement of the stage, the alignment time can be shortened, and alignment accuracy can be improved.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a reticle diagram in one embodiment of the present invention.

In FIG. 1, six main body chips 1 are arranged in the reticle area. An alignment mark 2 and a PCM 3 are arranged in a portion corresponding to the scribe line of this chip.

When a wafer is exposed using this reticle, it becomes as shown in Fig. 2, and it is possible to expose only the chips to the maximum extent possible, and the PCM 31 and alignment Since the mark 21 is included, the PCM and alignment marks are uniformly present on the wafer.

Next, a comparison will be made between the reticle of the present invention shown in FIG. 1 and the conventional reticle shown in FIG.

In FIG. 3, only four chips 6 can be placed on the reticle in order to take up the area for placing the alignment mark 7 and PCM 8.

When a wafer is exposed using this reticle, as shown in FIG. 4, the number of chips that can be exposed per shot of 10 is 4, which is 2/3 compared to the embodiment of the present invention, and the reduced projection It can be seen that the throughput of the exposure equipment decreases.

Furthermore, as shown in FIG. 4, the PCM is exposed at five points on the wafer, but for this reason, compared to the embodiment of the present invention,
Control files for reduction projection exposure devices become complex. Furthermore, since there are alignment marks only at these five points, restrictions increase and the alignment time and precision are inferior.

Furthermore, since the PCM arrangement area exists, the number of chips arranged per wafer is reduced compared to the embodiment of the invention.

Effects of the Invention As described above, the present invention improves the throughput and precision of pattern exposure on wafers during semiconductor manufacturing by arranging alignment marks or PCMs in portions corresponding to the scribe lines of the main chip when forming a reticle. This results in improved performance and reduced semiconductor manufacturing costs.

[Brief explanation of the drawing]

FIG. 1 is a reticle diagram for a reduction projection exposure apparatus of the present invention, and FIG.
The figure shows a pattern exposed on a wafer using the reticle shown in Fig. 1, Fig. 3 shows a reticle for a conventional reduction projection exposure system, and Fig. 4 shows a pattern exposed on a wafer using the reticle shown in Fig. 3. It is an exposed figure.

Claims (2)

[Claims] (1) A reticle for a reduction projection exposure apparatus, characterized in that an alignment mark for mask alignment is arranged in an area corresponding to a scribe line portion of a main chip. (2) A reticle for a reduction projection exposure apparatus, characterized in that a process control module is disposed in an area corresponding to a scribe line portion of a main chip.