JP2015184526A - Photomask and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask that can maximize the number of effective chips per one wafer without increasing the cost for the mask.SOLUTION: A photomask 100 includes a first mask pattern 100 and a second mask pattern 120, in which the first mask pattern 110 and the second mask pattern 120 are disposed to overlap chip segments arranged in 4×4 rows and columns, where chip segments are shifted by one row and one column. In the second mask pattern 120, a parts pattern 150 such as an alignment mark is disposed in a chip segment 130 other than segments in the overlapped area 160 with the first mask pattern 110, and thereby, different mask patterns can be separately subjected to exposure, and the number of effective chips can be maximized.

Description

  The present invention relates to a photomask and a method for manufacturing a semiconductor device.

  In a semiconductor device manufacturing process, in order to form a large number of semiconductor chips on a wafer, a circuit pattern is transferred, developed, and etched on the wafer using photolithography. The circuit pattern is transferred by reducing and projecting the pattern formed on the photomask onto the wafer using a stepper device or the like.

JP 2008-268864 A

  In such a semiconductor device manufacturing process, parts (alignment marks and TEGs for aligning the photomask and the wafer, etc.) necessary for the process steps are arranged, but the arrangement area of such parts is increased. This reduces the effective chip area on the wafer, leading to an increase in manufacturing cost.

  In addition, since parts necessary for the process steps are drawn on a photomask, efficient mask pattern design is required to reduce the cost including the mask.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, it is possible to provide a photomask that can discriminate between different mask patterns at the time of exposure, so that the number of effective chips per piece of wear can be maximized without increasing the mask cost. Can be realized.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following application examples.

[Application Example 1]
The photomask of this application example includes a first mask pattern which is a one-shot mask pattern in which chip sections where chip patterns are arranged are arranged in a matrix of n rows × m columns, and the first mask pattern And a second mask pattern that is a one-shot mask pattern in which part patterns (alignment marks and TEG) used in a process step are arranged in at least one of the chip sections. The mask pattern and the second mask pattern are arranged by shifting the chip sections by a row and b columns so that the chip sections of (na) rows × (m−b) columns overlap. In the second mask pattern, the part pattern is arranged in a chip section in a portion other than the overlapping area with the first mask pattern.

  According to this application example, it is possible to provide a photomask that can be distinguished from the first mask pattern and the second mask pattern at the time of exposure, so it is possible to increase the cost per piece of wear without increasing the mask cost. The number of effective chips can be maximized.

[Application Example 2]
In the above photomask, a = 1 and b = 1 may be used.

According to this application example, it is possible to provide a photomask that can distinguish between the first mask pattern and the second mask pattern during exposure without increasing the area of the photomask [Application Example 3].
In the photomask described above, the first mask pattern may have a chip pattern arranged in all chip sections.

  According to this application example, it is possible to maximize the number of effective chips when the first mask pattern is shot in a photomask that can be divided into the first mask pattern and the second mask pattern at the time of exposure. .

[Application Example 4]
This application example is a method of manufacturing a semiconductor device using the above-described photomask, and in an exposure step of exposing the photomask to a wafer of the semiconductor device, for a shot that does not expose the part pattern, For the shot in which the first mask pattern of the photomask is exposed and the part pattern is exposed, the second mask pattern of the photomask is exposed.

  According to this application example, a semiconductor device can be manufactured using a photomask that can be distinguished from the first mask pattern and the second mask pattern at the time of exposure without increasing the mask cost. The number of effective chips per piece of wear can be maximized.

[Application Example 5]
In the semiconductor device manufacturing method, the exposure step includes a projection unit that reduces and projects the photomask onto the wafer, and a mounting unit that mounts the wafer and freely moves in the X / Y-axis direction. In the case where the second mask pattern is exposed when the photomask is exposed to the wafer using an exposure apparatus (for example, a stepper apparatus), the mounting portion described above when the first mask pattern is exposed The position described above is moved in the X-axis direction and the Y-axis direction according to the distance on the wafer corresponding to the shift of the first mask pattern and the second mask pattern with respect to the position of You may align the said mounting part and the said projection part.

  According to this application example, it is possible to perform the necessary alignment by moving the placement portion to the first mask pattern and the second mask pattern.

The figure which shows typically an example of the photomask which concerns on this embodiment. The figure which shows typically the exposure image to the wafer of a photomask. 3A and 3B are views schematically showing another example of the photomask according to the present embodiment. The figure which shows typically an example of the photomask which concerns on a comparative example. The figure which shows typically the exposure image to the wafer of the photomask of a comparative example. The figure for demonstrating the structure of the exposure apparatus used for the manufacturing method of the semiconductor device in this Embodiment. The figure which showed the relationship between the exposure position of a 1st mask pattern, and the exposure position of a 2nd mask pattern. 6 is a flowchart showing a flow of exposure processing according to the present embodiment.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

1. FIG. 1 is a diagram schematically illustrating an example of a photomask according to the present embodiment.

  The photomask 100 includes a first mask pattern 110 and a second mask pattern 120. The first mask pattern 110 is arranged in a matrix of 5 × 5 (when n = 5 and m = 5 in n rows × m columns) where the chip sections 130 where the chip patterns 140 of the semiconductor device (device) are arranged. This is a mask pattern for one shot. In the first mask pattern 110, a chip pattern may be arranged in all chip sections 130. The chip pattern 140 arranged in the chip section 130 is a device pattern for forming an IC circuit pattern, for example. In this way, all shot areas on the wafer corresponding to the first mask pattern 110 become effective chip areas and no crushed chips are produced.

  The second mask pattern 120 is a one-shot mask pattern having the same size as the first mask pattern 110. The first mask pattern 110 and the second mask pattern 120 are n = 5, m = 5, a = 1, b = 4 rows × 4 columns ((na) rows × (mb) columns). In the case of 1), the chip sections 130 are shifted by a row and b columns so that the chip sections 130 overlap. In FIG. 1, the 16 chip sections 130 arranged in the overlapping area 160 are shared by the first mask pattern 110 and the second mask pattern 120.

  In the second mask pattern 120, a part pattern (alignment mark or TEG pattern, hereinafter referred to as “part pattern”) 150 used in a process step is arranged in at least one chip section 130. The part pattern 150 is arranged in the chip section 130 in a portion other than the overlapping area 160 between the second mask pattern 120 and the first mask pattern 110.

  The parts used in the process process are an alignment mark, a TEG (test element group), and the like. An alignment mark is a stylized pattern that is located at a specific location on the base to facilitate alignment. With the alignment mark formed on the wafer, for example, alignment with the photomask wafer can be performed in the exposure process.

  TEG (test element group) is an evaluation element for finding design and manufacturing problems that occur in LSI, and causes of problems that occur at various stages such as LSI process development, design, and manufacturing. In order to investigate the cause, it is possible to investigate the cause at an early stage by cutting out a part of an element or structure constituting the LSI or constructing a dedicated circuit suitable for investigating the cause.

  Since the part pattern 150 is arranged in a chip section 130 (in FIG. 1, nine chip sections correspond) located outside the overlapping area 160 of the second mask pattern 120, a maximum of nine chip sections 130 in FIG. Part patterns can be placed on In addition, the nine chip sections include three chip sections located at the four corners of the rectangular second mask pattern region, which is suitable for the arrangement of parts. A chip pattern is arranged in the chip section 130 where the part pattern 150 is not arranged.

  FIG. 1 shows a state in which the part patterns 150 are arranged in three chip sections 130 that do not belong to the overlapping area 160 among the four chip sections of the rectangular second mask pattern.

  In the first mask pattern, since the chip pattern is arranged in all of the 5 × 5 chip sections 130, 25 effective chip areas (areas where the chip pattern is formed) can be formed in one shot.

  In the second mask pattern, part patterns are arranged in three chip sections of a 5 × 5 chip section 130, and chip patterns are arranged in other areas. Therefore, 22 effective chip areas (chip patterns) are shot in one shot. Can be formed.

  As described above, in the present embodiment, the first shot area (the area on the wafer and the first mask pattern) which becomes the effective shot area (the shot area in which all the chip areas included in the shot area are effective chip areas). A first mask pattern 110 for exposing a region corresponding to (1) is designed. Then, the first mask pattern 110 is shifted by one chip section in the X and Y directions, and the second shot area (the area on the wafer and the second mask pattern is the same size as the first shot area). The second mask pattern 120 for exposing the region corresponding to (1) is designed. A part pattern of a part necessary for the process is arranged in an arbitrary chip section (chip section not belonging to the overlapping area 160) of the outermost chip section of the second mask pattern 120.

  If the number of parts per shot is constant (eg, 1 to 3), the photomask design technique is effective for increasing the number of effective chips per shot as the chip size decreases.

  The chip pattern 140 arranged in the chip section 130 is a device pattern for forming an IC circuit pattern, for example. On the wafer, a region outside the chip region where the chip pattern 140 is formed (a region between adjacent chip regions) is a scribe line. In the manufacturing process of a semiconductor device, for example, by dicing, the wafer can be cut along a scribe area that is the outer periphery of the chip area on the wafer (not shown), and the chip area (device) can be separated. The photomask design method of this embodiment can also be applied to a narrow scribe structure in which parts cannot be arranged on a scribe line.

  FIG. 2 is a diagram schematically showing an exposure image of the photomask 100 to the wafer 200. This figure shows a state in which twelve shot areas 210 (i, j) are exposed on a wafer 200 in a matrix of 3 rows × 4 columns. The shot areas 210 (2, 2), 210 (2, 4) are shot areas of the second mask pattern 120, and the other shot areas 210 (i, j) are shots of the first mask pattern 110. Region 210 (i, j).

  During normal exposure, the first mask pattern 110 of the photomask 100 is exposed on the wafer, and when a necessary mark is exposed due to the flow of the process, the second mask pattern 120 of the photomask 100 is exposed on the wafer. .

  In the shot areas 210 (2, 2) and 210 (2, 4) exposed to the second mask pattern, the area for three chips is used for the mark, so the number of effective chips per shot is reduced by three. Become.

  In FIGS. 1 and 2, the first mask pattern 110 and the second mask pattern 120 in the photomask have been described by taking the case where the chip sections 130 are shifted by one row and one column as an example. Not limited.

  3A and 3B are views schematically showing another example of the photomask according to the present embodiment. As shown in FIG. 3A, the first mask pattern 110 and the second mask pattern 120 may be arranged on the photomask 100 so as to be shifted by two rows and two columns of chip sections. Further, as shown in FIG. 3B, the first mask pattern 110 and the second mask pattern 120 may be arranged on the photomask 100 so as to be shifted by two rows and one column of chip sections. In addition to the above, the second mask pattern may be arranged by shifting the chip sections of arbitrary rows and columns.

2. FIG. 4 is a diagram schematically illustrating an example of a photomask according to a comparative example.

  The photomask 300 of the comparative example includes a mask pattern 310 corresponding to the effective shot area and a mask pattern 320 corresponding to the part arrangement area.

  The mask pattern 310 corresponding to the effective shot region is 1 in which the chip sections 130 in which the chip patterns 140 are arranged are arranged in a matrix of 5 × 5 (when n = 5 and m = 5 in n rows × m columns). This is a mask pattern for a shot. In the mask pattern 310 corresponding to the effective shot area, the chip pattern is arranged in all the chip sections 130. In this way, like the first mask pattern 110 of FIG. 1, all shot areas on the wafer corresponding to the mask pattern 310 corresponding to the effective shot area become effective chip areas and no crushed chips are produced.

  The mask pattern 320 corresponding to the part placement area is a mask corresponding to an area in which a part pattern (pattern such as an alignment mark or TEG (test element group), hereinafter referred to as “part pattern”) used in the process step is placed. It is a pattern. The mask pattern 320 corresponding to the part arrangement area is arranged in an area corresponding to five chip sections. As described above, in the comparative example, parts necessary for the process step are arranged outside the effective chip rear (an area where there is no crushed chip).

  When arranging parts necessary for process flow, an area including a mask pattern 310 corresponding to an effective shot area and a mask pattern 320 corresponding to a part arrangement area (hereinafter referred to as a mask pattern including an effective shot area and a part arrangement area). 330 ”) is exposed on the wafer as one shot area. The mask pattern 330 including the effective shot area and the part arrangement area is larger in size by one chip section (for five chip sections) than the mask pattern 310 corresponding to the effective shot area. Minutes are the squashed area.

  FIG. 5 is a diagram schematically showing an exposure image of the photomask of the comparative example onto the wafer. FIG. 5 shows a state where 12 shot areas 410 (i, j) are exposed on the wafer 400. The shot areas 410 (2, 2) and 410 (2, 4) are shot areas of the mask pattern 330 including the effective shot area and the part arrangement area, and the other shot areas are mask patterns corresponding to the effective shot area. 310 shot areas.

  In the comparative example, during normal exposure, the mask pattern 310 corresponding to the effective shot area of the photomask is exposed, and when necessary marks are exposed due to the flow of the process, the effective shot area and the part arrangement area of the photomask 300 are exposed. The wafer is exposed to a mask pattern 330 including

  In the shot area where the mask pattern 340 including the effective shot area and the part arrangement area is exposed, the area for five chips is used for the mark, so the number of effective chips per shot is reduced by five.

3. Manufacturing method of semiconductor device of this embodiment In this embodiment, a semiconductor wafer is exposed to light by using an exposure reticle (an example of a photomask) with a stepper device or the like which is a reduction projection exposure device, and a plurality of semiconductor devices Manufacturing. When manufacturing a semiconductor device such as a semiconductor integrated circuit or a solid-state imaging device, a reticle (photomask) on which a chip pattern having a size of about 5 to 10 times the size of a chip to be manufactured is used. A so-called stepper exposure method is known in which a large number of integrated circuit patterns are accurately exposed on a wafer on which a photoresist film is formed by repeatedly performing reduced projection exposure with a stepper apparatus while changing the position so as to be adjacent to the wafer. ing. In the stepper exposure method, photolithography is performed using a reticle (photomask) on which a rectangular mask pattern (a first mask pattern 110 or a second mask pattern 120) having a plurality of chip patterns 140 as shown in FIG. 1 is formed. Reduced projection exposure is continuously performed on the surface of the wafer on which the resist film is formed.

  Using the reticle (photomask 100) having the first mask pattern 110 and the second mask pattern 120 in this way, the mask pattern is continuously reduced and projected onto the wafer 200 on which the photoresist film is formed. Thus, exposure can be performed with an exposure image on the wafer as shown in FIG.

  FIG. 6 is a diagram for explaining the configuration of an exposure apparatus (stepper apparatus that is a reduction projection exposure apparatus) used in the method of manufacturing a semiconductor device in the present embodiment.

  The exposure apparatus 10 includes a light projection apparatus 1 that irradiates exposure light downward, and an exposure reticle that is provided on the lower side of the light projection apparatus 1 and is an exposure original plate (photomask) for performing reduced projection exposure. 2, a reduction projection apparatus 3 for reducing and projecting a mask pattern that has passed through an exposure reticle 2, and a table 5 that is mounted with a wafer 4 as a semiconductor substrate and is movable in the X and Y axis directions, and a photoresist film A mask pattern that has passed through the exposure reticle 2 is sequentially moved on the wafer 4 on which the wafer 4 is formed, and the wafer 4 is moved by the table 5 for exposure.

  At the time of exposure, a mask pattern is adjacently reduced and exposed repeatedly on the wafer 4 on which the photoresist film is formed. At the time of exposure, positioning is performed using alignment marks (an example of parts). Accordingly, during normal exposure, exposure is performed using the first mask pattern, and second mask patterns including alignment marks are sequentially exposed as necessary.

  When the first mask pattern is exposed using the photomask shown in FIG. 1, exposure is performed by masking portions other than the first mask pattern, and when the second mask pattern is exposed, the first mask pattern is exposed. The exposure is performed by masking portions other than the mask pattern 2.

  The light projection device 1, the exposure reticle 2, and the reduction projection device 3 function as a projection unit, and the table 5 functions as a placement unit. In this embodiment, the projection unit is fixed and the mounting unit (table 5) is moved in the X-axis and Y-axis directions to determine the shot position on the wafer.

  When the first mask pattern is continuously used, when the column is moved in the same row as the previous shot position, the wafer is mounted so that the X coordinate value of the wafer is displaced by one shot area. The position of the section (table 5) is moved. However, when the second mask pattern is exposed after the first mask pattern, a movement different from the movement for exposing the first mask pattern is required.

  FIG. 7 shows one of the exposure areas 212 of the first mask pattern and the exposure area 222 of the second mask pattern when the wafer 200 is fixed and the first mask pattern and the second mask pattern are exposed. It is the figure which showed the relationship of the position.

  Assuming that the vertical and horizontal sizes of the chip area are w × l, the exposure area 212 of the first mask pattern and the exposure area 222 of the second mask pattern correspond to a shift between the first mask pattern and the second mask pattern. Thus, it is shifted by w in the X-axis direction and l in the Y-axis direction on the wafer.

  Therefore, when the first mask pattern is exposed and when the second mask pattern is exposed, the exposure position is shifted by w in the X-axis direction and l in the Y-axis direction. Perform alignment.

  FIG. 8 is a flowchart showing a flow of exposure processing according to the present embodiment.

  Assume that the following exposure processing is performed according to a shot map in which N × M shot areas are defined, for example, as shown in the image of exposure to a wafer in FIG.

  Variables i and j indicating the vertical and horizontal dimensions of the matrix of the shot area (i, j) to be exposed are initially set (i = 1, j = 1) (step S10).

  The position of the table is controlled to move so that the shot area (i, j) on the wafer to be exposed comes to the reference exposure position (step S20). Here, it is assumed that the reference exposure position is a position where an exposure target area on the wafer overlaps with the exposure region 20 in FIG. When the first mask pattern 110 and the second mask pattern 120 are separated, the exposure area 212 of the first mask pattern 110 and the exposure area 222 of the second mask pattern 120 are shifted as shown in FIG. Therefore, here, it is assumed that the area that becomes the exposure region 212 of the first mask pattern 110 on the wafer is a position that overlaps the exposure region 20 of FIG.

  In the exposure apparatus, the process of exposing the mask pattern by moving the wafer in units of shot areas is repeated until completion for all shot areas. When the chip area on the wafer has a vertical and horizontal size w × l and the shot area is composed of chip areas arranged in an n × m matrix, the vertical and horizontal sizes of the shot area are nw + α in the horizontal direction and ml + β in the vertical direction. Become. Therefore, when shifting in the row direction by one shot, the table of nw + α should be moved in the positive direction of the X axis. That is, when i is incremented by 1, the table may be moved by nw + α in the positive direction of the X axis. When shifting one shot in the row direction, the table may be moved by ml + β in the positive Y-axis direction. That is, when j is incremented by 1, the table is moved by ml + β in the positive Y-axis direction and moved to the position of i = 1 in the X-axis direction. For example, when the number (number of columns) of shot areas in the X-axis direction is 4, the table is moved in the negative X-axis direction by (4-1) × (ml + α).

  When the part pattern is not exposed to the shot area (i, j) to be exposed (N in step S30), the first pattern is exposed (step S40).

  When the part pattern is exposed to the shot area (i, j) to be exposed (Y in step S30), a table corresponding to the deviation between the first mask pattern 110 and the second mask pattern 120 is further provided. Is controlled to move in the X-axis direction and the Y-axis direction (step S50). The first mask pattern 110 and the second mask pattern 120 have one chip area in the X-axis direction (horizontal length w of one chip area) and one chip area in the Y-axis direction (vertical length of one chip area). Since the length l) is shifted, the table is moved by that amount. Then, the second pattern is exposed (step S60). Next, the variable i is counted up (i = i + 1) (step S70). If i> N (Y in step S80), the variable i is initialized (i = 1) and the variable j is counted up (j = J + 1) (step S90). If j> M is not satisfied (N in step S100), the process returns to step S20 to repeat the processes in steps S20 to S100.

  Although the embodiments of the present invention have been described in detail as described above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Light projection apparatus 1, 2 Exposure reticle, 3 Reduction projection apparatus, 4 Wafer, 5 Table, 10 Exposure apparatus, 100 Photomask, 110 1st mask pattern, 120 2nd mask pattern, 130 Chip division, 140 chip Pattern, 150 part pattern, 200 wafer, 210 (i, j) shot section, 300 comparative photomask, 310 mask pattern corresponding to effective shot area, 320 mask pattern corresponding to part placement area, 330 effective shot area Mask patterns 330 and 400 including part arrangement regions Wafers of comparative examples

Claims (5)

A first mask pattern which is a mask pattern for one shot in which chip sections in which chip patterns are arranged are arranged in a matrix of n rows × m columns, and the same size as the first mask pattern, and at least 1 A second mask pattern that is a mask pattern for one shot in which a part pattern to be used in a process step is disposed in one of the chip sections,
The first mask pattern and the second mask pattern are arranged by shifting chip sections by a row and b columns so that chip sections of (na) rows × (m−b) columns overlap. And
The second mask pattern is a photomask in which the part pattern is arranged in a chip section in a portion other than an overlapping area with the first mask pattern. In claim 1,
A photomask in which a = 1 and b = 1. In claim 1 or 2,
The first mask pattern is a photomask in which chip patterns are arranged in all chip sections. A method for manufacturing a semiconductor device using the photomask according to any one of claims 1 to 3,
In an exposure process of exposing the photomask to a wafer of a semiconductor device,
For shots that do not expose the part pattern, expose the first mask pattern of the photomask,
For the shot for exposing the part pattern, a method for manufacturing a semiconductor device for exposing the second mask pattern of the photomask. In claim 4,
In the exposure step,
The photomask is exposed onto the wafer using an exposure apparatus that includes a projection unit that reduces and projects the photomask onto the wafer and a placement unit that places the wafer and is movable in the X / Y-axis direction. When
In the case of exposing the second mask pattern, the first mask pattern and the second mask pattern are shifted with respect to the position of the placement portion in the case of exposing the first mask pattern. A method of manufacturing a semiconductor device, wherein the mounting unit is moved in the X-axis direction and the Y-axis direction according to the corresponding distance on the wafer, and the mounting unit and the projection unit are aligned.

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