JP2006310446A - Manufacturing method of semiconductor device, and exposure device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of reducing the connection misalignment between divided pattern regions when a chip pattern is plurally divided and divided exposures are carried out. <P>SOLUTION: This manufacturing method comprises the steps of preparing a photomask set wherein at least one of a plurality of photomasks corresponding to a plurality of divided patterns obtained by plurally dividing the chip pattern respectively has an alignment mark, transferring a pattern including the alignment mark to a first photoresist applied on a substrate using the photomask having the alignment mark, forming the pattern including the alignment mark on the substrate by carrying out etching processing using the first photoresist as a mask, applying a second photoresist on the substrate having the pattern including the alignment mark formed thereon, and carrying out the alignment between a photomask for forming a pattern on the second photoresist and the substrate using the alignment mark. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a manufacturing method of a semiconductor device such as a semiconductor element such as a memory and a logic, a liquid crystal display element, and an imaging element (CCD sensor, CMOS sensor), and an exposure apparatus.

  Conventionally, when manufacturing a semiconductor device such as a liquid crystal display element and an image sensor, a desired chip pattern formed on a photomask is exposed to a photoresist coated on a substrate using a projection exposure apparatus. Etching or impurity ion implantation is performed on the substrate using the resist pattern. A step-and-repeat stepper or a step-and-scan scanner is often used for the projection exposure apparatus. Note that a photomask used in a projection exposure apparatus is generally referred to as a reticle. Therefore, hereinafter, a photomask used in a projection exposure apparatus is referred to as a reticle. The projection exposure apparatus is simply referred to as an exposure apparatus. In addition, the “substrate” is not limited to the semiconductor substrate itself, but includes a semiconductor device being manufactured on the semiconductor substrate, and is hereinafter referred to as a wafer.

  Depending on the chip pattern, the size may be larger than the exposure range determined by the projection optical system performance of the exposure apparatus. In such a case, divided exposure is used. Divided exposure refers to an exposure method in which a desired chip pattern is divided into a plurality of patterns and an exposure process is performed for each divided pattern. All the divided patterns are finally connected to form the chip pattern. Such divided exposure may be used in the manufacture of liquid crystal display elements as well as imaging elements such as CCD (Charge Coupled Device) sensors and CMOS (Complementary Metal Oxide Semiconductor) sensors (see Patent Document 1).

  In general, since elements are formed by stacking multiple layers of circuit patterns on a wafer, in order for manufactured elements to meet the design specifications, the overlay accuracy of circuit patterns related to each other must be within a predetermined allowable range. It is necessary to fit in. Therefore, when the reticle pattern is exposed on the photoresist on the wafer by the exposure apparatus, the wafer and the reticle are aligned. For this purpose, alignment marks formed on the wafer are used. The alignment mark is provided on the reticle as a predetermined pattern such as a cross shape, a lattice shape, or a double round shape. This is transferred to the photoresist on the wafer and formed as a three-dimensional step on the wafer by etching. By using this alignment mark, it is possible to align the wafer and the reticle in the subsequent exposure process. Japanese Patent Application Laid-Open No. 2004-228688 discloses a divided exposure method for a photosensitive resist or the like in a manufacturing process of a thick thin film hybrid substrate in which an organic insulating film and a metal wiring film are laminated on a wiring substrate such as ceramic.

  A method for forming a desired chip pattern by divided exposure using a stepper in the first exposure process in the manufacturing process of such an element will be specifically described.

  FIG. 11 is a schematic external view showing an example of the size and arrangement of chips formed on a wafer. As shown in FIG. 11, five elements 2 are arranged on the wafer 1 in the vertical direction (Y direction) in the figure. Two rows arranged in the Y direction are provided in the horizontal direction (X direction) in the figure. A total of 10 (= 5 × 2 columns) elements 2 are arranged on the wafer 1. Note that the circuit pattern of the element 2 is not shown in the figure.

  FIG. 12 shows the shape and size of the chip pattern and exposure range. As shown in FIG. 12, the exposure range 3 is substantially square, whereas the chip pattern 20 of the element 2 shown in FIG. 11 is rectangular. Further, the direction along the long side of the chip pattern 20 is the X direction, and the direction along the short side is the Y direction. The chip pattern 20 has a length in the X direction that is longer than one side of the exposure range 3 of the stepper. When the chip pattern 20 protrudes from the exposure range 3 in the X direction as described above, the chip pattern 20 is divided into sizes that can be exposed.

  FIG. 13 is a diagram showing a state where the chip pattern shown in FIG. 12 is divided into sizes that can be exposed. The chip pattern 20 including the circuit pattern is divided into three sizes that can be exposed. Hereinafter, one of the patterns obtained by dividing the chip pattern 20 into a plurality is referred to as a divided pattern, and an area occupied by the divided pattern is referred to as a divided pattern area. As shown in FIG. 13, the chip pattern 20 is divided into three in the X direction, and is divided into divided pattern areas A, B, and C. Then, an exposure process is performed for each of the divided pattern areas A, B, and C by a method described later. The arrangement of the divided pattern areas shown in FIG. 13 indicates the order when transferred to the photoresist on the wafer. The reticles corresponding to the divided pattern areas are RA, RB, and RC. 11 and 13 specify chip arrangement reference information that is information including the arrangement of the chip of the element 2 on the wafer and the arrangement of the divided pattern areas A, B, and C in the chip. The procedure of the pattern forming method will be described below.

  FIG. 14 is a diagram showing a pattern forming method of the chip pattern shown in FIG. A wafer coated with a photoresist by spin coating is prepared. Hereinafter, a wafer coated with a photoresist is referred to as a resist-coated wafer. An operator sets reticles RA, RB and RC in the exposure apparatus in advance.

  The exposure apparatus mounts a reticle RA on a reticle stage on which the reticle is placed, and aligns the reticle RA and the reticle stage. Then, the exposure apparatus refers to the chip arrangement reference information, moves the resist-attached wafer 7 to the exposure start position, and then exposes the divided pattern region A to the photoresist at a position 50a shown in FIG. Subsequently, each time the resist-attached wafer 7 is moved by a predetermined distance from the upper right position 50a to the lower right position 50b by the step-and-repeat method with reference to the chip arrangement reference information (step S3). The reticle RA is irradiated with illumination light to expose the divided pattern region A on the photoresist. Here, the predetermined distance moved in the −Y direction by the stepping operation is equal to the length of the element 2 in the Y direction.

  When the exposure processing is completed to the lower right position 50b in FIG. 14A, the resist-attached wafer 7 is moved in the −X direction by a predetermined distance with reference to the chip arrangement reference information, and the divided pattern region A is formed on the photoresist. To expose. The position after the movement is indicated by reference numeral 50c. Here, the predetermined distance moved in the −X direction from the position 50b to the position 50c is equal to the sum of the lengths of the divided pattern regions B and C in the X direction. Subsequently, with reference to the chip arrangement reference information, every time the resist-coated wafer 7 is moved by a predetermined distance to the uppermost position 50d in the upward direction (Y direction) of FIG. 14A by the step-and-repeat method. Then, the reticle RA is irradiated with illumination light to expose the divided pattern region A on the photoresist. Here, the predetermined distance moved in the Y direction by the stepping operation is equal to the length of the element 2 in the Y direction. In this way, as shown in FIG. 14A, two rows of regions in which five divided pattern regions A are arranged and exposed in the Y direction are formed in the photoresist.

  Subsequently, the exposure apparatus replaces the reticle RA on the reticle stage with the reticle RB, and aligns the reticle RB with the reticle stage. Thereafter, the divided pattern region B is exposed to the photoresist each time the resist-coated wafer 7 is moved by a predetermined distance in the same manner as the divided pattern region A by the step-and-repeat method. At that time, as shown in FIG. 14B, the area where the divided pattern area B is exposed is positioned in the adjacent area in the −X direction with respect to the area where the divided pattern area A is exposed. In this way, the divided pattern area B is exposed to the photoresist adjacent to each area of the divided pattern area A.

  Furthermore, the exposure apparatus replaces reticle RB on the reticle stage with reticle RC, and aligns reticle RC with the reticle stage. Then, the divided pattern area C is exposed to the photoresist each time the resist-coated wafer 7 is moved by a predetermined distance in the same manner as the divided pattern area A by the step-and-repeat method. At this time, as shown in FIG. 14C, the region where the divided pattern region C is exposed is positioned in the adjacent region in the −X direction with respect to the region where the divided pattern region B is exposed. In this way, the divided pattern region C is exposed to the photoresist adjacent to each region of the divided pattern region B.

By separately performing the exposure processing of the divided pattern areas A, B, and C by the above-described method, a desired chip pattern can be exposed to the photoresist even if the chip size is larger than the exposure range at the capability limit of the exposure apparatus. Thereafter, development processing is performed to form a resist pattern having a desired chip pattern. Then, when an etching process is performed using the resist pattern as a mask, a desired chip pattern is formed as a step on the wafer. FIG. 14D shows the state of the wafer after the resist is removed, and ten chip patterns 20 are formed as steps on the wafer.
JP 61-180275 A Japanese Patent Laid-Open No. 09-185176

  In the pattern forming method described above, when performing the divided exposure in the first exposure process in the element manufacturing process, the exposure apparatus determines the exposure positions of the divided pattern areas A, B, and C by the stepping operation based on the chip arrangement reference information. is doing. In this case, the accuracy of the position where the divided pattern region is exposed on the wafer greatly depends on the accuracy of the stepping operation of the exposure apparatus. The problem in this case is the accuracy of adjacent connection between the divided pattern areas.

  As the circuit pattern of the element portion in the desired chip pattern becomes finer, the influence on the circuit pattern at the connection boundary position of each divided pattern region cannot be ignored. This will be described in the case of a circuit pattern having a fine wiring having the width of the minimum pattern size of the resolution limit of the exposure apparatus. If fine wiring that spans two adjacent divided pattern areas is provided in the circuit design, when these two divided pattern areas are connected, the connection positions of the fine wiring that straddle between the areas do not match due to the effect of misalignment. There is a fear. At this time, a part of the fine wiring in the circuit pattern is disconnected, and the manufactured element does not function.

  As a countermeasure against the above-described problem due to the misalignment, it is also conceivable to avoid the influence of the misalignment by not forming the fine wiring at the boundary position where the connection between the divided pattern areas occurs. However, in the case of an imaging device in which a predetermined pattern is repeatedly arranged on a large imaging surface, it is difficult to use such an avoidance measure because the connecting position is applied to the imaging surface.

  The present invention has been made in order to solve the problems of the conventional techniques as described above, and to reduce the misalignment between divided pattern areas when a chip pattern is divided into a plurality of pieces and divided exposure is performed. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing the above and an exposure apparatus.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention provides a photomask set in which at least one of a plurality of photomasks corresponding to each of a plurality of divided patterns obtained by dividing a chip pattern into a plurality of divided patterns has an alignment mark. A preparation process;
Transferring a pattern including the alignment mark to a first photoresist applied on a substrate using a photomask having the alignment mark;
Forming a pattern including the alignment marks on the substrate by performing an etching process using the first photoresist as a mask;
Applying a second photoresist on a substrate on which a pattern including the alignment mark is formed;
Performing alignment between a photomask for forming a pattern on the second photoresist and the substrate using an alignment mark formed on the substrate;
It is what has.

  According to the present invention, an exposure area of a pattern corresponding to a photomask at the time of divided exposure is determined with higher accuracy. Compared to the case where the divided patterns are continuously exposed depending only on the stepping operation accuracy of the exposure apparatus, the connection shift between the divided patterns is reduced.

  In the method of manufacturing a semiconductor device according to the present invention, when a chip pattern is divided and exposed, at least an alignment mark pattern is formed on the substrate by the first divided exposure, and the alignment mark is used for the subsequent divided exposure and a photomask. Exposure is performed after alignment with the substrate.

  A method for manufacturing a semiconductor device of the present invention will be described. Hereinafter, the semiconductor device is referred to as an element.

  The chip pattern used here and its arrangement are the same as those shown in FIG. The chip pattern 20 of the element 2 shown in FIGS. 11 to 14 is a pattern of at least one of the multiple layers of circuit patterns constituting the element. 11 and 13, the chip arrangement reference information is specified as in the conventional case. The exposure apparatus uses an exposure apparatus having an exposure range as shown in FIG. Furthermore, it is assumed that the exposure is divided into the three divided pattern areas A, B and C shown in FIG. The reticles corresponding to the divided pattern areas A, B, and C are RA, RB, and RC, respectively.

  At least one of the three reticles RA, RB and RC is provided with an alignment mark for alignment with the other two. FIG. 1 is a diagram showing a case where alignment marks are arranged on the reticle RA. As shown in FIG. 1, the reticle RA is formed with alignment marks 10 for aligning the other reticles RB and RC with the divided pattern region A in each of the X direction and the Y direction.

  The procedure of the pattern forming method of the present invention for the chip pattern shown in FIG. 13 will be described.

  FIG. 2 is a diagram showing a pattern forming method. A resist-coated wafer 7 in which a photoresist is applied to the wafer is prepared. When the reticle RA is mounted on the reticle stage of the exposure apparatus, the exposure apparatus aligns the reticle RA and the reticle stage. When the resist-attached wafer 7 is set in the exposure apparatus, the exposure apparatus mounts the resist-attached wafer 7 on the wafer stage. Subsequently, as shown in FIG. 2A, the exposure apparatus moves the resist-coated wafer 7 at a predetermined distance obtained from the chip arrangement reference information in each of the X direction and the Y direction by the step-and-repeat method. For each movement, illumination light is irradiated onto the reticle RA to sequentially expose the divided pattern areas A on the photoresist. The image of reticle RA shown in FIG. 1 is exposed to the photoresist while being vertically and horizontally reversed through the lens when it is reduced and projected by the exposure apparatus.

  Subsequently, after the resist-attached wafer 7 is taken out from the exposure apparatus, the resist in which the divided pattern region A is exposed is developed to form a resist pattern in the divided pattern region A. Then, an etching process is performed using the resist pattern as a mask, and the divided pattern area A is formed as a step (pattern) on the wafer. At that time, of course, the alignment mark arranged on the reticle RA is also formed as a step on the wafer by the etching process.

  Next, a photoresist is applied again on the etched wafer. A wafer coated with a photoresist again is referred to as a resist-attached wafer. The reticle RB is mounted on the reticle stage of the exposure apparatus, and the alignment between the reticle RB and the reticle stage is performed. Subsequently, the resist-attached wafer 7 is set in an exposure apparatus, and the resist-attached wafer 7 is mounted on the wafer stage. Thereafter, several shots of alignment marks formed together with the divided pattern area A are measured, and the arrangement information indicating the coordinate position on the wafer of the divided pattern area A is examined. Then, components such as a shift in the X direction and a Y direction of the divided pattern region A, a rotational deviation, and a magnification error are obtained from the examined arrangement information. Further, the coordinate system of the original chip arrangement reference information is corrected in consideration of these components. Hereinafter, the corrected coordinate system is referred to as a corrected coordinate system.

  Subsequently, the resist-attached wafer 7 is moved to the exposure start position of the divided pattern region B of the chip arrangement reference information with reference to the correction coordinate system, and the reticle RB is irradiated with illumination light to expose the divided pattern region B on the photoresist. To do. Further, the resist-attached wafer 7 is moved by a predetermined distance in each of the X direction and the Y direction by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. Then, for each movement, exposure processing of the divided pattern region B is sequentially performed as shown in FIG. At this time, the exposure area of each divided pattern area B is an area adjacent to the area where the divided pattern area A is formed in the −X direction.

  Subsequently, the reticle on the reticle stage is exchanged from RB to RC, and alignment between the reticle RC and the reticle stage is performed. Then, the exposure start position of the divided pattern area C of the chip arrangement reference information is obtained with reference to the correction coordinate system obtained before the exposure of the divided pattern area B. Then, the resist-coated wafer 7 is moved to the obtained exposure start position, and the reticle RC is irradiated with illumination light to expose the divided pattern region C on the photoresist. Further, the resist-attached wafer 7 is moved by a predetermined distance in each of the X direction and the Y direction by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. Then, as shown in FIG. 2C, the exposure processing of the divided pattern region C is sequentially performed. At this time, the exposure area of each divided pattern area C is an area adjacent to the −X direction of the area where the divided pattern area B is exposed.

  Then, after the resist-attached wafer 7 is taken out from the exposure apparatus, the photoresist on which the divided pattern areas B and C are exposed is subjected to development processing to form resist patterns in the divided pattern areas B and C. Etching is performed using the resist pattern as a mask to form divided pattern regions B and C as steps on the wafer. The area of the divided pattern area A formed by the etching process is not exposed when the divided pattern areas B and C are exposed. Therefore, the area is still covered with the photoresist after the development process. Not receive. In this way, the divided pattern region A is first exposed and etched, and then the divided pattern regions B and C are exposed and etched to obtain a desired chip pattern as shown in FIG. Can be formed on the wafer 1. In FIG. 2D, ten chip patterns 20 of elements are formed as steps on the wafer 1.

  As described above, the arrangement information on the wafer of the divided pattern area A is measured, and based on this arrangement information, a correction coordinate system for exposing the division pattern areas B and C on the wafer is obtained. The stepping operation of the exposure apparatus is performed with reference. Since the alignment of the wafer and the reticles RB and RC is performed using alignment marks directly formed on the wafer, the exposure areas of the divided pattern areas B and C with respect to the position of the divided pattern area A formed on the wafer Is determined more accurately. As a result, the gap between the divided pattern regions is less than when the reticles RA, RB, and RC are continuously exposed on a wafer on which no alignment mark is formed, depending on only the stepping operation accuracy of the exposure apparatus. To reduce.

  The alignment mark used in the present invention may be an alignment mark used for aligning the reticle and wafer in the subsequent exposure process in the device manufacturing process.

The desired chip pattern dividing method according to the present invention is not limited to the above-described case and has the following degrees of freedom. For example, in the above-described case, an alignment mark is included together with a part of the circuit pattern in one of the divided pattern areas when the entire chip pattern is divided into a plurality of divided pattern areas. Alternatively, a reticle having a pattern from which only the pattern is extracted may be prepared.
(First embodiment)
The structure of a stepper as an exposure apparatus used when the semiconductor device manufacturing method of the present embodiment is carried out will be briefly described.

  FIG. 3 is a diagram for explaining the configuration of the stepper. The stepper mounts an illumination system 100 including a light source and an illumination optical system, a reticle stage 104 for mounting the reticle 102, a projection optical system 106 that reduces the reticle image and projects it onto the wafer 108, and a wafer 108. The wafer stage 110 and a control unit 112 that controls each unit are configured. The control unit 112 is communicably connected to a reticle alignment system 114 serving as a drive unit for the reticle stage 104 and a stage drive unit 116 serving as a drive unit for the wafer stage 110. The control unit 112 includes a CPU that executes predetermined processing according to a program and a memory for storing the program. As the illumination light, one of excimer lasers such as KrF and ArF excimer laser light, or one of g-line and i-line by an ultra-high pressure mercury lamp is mainly used.

  Further, the stepper is provided with a wafer alignment scope (hereinafter simply referred to as a scope) 118 serving as a detection unit for detecting alignment marks formed on the wafer. The alignment mark detection method in the present embodiment is an off-axis method in which the alignment mark is detected by a microscope provided separately from the projection optical system 106. The alignment mark detection method is not limited to the off-axis method, and may be a TTL method that detects an image of the alignment mark that has passed through the projection optical system 106 with a TTL (Through The Lens) microscope.

  A reticle transport system (not shown) for mounting the reticle 102 on the reticle stage 104 is also provided. Furthermore, a pre-alignment stage (not shown) for detecting a wafer reference position such as an orientation flat or notch and positioning the whole wafer (hereinafter, this positioning is referred to as “mechanical pre-alignment”), and a pre-alignment stage A feeding hand (not shown) for moving the wafer from the wafer stage 110 to the wafer stage 110 is provided.

  The configuration of each part will be described in detail below.

  The reticle alignment system 114 performs alignment between the reticle 102 and the reticle stage 104. The reticle alignment system 114 moves the reticle stage 104 to a predetermined position below the illumination system 100 according to a control signal from the control unit 112. When the illumination light generated by the illumination system 100 is irradiated onto the reticle 102 mounted on the reticle stage 104, the reticle pattern passes through the projection optical system 106 by the illumination light that has passed through the reticle 102, and a reduced image of the reticle 102 is formed on the wafer. Projection exposure is performed on the coated photoresist. The reduced image of the reticle 102 is generally 1/2 times, 1/4 times, or 1/5 times the reticle pattern.

  Wafer stage 110 places wafer 108 such that a reduced image of reticle 102 is projected onto an area where a chip pattern is formed based on chip placement reference information. Therefore, two-dimensional coordinates for an arbitrary position with the home position as the origin are determined in advance. The stage drive unit 116 is provided with a coordinate sensor for measuring coordinates in the X direction and the Y direction from the home position of the wafer stage 116. Based on the X direction and Y direction distance data received from the control unit 112, the stage drive unit 116 linearly steps the wafer stage 110 in a predetermined XY two-dimensional direction using an air bearing and a linear motor. Then, in order to notify the control unit 112 of the position of the wafer stage 110, coordinate information indicating the X-direction and Y-direction coordinates read from the coordinate sensor is sent to the control unit 112. In this way, the wafer can be moved to a predetermined position at high speed and positioned. When the operator inputs the chip arrangement reference information to the control unit 112 in advance, the movement distances in the X direction and the Y direction of the wafer stage 110 in the exposure process are set in the program of the control unit 112. The stage drive unit 116 also has a mechanism for driving in the focus direction (Z direction) and tilt (Θ direction) in order to adjust the tilt of the wafer surface and the distance from the imaging plane of the projection optical system. Yes.

  The scope 118 is provided with an image sensor such as a CCD, and is connected to the control unit 112 through communication wiring. An image captured by the imaging element of the scope 118 is input to the control unit 112 via a communication wiring. The reference alignment mark image and position information are registered in the control unit 112 in advance.

  The controller 112 detects the alignment mark as follows. The control unit 112 operates the stage driving unit 116 with reference to the position information so that the alignment mark is positioned under the scope 118. Subsequently, when an image of an alignment mark registered in advance is included in the image received from the scope 118, the stage driving unit 116 is finely adjusted and operated so that the images of the two alignment marks overlap. When the two alignment mark images overlap, the coordinate information of the wafer stage 110 at that time is registered in the memory.

  The control unit 112 corrects the coordinate system of the chip placement reference information as follows. The control unit 112 detects the alignment mark near the center of the wafer among the plurality of alignment marks formed on the wafer with reference to the chip arrangement reference information by the method described above. The coordinate information of the alignment mark near the center is registered in the memory. Similarly, alignment marks for several shots around the wafer are detected and their coordinate information is registered in the memory. After measuring the alignment marks for several shots in this way, the measurement results are statistically calculated to obtain alignment information on the alignment marks on the wafer. It should be noted that this arrangement information matches the arrangement information of the division pattern if the division pattern is formed on the wafer together with the alignment mark. Subsequently, a corrected coordinate system in which the coordinate system of the chip arrangement reference information is corrected in consideration of the shift component, the rotation component, and the magnification component in the X direction and Y direction of the divided pattern obtained from the array information is obtained.

  After obtaining the correction coordinate system as described above, the control unit 112 refers to the chip arrangement reference information based on the correction coordinate system during the exposure processing in the divided exposure, and performs wafers in each of the X direction and the Y direction. The movement distance is calculated, and the obtained movement distance data in the X direction and the Y direction are transmitted to the stage driving unit 116. In this way, by correcting the coordinate system for determining the position where the exposure processing is performed using the array information, the accuracy of alignment between the wafer and the reticle is further improved.

  Here, a specific example of a method for aligning the wafer and the reticle by correcting the coordinate system will be described. Here, for the sake of simple explanation, it is assumed that the alignment mark formed on the wafer is shifted in the + X direction. Further, the alignment mark of the chip arrangement reference information is referred to as a reference mark, and the alignment mark formed on the wafer is referred to as an actual mark.

  The actual mark is superimposed on the coordinates of the reference mark in the shot near the wafer center. Using this position as a reference point, the positional deviation between the reference mark and the actual mark is measured at the position moved by three shots and the position moved by five shots in the + X direction from the reference point in accordance with the chip placement reference information. It is assumed that the positional deviation at the position moved by 3 shots is 0.02 μm and the positional deviation at the position moved by 5 shots is 0.04 μm. It is possible to predict the positional deviation of each shot with respect to the + X direction based on the arrangement information due to these positional deviations.

  In this specific example, when exposing a shot near the center of the wafer, the wafer and the reticle are aligned so that the alignment marks overlap, and the exposure is performed for each shot in the + X direction from the vicinity of the center. Exposure is performed by aligning the wafer and reticle in anticipation of misalignment.

  Next, a method for manufacturing a semiconductor device of the present invention using the stepper having the above-described configuration will be described with reference to FIGS. 4 to 7, the horizontal direction in the figure is the X direction, and the vertical direction in the figure is the Y direction. A semiconductor device is referred to as an element.

  FIG. 4 is a plan view showing the appearance of the chip pattern of the element. Note that illustration of circuit patterns in the chip is omitted.

  As shown in FIG. 4, the chip pattern 11 has a length in the X direction of 48 mm, a length in the Y direction of 22 mm, and is elongated in the X direction. The minimum pattern size of the element inside the chip is 0.25 μm. As a stepper capable of exposing a circuit pattern of 0.25 μm, there is a stepper using a KrF excimer laser or an ArF excimer laser as a light source. In this embodiment, a stepper using a KrF excimer laser as a light source is used. The exposure range of this stepper is 22 mm square.

  FIG. 5 shows the chip shown in FIG. 4 divided for divided exposure.

  Since the exposure area of the stepper is a 22 mm square, as shown in FIG. 5, the divided pattern areas A, B, and B are divided into three equal parts along the X direction which is the longitudinal direction of the chip. C. The length of each divided pattern region in the X direction is 16 mm. Then, reticles RA, RB, and RC corresponding to the divided pattern areas A, B, and C are prepared. Using the reticles RA, RB, and RC, the divided pattern regions A, B, and C having a length of 16 mm in the X direction and a length of 22 mm in the Y direction are exposed to the photoresist in this order. The arrangement of the divided pattern areas shown in FIG. 5 indicates the order when transferred to the photoresist. The information including the arrangement of the chip shown in FIGS. 4 and 5 on the wafer and the arrangement of each divided pattern in the chip is the chip arrangement reference information.

  Next, the reticle used in this embodiment will be described.

  FIG. 6 is a schematic diagram showing reticle RA. As shown in FIG. 6, at least one wafer alignment mark 10 that can be measured by the scope 118 is arranged in each of the X direction and the Y direction on the reticle RA used for the first exposure process. Further, it is desirable to provide a pre-alignment mark for performing alignment on the wafer stage 110 before alignment by the wafer alignment mark 10, and the reticle RA shown in FIG. 6 is provided with the pre-alignment mark 15. The reason for providing the pre-alignment mark 15 is that measurement of the pre-alignment mark 15 is performed after the mechanical pre-alignment is completed and before the wafer alignment mark 10 is aligned with the wafer transferred onto the wafer stage 110. This is because it becomes possible to make the wafer alignment mark 10 fall within the detection range of the scope 118. In addition, the pre-alignment mark 15 and the wafer alignment mark 10 are included in the divided pattern area A corresponding to the reticle RA.

  Note that wafer alignment marks and pre-alignment marks may be arranged not only on the reticle RA corresponding to the divided pattern region A to be exposed first but also on the remaining reticles RB and RC in the same manner as the reticle RA.

  Next, the procedure of the pattern forming method using the above-described reticle will be described.

  FIG. 7 is a diagram for explaining the procedure of the pattern forming method. Here, it is assumed that a pattern is formed on a wafer on which a wafer alignment mark is not formed since the first exposure process and the subsequent etching process are not yet performed in the manufacturing process of the semiconductor device.

  First, a photoresist is formed on a wafer by the following procedure. The wafer is heat-treated in a resist coating apparatus in an HMDS (hexamethyldisilane) atmosphere. Thereafter, a photoresist is applied, followed by heat treatment (referred to as pre-baking or soft baking) at an appropriate temperature. A wafer coated with a photoresist is referred to as a resist-attached wafer.

  After the reticles RA, RB and RC are set in advance on the stepper, the reticle transport system is operated to mount the reticle RA on the reticle stage 104 and perform reticle alignment to position the reticle RA.

  When the resist-attached wafer 7 is set on the stepper, the stepper performs mechanical pre-alignment on the wafer in the apparatus, and then moves the resist-attached wafer 7 to the wafer stage 110 via the feeding hand. Then, the resist-attached wafer 7 is moved by the distance set by the chip arrangement reference information in the X direction and the Y direction by the step-and-repeat method. For each movement, illumination light is irradiated onto the reticle RA to sequentially expose the divided pattern areas A on the photoresist.

  Thereafter, the resist-coated wafer 7 for which the exposure processing of the divided pattern region A has been completed is developed in the following procedure. In the resist developing apparatus, after the overheat treatment (referred to as post-exposure baking or PEB) immediately after exposure is performed on the photoresist at an appropriate temperature, development processing is performed with a developer. Subsequently, a water washing treatment is performed, and a heat treatment at an appropriate temperature (referred to as post-baking or hard baking) and / or a light irradiation treatment with UV light or the like is performed again. Then, a resist pattern of the divided pattern region A as shown in FIG. 7A is formed on the wafer. Etching is performed using the photoresist in which the pattern of the divided pattern area A is formed in this manner as a mask, and the divided pattern area A is formed as an etching step on the wafer. By this etching process, the wafer alignment mark 10 and the pre-alignment mark 15 arranged on the reticle RA are also formed as a step pattern on the wafer. Thereafter, ashing is performed to remove the photoresist remaining on the wafer, and the photoresist residue is also removed using an appropriate stripping solution. Note that resist removal by ashing and / or resist residue removal by a stripping solution is not essential. As will be described below, it is desirable to carry out in order to suppress the occurrence of coating abnormality when a photoresist is applied for the exposure processing of the divided pattern regions B and C.

  Thereafter, a photoresist is applied again on the wafer in the same manner as in the resist coating method in forming the divided pattern region A. A wafer coated with a photoresist again is referred to as a resist-attached wafer.

  Next, in order to perform the exposure processing of the divided pattern region B, the reticle RA is taken out from the reticle stage, the reticle RB is mounted on the reticle stage 104, and reticle alignment is performed. Then, the pre-registration wafer 7 is mechanically pre-aligned in the apparatus, and the resist-added wafer 7 is moved to the wafer stage 110 via the feeding hand.

  Subsequently, the control unit 112 of the stepper causes the scope 118 to detect the pre-alignment mark 15 so that the alignment mark 10 enters the imaging range of the scope 118. Further, the alignment marks 10 in the X direction and the Y direction are measured by the method described above corresponding to several shots of the divided pattern area A in the wafer. The control unit 112 obtains the arrangement information of the divided pattern area A on the wafer from the measurement result of the wafer alignment mark 10.

  Thereafter, a correction coordinate system is obtained by correcting the coordinate system of the chip arrangement reference information in consideration of the shift component, the rotation component, and the magnification component in the X and Y directions of the divided pattern area A obtained from the arrangement information. Subsequently, the resist-attached wafer 7 is moved to the exposure start position of the divided pattern region B with reference to the chip arrangement reference information based on the correction coordinate system. Then, the illumination light is irradiated onto the reticle RB at the exposure start position to perform exposure processing of the divided pattern region B.

  Further, the resist-attached wafer 7 is moved from the exposure start position by a predetermined distance in the X and Y directions by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. Then, for each movement, as shown in FIG. 7B, illumination light is irradiated onto the reticle RB to sequentially expose the divided pattern regions B. In the case of the present embodiment, the divided pattern region B is exposed to a region adjacent to the −X direction of the region where the divided pattern region A is formed. The area adjacent to the −X direction of the area where the divided pattern area A is formed is an area 16 mm away from the divided pattern area A in the left direction in the drawing in the wafer external view shown in FIG. In this way, as shown in FIG. 7B, the exposed area of the divided pattern area B is formed in the photoresist on the wafer.

  Next, in order to perform the exposure processing of the divided pattern region C, the reticle RB is taken out from the reticle stage, the reticle RC is mounted on the reticle stage 104, and reticle alignment is performed. On the other hand, the resist-coated wafer 7 on which the divided pattern region B is exposed is left on the wafer stage 110 as it is.

  After the reticle alignment of the reticle RC is completed, the resist-attached wafer 7 is moved to the exposure start position of the divided pattern region C with reference to the chip arrangement reference information based on the correction coordinate system. Then, the illumination light is irradiated onto the reticle RC at the exposure start position, and the divided pattern region C is exposed. Further, the wafer is moved by a predetermined distance in the X direction and the Y direction from the exposure start position by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. For each movement, as shown in FIG. 7C, illumination light is irradiated onto the reticle RC to sequentially expose the divided pattern regions C.

  In the case of the present embodiment, the divided pattern region C is exposed to a region adjacent to the −X direction of the region where the divided pattern region B is formed. The region adjacent to the −X direction of the region in which the divided pattern region B is formed is 16 mm on the left side of the divided pattern region B in the wafer external view shown in FIG. The region is 32 mm away from the left side. In this way, as shown in FIG. 7C, the exposed area of the divided pattern area C is formed in the photoresist on the wafer.

  In the above-described case, the correction coordinate system obtained before the exposure of the divided pattern area B was used in the exposure process of the divided pattern area C. However, even if the wafer alignment mark is measured again and the correction coordinate system is obtained again. Good.

  After the exposure processing of the divided pattern areas B and C is completed, the developing process is performed on the resist-coated wafer 7 in the same manner as the developing method for forming the divided pattern areas A. As a result, resist patterns in the divided pattern areas B and C as shown in FIG. 7D are formed on the wafer.

  Subsequently, etching is performed using the photoresist on which the patterns of the divided pattern regions B and C are formed as a mask, so that the divided pattern regions B and C are formed as etching steps on the wafer. In addition, the area | region of the division | segmentation pattern area A formed by the etching process previously is not exposed at the time of the division | segmentation pattern area | regions B and C exposure. Therefore, it is covered with the photoresist even after the development process and is not subjected to the etching process. Thereafter, ashing is performed to remove the photoresist remaining on the wafer, and the photoresist residue is also removed using an appropriate stripping solution.

  In this way, the divided pattern region A is first exposed and etched, and then the divided pattern regions B and C are exposed and etched to obtain a desired chip pattern as shown in FIG. Is formed on the wafer 1. In FIG. 7E, ten chip patterns 11 are formed on the wafer 1 as steps.

In the case of performing the continuous exposure with the conventional technique, since there is no means for confirming the arrangement information on the wafer of the divided pattern area A that has been exposed first, the position where the divided pattern areas B and C are exposed on the wafer. The accuracy depends only on the accuracy of the stepping operation of the exposure apparatus. On the other hand, in the present embodiment, the alignment marks formed in the divided pattern area A are measured to obtain the arrangement information of the divided pattern area A, and the remaining divided pattern areas B and C are obtained based on the obtained arrangement information. The coordinate system used for exposure is corrected. Therefore, the arrangement of the divided pattern areas does not depend only on the accuracy of the stepping operation of the exposure apparatus. Then, the exposure areas of the divided pattern areas B and C that are subsequently exposed corresponding to the position of the divided pattern area A formed on the wafer are determined with higher accuracy, and the shift between the divided pattern areas can be reduced.
(Second Embodiment)
In the present embodiment, exposure processing with different exposure ranges is combined in divided exposure. A method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 8 to 10, the horizontal direction in the figure is the X direction, and the vertical direction in the figure is the Y direction. Hereinafter, the semiconductor device is referred to as an element.

  FIG. 8 is a plan view showing the appearance of the chip pattern of the element. As shown in FIG. 8A, the chip pattern 16 has a length in the X direction of 49 mm, a length in the Y direction of 23 mm, and is elongated in the X direction. This chip pattern 16 has an element portion (X direction 48 mm, Y direction 22 mm) having a pattern minimum dimension of 0.25 μm, and an alignment mark, and a scribe portion (X and Y directions) surrounding the element portion. Width 0.5 mm).

  FIG. 8B is a diagram in which the chip pattern shown in FIG. 8A is divided for divided exposure.

  As shown in FIG. 8B, the chip pattern is divided into four regions. The four regions are a divided pattern region A corresponding to the scribe portion, a divided pattern region B1, B2 corresponding to each region obtained by dividing the circuit pattern of the element portion into three equal parts along the X direction in the chip longitudinal direction, and B3. The division pattern area A is an area from each side of a rectangle having a long side of 49 mm in the X direction and a short side of 23 mm in the Y direction to the inner side of 0.5 mm, and is a frame shape having a width of 0.5 mm. It is. However, the exposure range of the divided pattern area A requires a rectangular size having a long side length of 49 mm and a short side length of 23 mm.

  Each of the divided pattern areas B1, B2, and B3 has a rectangular size having a length of 16 mm in the X direction as a short side and a length of 22 mm in the Y direction as a long side. Then, reticles RA, RB1, RB2, and RB3 corresponding to the divided pattern areas A, B1, B2, and B3 are prepared. Using the reticles RA, RB1, RB2, and RB3, the divided pattern areas A, B1, B2, and B3 are exposed to the photoresist in this order by the method described later. The arrangement of the divided pattern areas B1, B2, and B3 shown in FIG. 8B indicates the order when transferred to the photoresist. Note that information including the arrangement of the chips shown in FIG. 8 on the wafer and the arrangement of each divided pattern in the chip is the chip arrangement reference information.

  Next, an exposure apparatus for exposing each divided pattern area will be considered.

  In order to expose the divided pattern region A, an exposure range having a size equal to or larger than a rectangle having a long side of 49 mm in the X direction and a short side of 23 mm in the Y direction is necessary. Therefore, in a stepper using a KrF excimer laser as a light source (hereinafter simply referred to as “KrF excimer stepper”), the exposure range is 22 mm square, so that the divided pattern region A cannot be exposed at once. On the other hand, the divided pattern region A is only a scribe portion having an alignment mark, and generally has a pattern dimension of 1 μm or more even if the size of the alignment mark generally used is small. Therefore, in the exposure of the divided pattern region A, it is only necessary that a pattern having a minimum dimension of 1 μm can be exposed.

  A stepper with a large exposure range using i-line from an ultra-high pressure mercury lamp as a light source has a lower limit resolution than a KrF excimer stepper and a minimum pattern dimension of about 0.8 μm. Therefore, such an i-line stepper having a large exposure range can be exposed to a size of 0.8 μm which is smaller than 1 μm which is the minimum exposure size of the divided pattern region A. This i-line stepper has an exposure range of 50 mm square. Therefore, with this i-line stepper, it is possible to satisfy the requirements of the minimum pattern size and the exposure range of the divided pattern area A and to expose the divided pattern area A to the photoresist.

  Each of the divided pattern areas B1, B2, and B3 requires a rectangular exposure range of 16 mm in the X direction and 22 mm in the Y direction, and requires that the minimum pattern dimension is 0.25 μm. Therefore, the divided pattern regions B1, B2, and B3 can be exposed to the photoresist by the KrF excimer stepper having the exposure range of 22 mm square used in the first embodiment.

  Next, the reticle RA used in this embodiment will be described.

  FIG. 9 is a schematic diagram showing reticle RA. As shown in FIG. 9, at least one wafer alignment mark 10 that can be measured by the scope 118 of the i-line stepper is arranged in each of the X direction and the Y direction of the scribe portion on the reticle RA used for the first exposure process. Yes. Further, a pre-alignment mark 15 is provided on the reticle RA shown in FIG. A region surrounded by the divided pattern region A is a light shielding surface 22 so as not to be exposed.

  Next, the procedure of the pattern forming method using the above-described reticle will be described. As the stepper, an i-line stepper having a large exposure range is used in addition to the KrF excimer stepper used in the first embodiment. The i-line stepper and the KrF excimer stepper have different light sources, but the other configurations are the same. Also in the i-line stepper, the same reference numerals are used for the same components as those shown in FIG. 3, and the detailed description thereof is omitted.

  FIG. 10 is a diagram for explaining the procedure of the pattern forming method. Here, it is assumed that a pattern is formed on a wafer on which a wafer alignment mark is not formed because an initial exposure process and a subsequent etching process are not yet performed in the element manufacturing process.

  First, in the same manner as the resist coating method described in the first embodiment, an i-line photoresist is coated on a wafer. A wafer coated with a photoresist is referred to as a resist-attached wafer. On the other hand, reticle RA is set in advance on an i-line stepper, and reticles RB1, RB2, and RB3 are set in a KrF excimer stepper. Then, reticle RA is mounted on reticle stage 104, and reticle alignment is performed by performing reticle alignment.

  When the resist-attached wafer 7 is set on the i-line stepper, after mechanical pre-alignment is performed on the wafer, the resist-attached wafer 7 is moved to the wafer stage 110 via the feeding hand. Then, the resist-attached wafer 7 is moved by the distance set by the chip arrangement reference information in the X direction and the Y direction by the step-and-repeat method. For each movement, i-line illumination light is irradiated onto the reticle RA to sequentially expose the divided pattern areas A on the photoresist.

  Thereafter, development processing is performed on the resist-coated wafer 7 in the same manner as in the first embodiment. Thereby, a resist pattern of the divided pattern region A as shown in FIG. 10A is formed on the wafer.

  The wafer alignment mark 10 and the pre-alignment mark arranged on the reticle RA are also formed on the wafer as a step pattern.

  Next, a chemically amplified photoresist corresponding to KrF (hereinafter simply referred to as “KrF resist”) is formed. A wafer coated with a KrF resist is referred to as a resist-attached wafer.

  Next, in order to perform the exposure processing of the divided pattern region B1, the reticle transport system is operated to mount the reticle RB1 on the reticle stage 104, and reticle alignment is performed. Then, the pre-registration wafer 7 is mechanically pre-aligned in the apparatus, and the resist-added wafer 7 is moved to the wafer stage 110 via the feeding hand.

  Subsequently, the control unit 112 causes the scope 118 to detect the pre-alignment mark 15 so that the alignment mark 10 enters the imaging range of the scope 118. Further, the alignment marks 10 in the X direction and the Y direction are measured in the same manner as described in the first embodiment, corresponding to several shots of the divided pattern area A in the wafer. The control unit 112 obtains the arrangement information of the divided pattern area A on the wafer from the measurement result of the wafer alignment mark 10.

  Thereafter, a correction coordinate system is obtained by correcting the coordinate system of the chip arrangement reference information in consideration of the shift component, the rotation component, and the magnification component in the X and Y directions of the divided pattern area A obtained from the arrangement information. Subsequently, the resist-attached wafer 7 is moved to the exposure start position of the divided pattern region B1 with reference to the chip arrangement reference information based on the correction coordinate system. Then, illumination light is irradiated onto the reticle RB1 at the exposure start position to perform exposure processing of the divided pattern region B.

  Further, the resist-attached wafer 7 is moved from the exposure start position by a predetermined distance in the X and Y directions by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. For each movement, as shown in FIG. 10B, illumination light is irradiated onto the reticle RB1 to sequentially expose the divided pattern region B1.

  In the case of the present embodiment, in the reticle image shown in FIG. 9, the divided pattern region B1 is exposed in the region adjacent to the scribe portion on the left side inside the divided pattern region A. In FIG. 10B, the divided pattern region B1 is located on the right side inside the divided pattern region A. In this manner, as shown in FIG. 10B, the exposed area of the divided pattern area B1 is formed in the KrF photoresist on the wafer.

  Next, in order to perform exposure processing of the divided pattern region B2, the reticle RB1 is taken out, and then the reticle RB2 is mounted on the reticle stage 104 to perform reticle alignment. On the other hand, the resist-coated wafer 7 on which the divided pattern region B1 is exposed is left on the wafer stage 110 as it is.

  After the reticle alignment of the reticle RB2, the wafer with resist 7 is moved to the exposure start position of the divided pattern region B2 of the chip arrangement reference information with reference to the correction coordinate system. Then, the illumination light is irradiated onto the reticle RB2 at the exposure start position, and the divided pattern region RB2 is exposed. Further, the resist-attached wafer 7 is moved from the exposure start position by a predetermined distance in the X and Y directions by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. For each movement, as shown in FIG. 10C, illumination light is irradiated onto the reticle RB2 to sequentially expose the divided pattern region B2.

  In the case of the present embodiment, in the reticle image shown in FIG. 9, the divided pattern region B2 is exposed in the central region inside the divided pattern region A. In FIG. 10C, the divided pattern area B2 is located in the center area inside the divided pattern area A. The central area in the divided pattern area A is an area 16 mm away from the divided pattern area B1 on the left side in the drawing in the wafer external view shown in FIG. In this manner, as shown in FIG. 10C, the exposed area of the divided pattern area B2 is formed in the KrF resist on the wafer.

  Next, in order to perform the exposure processing of the divided pattern region B3, the reticle RB is taken out from the reticle stage 104, the reticle RC is mounted on the reticle stage 104, and reticle alignment is performed. On the other hand, the resist-coated wafer 7 on which the divided pattern region B2 is exposed is left on the wafer stage 110 as it is.

  After the reticle alignment of the reticle RB3 is completed, the wafer 7 with resist is moved to the exposure start position of the divided pattern region B3 with reference to the chip arrangement reference information based on the correction coordinate system. Then, the illumination light is irradiated onto the reticle RB3 at the exposure start position to perform the exposure process for the divided pattern region B3. Further, the resist-attached wafer 7 is moved from the exposure start position by a predetermined distance in the X and Y directions by the step-and-repeat method with reference to the chip arrangement reference information based on the correction coordinate system. For each movement, as shown in FIG. 10D, illumination light is irradiated onto the reticle RB3 to sequentially expose the divided pattern region B3.

  In the case of the present embodiment, in the reticle image shown in FIG. 9, the divided pattern region B3 is exposed in a region adjacent to the scribe portion on the right side inside the divided pattern region A. In FIG. 10D, the divided pattern region B3 is a region located on the left side inside the divided pattern region A. The area located on the left side in the divided pattern area A is an area 16 mm away from the divided pattern area B2 on the left side in the drawing in the wafer external view shown in FIG. In this manner, as shown in FIG. 10D, the exposed area of the divided pattern area B3 is formed in the KrF photoresist on the wafer.

  In the exposure process of the divided pattern area B2 and the divided pattern area B3, the correction coordinate system obtained before the exposure of the divided pattern area B1 is used in the above-described case. However, the wafer alignment mark is measured again, and the corrected coordinate system is used. You may ask again.

  Thereafter, the resist-coated wafer 7 for which the exposure processing of the divided pattern areas B1, B2, and B3 has been completed is developed in the following procedure. In the resist development apparatus, the PEB process immediately after exposure is performed on the KrF resist at an appropriate temperature, and then the development process is performed with a developer. Subsequently, a water washing process is performed, and a post-baking process at an appropriate temperature and / or a light irradiation process using UV light or the like is performed again, so that the divided pattern regions B1, B2, and B3 as shown in FIG. A resist pattern is formed on the wafer.

  Subsequently, etching is performed using the KrF resist on which the patterns of the divided pattern regions B1, B2, and B3 are formed as a mask, and the divided pattern regions B1, B2, and B3 are formed as etching steps on the wafer. In addition, the area | region of the division | segmentation pattern area | region A formed by the etching process previously is not exposed at the time of exposure of division | segmentation pattern area | region B1, B2, and B3. Thereafter, the KrF resist remaining on the wafer is removed by ashing, and the KrF resist residue is also removed using an appropriate stripping solution.

  In this way, the divided pattern area A is first exposed and etched, and then the divided pattern areas B1, B2 and B3 are exposed and etched, as shown in FIG. 10 (f). A chip pattern is formed on the wafer.

  As described above, in this embodiment, after the alignment mark of the divided pattern region A is formed on the wafer, the alignment mark is measured to obtain the arrangement information of the divided pattern region A. As a result, the coordinate system for the exposure processing of the divided pattern areas B1, B2, and B3 is corrected. Since the alignment of the wafer and the reticle is performed using the alignment mark directly formed on the wafer, the exposure areas of the divided pattern areas B1, B2, and B3 are more accurate with respect to the position of the alignment mark formed on the wafer. Well decided. Accordingly, it is possible to reduce the connection shift between the scribe section and the element section and the connection shift between the divided pattern areas.

  In this embodiment, since the alignment mark is provided in the scribe portion on the outer periphery of the chip pattern, the circuit pattern region can be made wider.

  Further, an i-line stepper is used for the exposure process of the divided pattern area A including the alignment mark, and a KrF excimer stepper is used for the exposure process of the divided pattern areas B1, B2, and B3. By using an i-line stepper for the exposure processing of the divided pattern region A, the apparatus load of the KrF excimer stepper is reduced.

  Further, since the photoresist for forming the divided pattern region A is different from the photoresist for forming the divided pattern regions B1, B2, and B3, the photoresist for forming the divided pattern region A has an etching resistance. Higher ones can be used. As a result, the alignment mark pattern can be further deeply cut into the substrate. When the pattern of the alignment mark is deeply carved, the possibility that it can be used as an alignment mark increases even if a plurality of insulating films such as silicon oxide films are stacked in the subsequent process.

  In the first and second embodiments, the chip pattern that exposes the exposure range in the X direction has been described. However, in addition to the chip pattern that protrudes in the Y direction as well as the chip pattern that protrudes in both the X and Y directions, it can be applied to the present invention if it is divided to a size that allows exposure. The number of division areas of the chip pattern and the division method are arbitrary.

  Further, although the case where the semiconductor device manufacturing method of the present invention is implemented using a stepper which is a step-and-repeat type exposure apparatus has been described, the exposure apparatus is not limited to a stepper. It is possible to implement the method of manufacturing a semiconductor device in the present invention using a scanner, an electron beam exposure apparatus, and other exposure apparatuses that are step-and-scan type exposure apparatuses. Further, a plurality of exposure apparatuses may be used in light of the exposure range and resolution (limit resolution, minimum pattern dimension, minimum exposure dimension, etc.) and desired semiconductor device design dimensions.

  Furthermore, what was demonstrated by the said 1st and 2nd embodiment is an example, Comprising: This invention is not limited to this.

It is a figure which shows the case where the alignment mark is arrange | positioned to the reticle RA in this invention. It is a figure which shows the pattern formation method in this invention. It is a figure for demonstrating the structure of the stepper used in 1st Embodiment. It is a top view which shows the external appearance of the chip pattern of the element in 1st Embodiment. It is the figure which divided the chip | tip shown in FIG. 4 for division | segmentation exposure. It is a schematic diagram which shows reticle RA in 1st Embodiment. It is a figure for demonstrating the procedure of the pattern formation method in 1st Embodiment. It is a top view which shows the external appearance of the chip pattern of the element in 2nd Embodiment. It is a schematic diagram which shows reticle RA in 2nd Embodiment. It is a figure for demonstrating the procedure of the pattern formation method in 2nd Embodiment. It is an external appearance schematic diagram which shows an example of the size and arrangement | positioning of the chip | tip formed in a wafer. It is a figure which shows the shape and magnitude | size of a chip pattern and an exposure range. It is a figure which shows the state which divided | segmented the chip | tip pattern shown in FIG. 12 into the size which can be exposed. It is a figure which shows the pattern formation method of the chip pattern shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 2 Element 3 Exposure range 4, 5, 6 Divided pattern area 7 Wafer with resist 10 Alignment mark 11, 16, 20 Chip pattern 15 Pre-alignment mark 22 Light-shielding surface A, B, B1, B2, B3, C Divided pattern area RA, RB, RC reticle

Claims (6)

A step of preparing a photomask set in which at least one of a plurality of photomasks corresponding to each of a plurality of divided patterns obtained by dividing the chip pattern into a plurality of alignment marks, and
Transferring a pattern including the alignment mark to a first photoresist applied on a substrate using a photomask having the alignment mark;
Forming a pattern including the alignment marks on the substrate by performing an etching process using the first photoresist as a mask;
Applying a second photoresist on a substrate on which a pattern including the alignment mark is formed;
Performing alignment between a photomask for forming a pattern on the second photoresist and the substrate using an alignment mark formed on the substrate;
A method for manufacturing a semiconductor device comprising:   The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the first photoresist after the etching process and before the step of applying the second photoresist.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the photomask having the alignment mark has a part of a circuit pattern.   The method of manufacturing a semiconductor device according to claim 1, wherein the photomask having the alignment mark has a pattern of a scribe portion. The step of transferring the pattern including the alignment mark to the first photoresist includes an alignment mark exposure process for exposing the pattern including the alignment mark to the first photoresist,
The method of manufacturing a semiconductor device according to claim 4, wherein an exposure range of the alignment mark exposure process is larger than an exposure range of a step of exposing the second photoresist to a pattern corresponding to the remaining photomask. Divided exposure using a plurality of photomasks having a photomask having at least an alignment mark among a plurality of photomasks corresponding to each of a plurality of divided patterns which are patterns obtained by dividing a chip pattern including a circuit pattern into a plurality of patterns An exposure apparatus for
A stage driving unit for enabling coordinate information indicating the coordinates of a stage on which the substrate is mounted to be sent to the outside, and for moving a predetermined position of the stage to an exposure position;
A detection unit for detecting an alignment mark provided on the substrate;
A control unit that is communicably connected to the stage drive unit and the detection unit, and in which the reference arrangement information of the alignment mark is registered in advance;
When the substrate coated with the first photoresist is introduced, the control unit exposes the pattern of the photomask having the alignment mark to the first photoresist, and then the second photoresist. When the substrate on which the alignment mark is formed is introduced, the detection unit detects the alignment mark, and the coordinate information of the detected alignment mark is received from the stage driving unit. And the reference arrangement information is obtained, the coordinate system of the reference arrangement information is corrected based on the difference, and the alignment with the substrate is performed for each remaining photomask corresponding to the reference arrangement information of the corrected coordinate system. An exposure apparatus that performs a process of exposing the second photoresist to a pattern corresponding to the photomask.

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