JP5792431B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a divided exposure method.

  2. Description of the Related Art Conventionally, in the manufacture of semiconductor devices, a desired reticle (chip) pattern is baked on a photoresist applied on a substrate using a projection exposure apparatus, and surface processing is performed. As a projection exposure apparatus, a step-and-repeat stepper and a step-and-scan scanner are often used. When a large chip is required for an image sensor or liquid crystal display device, and the chip size exceeds the exposure area size of the exposure device, the entire chip is divided into multiple areas, and each area is separately exposed and connected. An exposure method is adopted.

  In this divided exposure method, if the gap between the divided patterns is large, it becomes impossible to form a fine pattern. Therefore, it is important to reduce this, and such a high accuracy method is disclosed in Japanese Patent Application Laid-Open No. 2006-310446. It is disclosed in the publication.

  First, a prior division exposure method described in [Background Art] of JP-A-2006-310446 will be described. This relates to a method of forming a desired chip pattern by divided exposure using a stepper in the first exposure process in the manufacturing process of an element requiring a divided exposure method.

  FIG. 6 is a schematic external view showing an example of the size and arrangement of chips formed on a wafer. As shown in FIG. 6, five elements 18 (circuit patterns are not shown) are arranged on the wafer 15 in the vertical direction (Y direction) in the figure. Two rows arranged in the Y direction are provided in the horizontal direction (X direction) in the figure. A total of 10 (= 5 × 2 rows) elements 18 are arranged on the wafer 15. While the exposure range of the stepper is substantially square, the chip pattern of the element 18 is a rectangle that is long in the X direction, and the length in the X direction is assumed to be larger than one side of the exposure range of the stepper. In such a case, the chip pattern is divided into sizes that can be exposed in the X direction. In this example, the chip pattern is divided into three areas (divided pattern areas A, B, and C) having a size that can be exposed. Let the reticles corresponding to each division pattern be RA, RB, and RC. Further, chip placement reference information, which is information including the placement of the chip of the element 18 on the wafer 15 and the placement of the divided pattern areas A, B, and C in the chip, is stored in advance in the stepper.

  FIG. 7 is a diagram showing a method of forming a chip pattern of the element 18 shown in FIG. A resist-coated wafer 14 coated with a photoresist is prepared, and reticles RA, RB, and RC are set on a stepper. The stepper mounts the reticle RA on the reticle stage, and aligns the reticle RA and the reticle stage. Then, the stepper refers to the chip arrangement reference information, moves the resist-coated wafer 14 to the exposure start position, and then exposes the divided pattern region A (19) to the photoresist at the position 22a shown in FIG. To do. Subsequently, each time the resist-coated wafer 14 is moved by a predetermined distance from the upper right position 22a to the lower right position 22b in a downward (−Y direction) step-and-repeat manner with reference to the chip arrangement reference information. The reticle RA is irradiated with irradiation light to expose the divided pattern region A (19) on the photoresist. In this example, the predetermined distance moved in the −Y direction by the stepping operation is equal to the length of the element 18 in the Y direction.

  When the exposure processing is completed up to the lower right position 22b in FIG. 7A, the resist-attached wafer 14 is moved in the −X direction by a predetermined distance with reference to the chip arrangement reference information, and the photoresist at the movement destination position 22c is obtained. Then, the divided pattern area A (19) is exposed. In this example, the predetermined distance moved in the −X direction from the position 22b to the position 22c is equal to the length of the element 18 in the X direction. Subsequently, with reference to the chip arrangement reference information, every time the resist-coated wafer 14 is moved by a predetermined distance in the upward direction (Y direction) in FIG. 7A to the uppermost position 22d by the step-and-repeat method. Then, the reticle RA is irradiated with irradiation light to expose the divided pattern region A (19) on the photoresist. In this example, the predetermined distance moved in the Y direction by the stepping operation is equal to the length of the element 18 in the Y direction. In this way, as shown in FIG. 7A, two rows of regions exposed by arranging five divided pattern regions A (19) in the Y direction are formed in the photoresist.

  Subsequently, the stepper exchanges the reticle RA on the reticle stage with the reticle RB, and aligns the reticle RB with the reticle stage. Thereafter, the divided pattern region B (20) is exposed to the photoresist each time the resist-coated wafer 14 is moved by a predetermined distance in the same manner as the divided pattern region A by the step-and-repeat method. At this time, as shown in FIG. 7B, the area where the divided pattern area B (20) is exposed is positioned closer to the −X direction than the area where the divided pattern area A (19) is exposed. In this way, a divided pattern region B (20) is formed in the photoresist next to each region of the divided pattern region A (19).

  Further, the stepper exchanges the reticle RB on the reticle stage with the reticle RC, and aligns the reticle RC with the reticle stage. Thereafter, the divided pattern region C (21) is exposed to the photoresist each time the resist-coated wafer 14 is moved by a predetermined distance by the step-and-repeat method in the same manner as the divided pattern region A. At this time, as shown in FIG. 7C, the area where the divided pattern area C (21) is exposed is positioned in the adjacent area in the −X direction with respect to the area where the divided pattern area B (20) is exposed. In this way, a divided pattern region C (21) is formed in the photoresist next to each region of the divided pattern region B (20).

  The resist-coated wafer 14 in which the exposure processing of all the divided pattern regions has been completed is taken out from the stepper and developed to cause a resist pattern having a desired chip pattern to appear. Then, when etching is performed using the resist pattern as a mask, a desired chip pattern is formed as a step on the wafer. FIG. 7D shows the wafer state after the resist is removed, and ten chip patterns 23 are formed as steps on the wafer 15.

  In the above-described divided exposure method, when performing the divided exposure in the first exposure process in the element manufacturing process, the stepper determines the exposure position of the divided pattern areas A, B, and C by the stepping operation based on the chip arrangement reference information. ing. In this case, the accuracy of the position where the divided pattern areas are exposed on the wafer greatly depends on the accuracy of the stepping operation of the stepper, and there is a problem that the accuracy of adjacent connection between the divided pattern areas is low.

  Next, a divided exposure method disclosed in Japanese Patent Application Laid-Open No. 2006-310446 that improves the above problem will be described. The size and arrangement of chips formed on the wafer are the same as those shown in FIG. Similarly, the chip pattern is divided into three areas (divided pattern areas A, B, and C) that can be exposed, and the reticles corresponding to the divided patterns are RA, RB, and RC. However, at least one of the reticles RA, RB, RC is provided with an alignment mark for alignment with the other two. In the example described here, an alignment mark for aligning the reticles RB and RC with the divided pattern region A in each of the X direction and the Y direction is formed on the reticle RA.

  FIG. 8 is a diagram showing a method of forming a chip pattern. A resist-coated wafer 14 coated with a photoresist is prepared, and reticles RA, RB, and RC are set on a stepper. The stepper mounts the reticle RA on the reticle stage, and aligns the reticle RA and the reticle stage. As shown in FIG. 8A, the stepper moves the resist-coated wafer 14 by a predetermined distance in each of the X direction and the Y direction by referring to the chip arrangement reference information, as shown in FIG. 8A. Then, the reticle RA is irradiated with irradiation light to sequentially expose the divided pattern region A (19) on the photoresist.

  The resist-coated wafer 14 in which the exposure processing of the divided pattern area A (19) has been completed is taken out from the stepper and developed to cause the resist pattern of the divided pattern area A (19) to appear. Then, etching is performed using the resist pattern as a mask, and the divided pattern region A (19) is formed as a step on the wafer. At this time, the alignment mark 24 arranged on the reticle RA is also formed as a step on the wafer by the etching process.

  Next, a photoresist is applied again on the wafer from which the resist pattern has been removed by etching, and set on a stepper. The stepper mounts the reticle RB on the reticle stage, and aligns the reticle RB with the reticle stage. Thereafter, several shots of the alignment mark 24 formed together with the divided pattern area A (19) are measured, and the arrangement information indicating the coordinate position on the wafer of the divided pattern area A (19) is examined. Components such as a shift in the X and Y directions, a rotation shift, and a magnification error of the divided pattern region A (19) are obtained from the examined arrangement information. Further, the coordinate system of the original chip arrangement reference information is corrected in consideration of these components.

  Subsequently, the resist-attached wafer 14 is moved to the exposure start position of the division pattern area B (20) of the chip arrangement reference information based on the correction coordinate system, the irradiation light is irradiated to the reticle RB, and the division pattern is applied to the photoresist. Area B (20) is exposed. Further, referring to the chip arrangement reference information based on the correction coordinate system, the resist-attached wafer 14 is moved by a predetermined distance in each of the X direction and the Y direction by the step-and-repeat method. As shown in (b), the exposure processing of the divided pattern region B (20) is sequentially performed. At this time, the exposure area of each divided pattern area B (20) is an area adjacent to the −X direction of the area where the divided pattern area A (19) is formed.

  Subsequently, the reticle RB on the reticle stage is exchanged with the reticle RC, and alignment between the reticle RC and the reticle stage is performed. Then, the exposure start position of the divided pattern area C (21) of the chip arrangement reference information is obtained with reference to the correction coordinate system obtained before the exposure of the divided pattern area B (20). The wafer 14 with resist is moved to the obtained exposure start position, and the reticle RC is irradiated with irradiation light to expose the divided pattern region C (21) on the photoresist. Further, referring to the chip arrangement reference information based on the correction coordinate system, the resist-attached wafer 14 is moved by a predetermined distance in each of the X direction and the Y direction by the step-and-repeat method. As shown in (c), the exposure processing of the divided pattern region C (21) is sequentially performed. At this time, the exposure area of each divided pattern area C (21) is an area adjacent to the −X direction of the area where the divided pattern area B (20) is formed.

  The resist-coated wafer 14 in which the exposure processing of the divided pattern region C (21) has been completed is taken out from the stepper and developed to cause the resist patterns of the divided pattern regions B (20) and C (21) to appear. Then, an etching process is performed using the resist pattern as a mask, and the divided pattern regions B (20) and C (21) are formed as steps on the wafer. Since the divided pattern area A (19) is not exposed during the exposure of the divided pattern areas B (20) and C (21), it is covered with the photoresist after the development process and is subjected to the etching process. There is nothing. First, the divided pattern region A (19) is exposed and etched, and then the divided pattern regions B (20) and C (21) are exposed and etched, as shown in FIG. 8D. The chip pattern 23 can be formed on the wafer 15.

  In the above-described divided exposure method, the arrangement information on the wafer of the division pattern area A is measured, and a correction coordinate system for exposing the division pattern areas B and C on the wafer is obtained based on the arrangement information, and the correction coordinates are obtained. The stepper is stepping on the basis of the system. Since the alignment of the wafer and the reticles RB and RC is performed using the alignment marks directly formed on the wafer, the exposure areas of the divided pattern areas B and C with respect to the position of the divided pattern area A formed on the wafer. Is determined more accurately. As a result, it is possible to reduce the misalignment between the divided pattern areas as compared with the case where the reticles RA, RB, RC are continuously exposed on the wafer on which no alignment mark is formed, depending only on the stepper operation accuracy of the stepper. Can be made.

JP 2006-310446 A

  The arrangement information on the wafer of the divided pattern area A previously formed on the wafer is measured by the division exposure method disclosed in the above-mentioned JP-A-2006-310446, and based on this arrangement information. A method for obtaining a correction coordinate system for exposing the divided pattern regions B and C on the wafer and performing the stepping operation of the stepper on the basis of the correction coordinate system is an alignment method that is normally performed during pattern overlay exposure. It can be considered that the enhanced global alignment method is applied to divided exposure.

  The overlay accuracy by this method is the residual error after correcting the components such as X- and Y-direction shifts, rotational deviations, and magnification errors to be the minimum in the wafer, and the step-and-step in exposure. The value is determined by a stepping error that occurs stochastically at the time of repeat, and the value that should be estimated as the worst case or margin is about 0.1 to 0.15 μm. Accordingly, there are approximately the same amount of misalignment between the divided pattern areas in the divided exposure method disclosed in Japanese Patent Laid-Open No. 2006-310446. This value is quite large for fine patterns.

  For example, a thermal infrared image sensor, which is a kind of imaging device, receives infrared rays with a diaphragm including a thermal resistor held in a state of floating from a substrate by a beam, and changes the temperature of the diaphragm due to the received infrared rays as a resistance change. In this thermal infrared image sensor, in order to reduce the thermal conductance of the beam, the beam width and the beam wiring width are reduced as the miniaturization, and the beam wiring width reaches about 0.4 μm. Yes. In addition, the pixel size has been further miniaturized, and the drive signal wiring width of the XY readout circuit has become 0.8 μm or less. The above values are 25 to 38% for the beam wiring width and 13 to 19% for the drive signal wiring width and cannot be ignored.

  Therefore, when the chip pattern is to be enlarged by the divided exposure method disclosed in Japanese Patent Application Laid-Open No. 2006-310446, the accuracy of joining between the divided pattern areas is insufficient with respect to such a device that has been miniaturized. Thus, there are problems such as disconnection at the connecting portion, resistance change at the connecting portion even if the disconnection does not occur, and image quality discontinuity at the connecting portion in the image sensor.

  The present invention has been made in view of the above problems, and its main purpose is to divide the divided pattern with high accuracy even in a device that has been miniaturized as described above. An object of the present invention is to provide a method for manufacturing a semiconductor device using an exposure method.

  In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention includes a semiconductor device manufacturing method in which a chip pattern is formed on a substrate by dividing and exposing a chip region into a plurality of divided patterns. An overlapping area overlapping with the divided exposure area of the adjacent divided pattern is provided at the periphery of the divided exposure area of the divided pattern, and at the time of the divided exposure of the preceding divided pattern, at least an alignment mark is provided in the overlapping area of the preceding divided pattern. One is formed, and in performing the divided exposure of the subsequent divided pattern, alignment is performed based on the coordinates of the alignment mark existing in the divided exposure region of the subsequent divided pattern.

  In the present invention, it is preferable that a divided exposure region when forming the alignment mark is larger than an effective divided exposure region for forming the chip pattern.

  In the present invention, it is preferable to perform alignment using a die-by-die alignment method for the alignment marks corresponding to the divided pattern regions in the divided exposure of the divided patterns. .

  According to the method for manufacturing a semiconductor device, alignment marks for alignment when exposing a divided pattern region are formed, and an alignment mark for a pair of X direction and Y direction is formed in the vicinity of the outer periphery of the preceding divided exposure region. At least one pair or more is provided, and the subsequent divided exposure area has an overlapping area including at least one pair of alignment marks in the vicinity of the outer periphery of the preceding divided exposure area, and is positioned at the alignment mark coordinates viewed from the subsequent exposure area. By repeating the alignment, alignment marks for all the divided pattern areas of the chip pattern are provided, so that the coordinates of the subsequent divided exposure areas can be aligned with the coordinates of the preceding divided exposure areas with high accuracy. Alignment accuracy of alignment marks in other divided exposure areas with respect to the first alignment mark formed in the divided exposure area There is an effect that can be highly accurately.

  In addition, in overlay layer exposure, alignment is performed using the die-by-die alignment method for each alignment pattern exposure mark provided with high placement accuracy. There is an effect that the accuracy can be made extremely high.

In the method for manufacturing a semiconductor device of the present invention, (a) a diagram showing divisional exposure for chip patterns, (b) a schematic diagram showing alignment mark placement on a reticle, and (c) a divisional exposure region at the time of alignment mark formation. The figure which shows a range and arrangement | positioning, (d) It is a schematic diagram which shows the alignment mark formation state on a chip | tip. It is a schematic diagram for demonstrating the alignment mark formation method in the manufacturing method of the semiconductor device of this invention. It is a schematic diagram for demonstrating the alignment mark formation method in the manufacturing method of the semiconductor device of this invention. It is a schematic diagram for demonstrating the alignment mark formation method in the manufacturing method of the semiconductor device of this invention. It is a schematic diagram for demonstrating the alignment mark formation method in the manufacturing method of the semiconductor device of this invention. In the manufacturing method of the semiconductor device of this invention, (a) The schematic diagram of the reticle for device chip pattern exposure used for superposition exposure, (b)-(f) It is a figure which shows the progress of division | segmentation exposure. In the manufacturing method of the semiconductor device of this invention, (a) The schematic diagram of the reticle used for the exposure in the case of forming an alignment mark and a device chip pattern simultaneously, (b)-(g) is a figure which shows progress of division | segmentation exposure. It is a figure which shows the other division | segmentation exposure area | region arrangement example in the manufacturing method of the semiconductor device of this invention. It is an external appearance schematic diagram which shows an example of the size of chip | tip formed in the wafer of a prior art example (Unexamined-Japanese-Patent No. 2006-310446) and arrangement | positioning. It is a figure which shows the chip | tip pattern formation method described in [background art] of the prior art example (Unexamined-Japanese-Patent No. 2006-310446). It is a figure which shows the chip | tip pattern formation method disclosed by the prior art example (Unexamined-Japanese-Patent No. 2006-310446).

  Embodiments of a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings.

[Embodiment 1]
FIG. 1A is a diagram showing a chip pattern division exposure division, FIG. 1B is a schematic diagram showing alignment mark arrangement on a reticle, and FIG. 1C is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. It is a figure which shows the range and arrangement | positioning of the division | segmentation exposure area | region at the time of alignment mark formation, (d) It is a schematic diagram which shows the alignment mark formation state on a chip | tip.

  As shown in FIG. 1A, the chip pattern 1 of the semiconductor device has a size that needs to be divided and divided into four areas of divided pattern areas A to D. Further, since the division is performed equally, the divided pattern areas A to D are all the same size.

FIG. 1B shows a reticle for first forming an alignment mark for aligning the overlay when each layer constituting the chip pattern is exposed. The photoresist used is assumed to be positive. The reticle _R M -A division pattern area A (2) for the reticle _R M -B & C is for division pattern regions B (3) and C (4). Further, the divided exposure regions of the prior is in the exposure area by the reticle R _M -A. Therefore, the reticle R _M -A is divided into the division pattern region A alignment mark 6 and the division pattern region B alignment mark 7 and the division pattern region for alignment of the reticle R _M -B & C used in the subsequent division exposure region. C alignment mark 8 is provided. On the other hand, the reticle R _M -B & C has the remaining divided pattern region D alignment marks 9. Each of the alignment marks 7, 8, 9 consists of a pair for the X direction and the Y direction. Since both reticles are used for forming an alignment mark as described above, a portion other than the alignment mark is a light shielding region 10. The pattern of the alignment mark may be either a concave shape that opens the alignment mark portion or a convex shape that opens a pattern prohibited area around the alignment mark.

The exposure range and positional relationship with these reticles are as shown in FIG. An alignment mark for divided pattern region B is provided between divided exposure region 12 by reticle R _M- A and divided exposure region (corresponding to B region) 13a and same (corresponding to C region) 13b by reticle R _M -B & C. 7 and an overlapping region including the alignment mark 8 for the divided pattern region C exists. If crowded built on a wafer in the prior alignment marks on the reticle R _M -A, when the alignment of the reticle R _M -B & C, the alignment marks in the lower right corner coordinates of the divided exposure regions due to reticle R _M -B & C It can be recognized and positioned. Since high-precision alignment at the same level as in the die-by-die alignment method can be performed, the arrangement accuracy of the alignment marks 9 for the divided pattern region D can be made extremely high. The alignment mark formation state on the chip shown in FIG.

  FIG. 2 is a schematic diagram for explaining an alignment mark forming method in the method for manufacturing a semiconductor device of the present invention.

With preparing a resist coated wafer 14 coated with a photoresist, to set the reticle _R M -A and _R M -B & C stepper. Stepper, a reticle is mounted R _M -A the reticle stage performs alignment of the reticle R _M -A and the reticle stage. As shown in FIG. 2A, the stepper moves the resist-coated wafer 14 by a predetermined distance in each of the X direction and the Y direction by referring to the chip arrangement reference information, as shown in FIG. Then, the reticle R _M -A is irradiated with irradiation light to sequentially expose the divided exposure regions 12 with R _M -A on the photoresist. The resist-coated wafer 14 in which the exposure processing of the divided exposure region 12 has been completed is taken out of the stepper and developed to cause a resist pattern in the divided exposure region 12 to appear. However, as described above, since the reticle has a light shielding region other than the alignment mark, the resist pattern that appears is only the alignment mark. Etching is performed using the resist pattern as a mask, and alignment marks 6, 7, and 8 in the divided exposure region 12 are formed as steps on the wafer.

Next, a photoresist is applied again on the wafer from which the resist pattern has been removed by etching, and set on a stepper. Stepper, a reticle is mounted _R M -B & C reticle stage performs alignment of the reticle _R M -B & C and the reticle stage. Then, the reticle R _M -B & C by the divided exposure regions (B regions corresponding) 13a enhanced global alignment method with reference to the chip placement reference information to divide the coordinates of the lower right corner pattern region B for the alignment mark 7 is present The wafer 14 with resist is aligned with each other, and further, with reference to the chip arrangement reference information based on the correction coordinate system, as shown in FIG. 2 (b), the step and repeat method is used for each of the X direction and the Y direction. The resist-coated wafer 14 is moved by a predetermined distance, and each time the movement is performed, the division pattern area B alignment mark 7 detection → alignment → divided exposure area (corresponding to the B area) 13a is sequentially performed. (The method from wafer alignment to exposure by the enhanced global alignment method can be regarded as “exposure processing by the die-by-die alignment method using the alignment marks 7 for the divided pattern region B”.)

Subsequently, the reticle R _M -B & C by dividing the exposure region (C region corresponding) 13b enhanced global alignment by referring to the chip placement reference information to divide the coordinates of the lower right corner pattern region C for the alignment mark 8 is present The wafer 14 with resist is aligned by the method, and further, with reference to the chip arrangement reference information based on the correction coordinate system, as shown in FIG. 2C, the X and Y directions are respectively performed by the step-and-repeat method. The resist-coated wafer 14 is moved at a predetermined distance to each other, and the division pattern area C alignment mark 8 detection → positioning → division exposure area (corresponding to the C area) 13b is sequentially performed for each movement. (The method from wafer alignment to exposure by the enhanced global alignment method can be regarded as “exposure processing by the die-by-die alignment method using the alignment mark 8 for the divided pattern region C”.)

  The resist-coated wafer 14 for which the exposure process has been completed is taken out from the stepper and developed to cause the resist patterns in the divided exposure regions 13a and 13b to appear. However, the resist pattern that also appears here is only the alignment mark. Etching is performed using the resist pattern as a mask to form the alignment marks 9 in the divided exposure regions 13a and 13b as steps on the wafer. As a result, as shown in FIG. 2D, all the divided pattern region alignment marks can be formed on the wafer 15 with extremely high placement accuracy.

3A and 3B are diagrams showing (a) a schematic diagram of a reticle for device chip pattern exposure used for overlay exposure and (b) to (f) showing the progress of divided exposure in the method for manufacturing a semiconductor device of the present invention. The reticle _{R D -A~R} D -D shown in FIG. 3 (a), respectively, it is for the divided pattern regions A~D exposure. As shown in this figure, in the light shielding area 16, in addition to the area for protecting the alignment mark, there is an area where each divided exposure area extends from the corresponding divided pattern area to another divided pattern area. It also includes that.

A wafer with a resist is prepared by applying a photoresist to a wafer in which an alignment mark is built by the manufacturing method of the present invention, and reticles R _D -A to R _D -D are set on a stepper. When alignment / exposure processing is performed by the die-by-die alignment method using the alignment mark 6 for the division pattern area A using the reticle R _D -A, the division pattern area is obtained as shown in FIG. A is exposed. Next, when the reticle is replaced with _RD- B and alignment / exposure processing is performed by a die-by-die alignment method using the alignment marks 7 for the divided pattern region B, as shown in FIG. Then, the divided pattern region B is exposed. Subsequently, when the reticle is replaced with _RD- C and alignment / exposure processing is performed by a die-by-die alignment method using the alignment marks 8 for the divided pattern region C, as shown in FIG. The divided pattern area C is exposed. Further, when the reticle is exchanged to R _D -D and alignment and exposure processing is performed by a die-by-die alignment method using the alignment marks 9 for the divided pattern region D, as shown in FIG. The divided pattern area D is exposed. At this time, the alignment mark 9 used for alignment may be formed in the divided exposure area B or in the divided exposure area C. The accuracy may be further increased by using both alignment marks 9. Further, there is a limit to the alignment mark detection optical system of the stepper to be used. For example, if the alignment mark for X is below the center of the exposure area and the alignment mark for Y is limited to the right from the center of the exposure area, the divided exposure area The X alignment mark may be used from the one formed in B, and the Y alignment mark may be used from the one formed in the divided exposure region C. Alternatively, if only one alignment mark is sufficient, the exposure processing of one of the divided exposure region B and the divided exposure region C may be omitted in the above-described alignment mark formation.

  When the resist-coated wafer having been subjected to the above exposure processing is taken out of the stepper and developed, a chip pattern as shown in FIG. 3F is formed. Since the alignment marks arranged with high accuracy are detected and aligned for each divided pattern region, the connecting accuracy between the divided pattern regions can be extremely high. If the alignment marks for each divided pattern region are formed in the divided pattern regions B to D at an early stage (for example, the step of forming the first alignment mark), the device chip pattern exposure used for the overlay exposure is used. It is also possible to match the exposure area of the reticle for use with each divided pattern area.

[Embodiment 2]
FIG. 4A is a schematic diagram of a reticle used for exposure when forming an alignment mark and a device chip pattern at the same time, and FIG. 4B to FIG. 4G show the progress of divided exposure. FIG. The reticle _R MD _-A~R MD -D shown in 4 (a) is, respectively, is used for dividing the exposure region A~D exposure. As shown in this figure, the light shielding region 17 is a region where each divided exposure region extends from the corresponding divided pattern region to another divided pattern region and a protective region for the alignment mark formed in the preceding process.

First, while preparing a resist coated wafer coated with a photoresist, to set the reticle _R MD _-A~R MD -D stepper. When the reticle R _MD- A is used and exposure processing similar to that of the divided exposure area 12 in FIG. 2 is performed, the divided exposure area A (the divided pattern area A and the alignment marks 6, 7,. 8) is exposed. The resist-coated wafer that has been subjected to the exposure process is taken out of the stepper and developed to cause a resist pattern in the divided exposure area A (the divided pattern area A and the alignment marks 6, 7, and 8) to appear. Etching is performed using the resist pattern as a mask, and the divided pattern region A and the alignment marks 6, 7, and 8 are formed as steps on the wafer.

Next, a photoresist is applied again on the wafer from which the resist pattern has been removed by etching, and set on a stepper. The reticle was replaced with R _{MD -B,} when performing the same exposure and the divided exposure regions 13a in FIG. 2, the divided exposure regions B (divided pattern regions B and the alignment mark 9) as shown in FIG. 4 (c) Exposed. Subsequently, when the reticle is replaced with _RMD- C and exposure processing similar to that of the divided exposure region 13b in FIG. 2 is performed, the divided exposure region C (the divided pattern region C and the alignment mark as shown in FIG. 4D) is obtained. 9) is exposed. The resist-coated wafer on which the exposure processing has been completed is taken out from the stepper and developed, and as shown in FIG. 4E, the divided exposure region B (the divided pattern region B and the alignment mark 9) and the divided exposure region C (the divided pattern region). C and alignment patterns 9) appear. Etching is performed using the resist pattern as a mask, and the divided pattern region B, the divided pattern region C, and the two alignment marks 9 are formed as steps on the wafer.

Photoresist is applied again on the wafer from which the resist pattern has been removed by etching, and set on a stepper. The reticle was replaced with R _{MD -D,} performed alignment, exposure processing by the die-by-die alignment method using the division pattern regions D for the alignment mark 9, divided as shown in FIG. 4 (f) Pattern Region D is exposed.

At this time, the alignment mark 9 used for alignment may be formed in the divided exposure area B or in the divided exposure area C. The accuracy may be further increased by using both alignment marks 9. Further, there is a limit to the alignment mark detection optical system of the stepper to be used. For example, if the alignment mark for X is below the center of the exposure area and the alignment mark for Y is limited to the right from the center of the exposure area, the divided exposure area The X alignment mark may be used from the one formed in B, and the Y alignment mark may be used from the one formed in the divided exposure region C. Alternatively, if suffices one alignment mark, a reticle is prepared for one of R _{MD -B} or R _{MD -C} may be those alignment marks 9 no.

  The resist-coated wafer for which the exposure process has been completed is taken out of the stepper and developed to cause a resist pattern in the divided pattern region D to appear as shown in FIG. Etching is performed using the resist pattern as a mask, and the divided pattern region D is formed as a step on the wafer. When the resist pattern is removed, a chip pattern as shown in FIG. 4G is obtained. It is possible to simultaneously form a first layer chip pattern having a highly accurate alignment mark and a highly accurate joining accuracy.

  As described above, in the method of manufacturing a semiconductor device according to the embodiment of the present invention, the alignment mark that is aligned when the divided pattern region is exposed is formed in the X direction near the outer periphery of the preceding divided exposure region. At least one pair of alignment marks for the Y direction is provided, and the subsequent divided exposure region has an overlapping region including at least one pair of alignment marks in the vicinity of the outer periphery of the preceding divided exposure region. By repeating the alignment with the alignment mark coordinates viewed from the exposure area, alignment marks for all the divided patterns of the chip pattern are provided, so that the coordinates of the subsequent divided exposure areas are set to those of the preceding divided exposure areas. It can be aligned with the coordinates with high accuracy, and the other divisional exposure areas of the divisional exposure area alignment mark that was initially formed It is possible to extremely high precision placement accuracy of line placement mark.

  In addition, in the exposure of the overlay layer, the alignment of each of the divided pattern areas provided above is aligned using the die-by-die alignment method, thereby joining the overlay layers. The accuracy can be extremely high.

  It should be noted that between the chips and between the divided pattern regions, a resist residue due to underexposure does not occur in a portion where the resist is to be removed by development processing. In general, a double exposure region (overlapping region) called a repeat margin having a width of several μm to several μm is provided. Accordingly, the exposure area of the reticle and the like is formed by expanding the part corresponding to the repeat margin from the dimension obtained by multiplying the actual chip size or divided pattern region size by the inverse multiple of the reduction ratio of the projection exposure apparatus. In the above description and drawings, the description of the repeat margin is omitted.

  As mentioned above, although each embodiment of this invention was described, this invention is not limited to description of each said embodiment, Unless it deviates from the meaning of this invention, it can change suitably.

  For example, in the above-described embodiment, the arrangement of the divided pattern areas to the exposure areas is an example of 2 rows × 2 columns. However, the arrangement is not limited to this, and other arrangements are possible. FIG. 5 is a view showing another example of the divided exposure region arrangement in the method for manufacturing a semiconductor device of the present invention. (A) 2 rows × 3 columns, (b) 3 rows × 2 columns, (c) 3 rows × 3 columns. Furthermore, it can be applied to higher order arrangements.

  In the above embodiment, the example in which the manufacturing method of the present invention is applied to the entire chip pattern region has been described. However, the manufacturing method of the present invention is limited to a region where high-precision joining is required in the chip pattern region. By applying the method, it is also possible to connect regions with sufficient accuracy with a low accuracy by step-and-repeat exposure using the enhanced global alignment method.

  In the above-described embodiment, the case where the semiconductor device manufacturing method of the present invention is implemented using a stepper that is a step-and-repeat type exposure apparatus has been described as an example. However, a step-and-scan type scanner or The present invention can also be applied using other exposure apparatuses such as an electron beam exposure apparatus.

  The manufacturing method of the present invention was applied to the manufacture of a thermal infrared image sensor having 1000 × 1000 effective pixels and a pixel pitch of 23.5 μm. The chip size is 26 mm (X) x 30 mm (Y), and the chip pattern area is divided into four divided pattern areas of 13 mm (X) x 15 mm (Y) so that exposure can be performed with an exposure area of 17.5 mm □ of the stepper used. Divided into Since the dimension in the longitudinal direction of the LSA mark used as the alignment mark is a little over 220 μm including the pattern prohibited area, the overlapping area width is set to 250 μm. As a result, the divided exposure area of the reticle was 13.25 mm (X) × 15.25 mm (Y). Both the divided exposure area and the divided pattern area were provided with a repeat margin of 0.5 μm width. As far as the appearance inspection in the production process is concerned, it seems that 0.01 μm or less is obtained as the joining accuracy. The connecting portion of this device includes a beam wiring with a width of less than 0.4 μm and a drive signal wiring with a width of less than 0.8 μm, but a good imaging function without image quality discontinuity can be obtained. The effectiveness of the semiconductor device manufacturing method was confirmed.

  The present invention can be used in a method for manufacturing a semiconductor device, in particular, a method for manufacturing an imaging element, a liquid crystal display element, or the like.

1 Chip pattern area 2 Divided pattern area A
3 Divided pattern area B
4 Division pattern area C
5 Divided pattern area D
6 divided pattern regions A for the alignment mark 7 division pattern regions B for the alignment mark 8 division pattern area C for the alignment mark 9 divided pattern regions D for the alignment mark 10 light shielding region 11 shielding frame 12 R _M -A-division exposure regions 13a R _M -Divided exposure area by B & C (B area correspondence)
13b R _M -B & C by dividing the exposure region (C region corresponding)
14 Wafer with resist 15 Wafer 16, 17 Light shielding area 18 Element 19 Divided pattern area A
20 Division pattern area B
21 Division pattern area C
22a, 22b, 22c, 22d Position 23 Chip pattern

Claims (3)

In a method for manufacturing a semiconductor device in which a chip pattern is formed on a substrate by dividing exposure with a divided pattern obtained by dividing a chip region into a plurality of patterns,
In the periphery of the divided exposure area of each divided pattern, an overlapping area overlapping with the divided exposure area of the adjacent divided pattern is provided,
At the time of divided exposure of the preceding divided pattern, at least one alignment mark is formed in the overlapping region of the preceding divided pattern,
In the divided exposure of the divided pattern of the trailing, cormorants line alignment based on the coordinates of the alignment marks present in the divided exposure regions of the divided pattern of the trailing, a manufacturing method of a semi-conductor device,
A resist is applied on the substrate, and a first reticle for exposing a chip pattern to the divided exposure area of the preceding divided pattern is aligned with the overlapping area of the preceding divided pattern using an alignment mark reticle. A first alignment mark for alignment and a second alignment mark for aligning a second reticle for exposing a chip pattern to a divided exposure region of the subsequent divided pattern, and developing and etching the substrate. Forming the first alignment mark and the second alignment mark thereon;
Resist is applied again on the substrate from which the resist has been removed, and the first reticle is aligned based on the coordinates of the first alignment mark existing in the divided exposure region of the first reticle, and the preceding division is performed. Exposing a chip pattern to a divided exposure area of the pattern;
Aligning the second reticle based on the coordinates of the second alignment mark present in the divided exposure area of the second reticle, and exposing a chip pattern to the divided exposure area of the subsequent divided pattern;
Forming the chip pattern in a divided exposure region of the preceding divided pattern and the succeeding divided pattern on the substrate by development and etching, and a method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a divided exposure region in forming the alignment mark is larger than an effective divided exposure region in which the chip pattern is formed. 3. The alignment is performed by using a die-by-die alignment method with respect to the alignment marks corresponding to the respective divided pattern areas at the time of divided exposure of each divided pattern. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

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