JP2020112585A - Method for manufacturing semiconductor device and inspection method - Google Patents

Abstract

To improve the accuracy of inspection and to improve the performance of a semiconductor device.SOLUTION: In an inspection for a positional deviation of a resist pattern RP1 by use of an inspection mark MK, deformation in an upper part of resist patterns RP1 to RP3 in the process of forming the resist patterns RP1 to RP3 by patterning a resist film RF may be erroneously determined as a positional deviation. In order to inspect the deformation, the resist patterns RP1 to RP3 are each individually contracted by subjecting the patterns to a heat treatment. After the heat treatment, a distance L5 between an end E1a of the resist pattern RP1 and an end E2a of the resist pattern RP2, and a distance L6 between an end E1c of the resist pattern RP1 and an end E3a of the resist pattern RP3 are measured. Thus, it can be determined that changes in the resist patterns RP1 to RP3 are caused by the contraction.SELECTED DRAWING: Figure 9

Description

The present invention relates to a method for manufacturing a semiconductor device and an inspection method, for example, a technology effective when an inspection mark is used when forming a resist pattern.

A resist pattern is used when various ion implantations or etching processes are performed during the manufacturing process of a semiconductor device. For example, when an impurity region is formed by ion implantation, it is required that a resist pattern serving as a mask be accurately arranged so that the impurity region is formed at a desired position. Therefore, an inspection is performed to confirm the positional deviation of the resist pattern.

For example, Patent Document 1 discloses a technique of measuring the amount of positional deviation between a resist mark and a base mark by a measuring machine in order to confirm the absolute positional relationship between the resist pattern and the wafer.

JP, 2002-252168, A

If the position of the resist pattern shifts, for example, the position of the impurity region formed by ion implantation shifts, or the position of the film to be processed that is the target of etching shifts, so it is necessary to accurately form the resist pattern. To be At this time, in order to determine whether or not the resist pattern is formed at a desired position, an inspection mark is formed in advance on the semiconductor substrate, and the position of this inspection mark is compared with the position of the resist pattern. There is technology. It is required to suppress the positional deviation of the resist pattern and improve the performance of the semiconductor device by increasing the accuracy of the inspection including such collation.

Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

According to one embodiment, a semiconductor device manufacturing method and an inspection method are (a) a step of forming an inspection mark on a semiconductor substrate, and (b) a resist film formed on the semiconductor substrate and the inspection mark. And (c) patterning the resist film to form a first resist pattern located on the inspection mark and second and third resist patterns adjacent to both sides of the first resist pattern. Have. The semiconductor device manufacturing method and inspection method are (d) a first end portion on the upper surface of the first resist pattern on the second resist pattern side and a second end portion on the upper surface of the inspection mark on the second resist pattern side. Between the third end of the upper surface of the first resist pattern on the third resist pattern side and the fourth end of the upper surface of the inspection mark on the third resist pattern side. Measuring the second distance. Further, the step (d) has a step of calculating half of the difference value between the first distance and the second distance. The semiconductor device manufacturing method and the inspection method are (e) a step of subjecting the first, second and third resist patterns to a first heat treatment, and (f) a first end portion and a fifth end portion. Measuring a fifth distance between them, measuring a sixth distance between the third end and the sixth end, and calculating a difference value between the fifth distance and the sixth distance.

According to one embodiment, the performance of the semiconductor device can be improved. In addition, the accuracy of inspection can be improved.

6 is a flow showing a manufacturing process of the semiconductor device of the first embodiment. FIG. 4 is a main-portion plan view of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment. It is sectional drawing which shows the manufacturing process following FIG. It is sectional drawing which shows the manufacturing process following FIG. It is sectional drawing which shows the manufacturing process following FIG. It is a graph which shows the experimental data by this inventor. It is sectional drawing which shows the manufacturing process following FIG. It is sectional drawing which shows the manufacturing process following FIG. It is a table which shows the measurement data by this inventor. 11 is a table showing a calibration curve obtained from the measurement data of FIG. 10. FIG. 9 is a plan view of a main portion of the semiconductor device of Second Embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device of the second embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the semiconductor device of the third embodiment. It is sectional drawing which shows the manufacturing process following FIG.

In the following embodiments, when there is a need for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. There is a relation of some or all of modifications, details, supplementary explanations, and the like. In addition, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.) of the elements, when explicitly stated, and in principle, the number is clearly limited to a specific number, etc. However, the number is not limited to the specific number, and may be equal to or more than the specific number. Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified or in principle considered to be essential. Needless to say. Similarly, in the following embodiments, when referring to shapes, positional relationships, etc. of constituent elements, etc., the shapes thereof are substantially the same unless explicitly stated otherwise or in principle not apparently. And the like, etc. are included. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view or hatched in a plan view in order to make the drawings easy to see.

(Embodiment 1)
The manufacturing method and the inspection method of the semiconductor device according to the present embodiment will be described below with reference to FIGS. FIG. 1 is a flowchart showing each manufacturing process (steps S1 to S16) of the present embodiment. 2 is a plan view of relevant parts of the semiconductor device of the present embodiment, and FIGS. 3 to 6, 8 and 9 are cross-sectional views taken along the line AA shown in FIG.

Further, in the present embodiment, steps S1 to S13 shown in FIG. 1 will be described as a part of a plurality of steps included in the method for manufacturing a semiconductor device, but steps S1 to S13 use the inspection mark MK. It is also an inspection method for inspecting the positional deviation of the resist patterns RP1 to RP3.

In FIG. 2, a plan view is shown at the time when the manufacturing process of FIG. 6 is completed, for the sake of convenience, so that the arrangement of each configuration can be easily understood. The region shown in FIG. 2 is an enlarged view of a part of the scribe region of the semiconductor substrate (wafer) SUB. The area that surrounds the area. In the scribe region, an inspection mark (mark, reference mark) MK used to measure the positional deviation of the resist pattern is formed.

FIG. 3 shows a process of forming the inspection mark MK and the resist film RF, which corresponds to step S1 and step S2 of FIG.

First, a groove is formed in the semiconductor substrate SUB by the photolithography technique and the dry etching process. Next, an insulating film such as a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the groove by, for example, a CVD (Chemical Vapor Deposition) method. Next, the insulating film formed on the semiconductor substrate SUB outside the groove is removed by polishing the insulating film by a CMP (Chemical Mechanical Polishing) method, and the insulating film is embedded in the groove. .. As a result, the element isolation portion STI is formed on the semiconductor substrate SUB, and the element isolation portion STI constitutes the inspection mark MK in the scribe region. Further, in FIG. 3, both end portions of the upper surface of the inspection mark MK are shown as an end portion Ema and an end portion Emb. Although not shown here, the element isolation part STI is also formed in the element formation region by the same step as the step of forming the inspection mark MK.

Note that, as shown in FIG. 2, the shape of the inspection mark MK in plan view (the shape of the element isolation portion STI) is actually an annular shape, but what is generally recognized as a mark is the annular shape. The inner area is also included. Therefore, in the cross-sectional views of this embodiment such as FIG. 3, a region obtained by combining the element isolation portion STI and the semiconductor substrate SUB (region of the broken line) surrounded by these is treated as the inspection mark MK.

Next, a resist film RF is formed on the semiconductor substrate SUB and the inspection mark MK by, for example, a coating method. The resist film RF used in this embodiment is a positive resist film.

The process of patterning the resist film RF by steps S3 to S5 of FIG. 1 will be described below. FIG. 4 shows the exposure process for the resist film RF and corresponds to step S3 of FIG.

A part of the resist film RF is selectively exposed. As a result, the exposed resist film RF becomes the resist pattern RP4, and the unexposed resist film RF becomes the resist patterns RP1 to RP3. The resist pattern RP4 is a pattern that is dissolved and removed after the subsequent development processing, and the resist patterns RP1 to RP3 are patterns that remain after the subsequent development processing. The resist pattern RP4 and the resist patterns RP1 to RP3 have different chemical compositions due to a crosslinking reaction, an acid generation reaction, and the like.

Further, as shown in FIG. 2, the resist pattern RP2 and the resist pattern RP3 are part of the resist film RF and are integrated, but in the present embodiment, they are adjacent to the resist pattern RP1 in the X direction. The resist pattern RP2 and the resist pattern RP3 will be described separately. Although not shown, the resist pattern RP2 is formed over the scribe region and the element formation region.

FIG. 5 shows heat treatment for the resist patterns RP1 to RP4, which corresponds to step S4 of FIG.

The resist patterns RP1 to RP4 are subjected to heat treatment called PEB (Post Exposure Bake), for example. The heat treatment is performed, for example, at 80 to 180°C. Here, since the shrinkage rate of the exposed resist pattern RP4 is different from the shrinkage rate of each of the resist patterns RP1 to RP3, when the heat treatment is performed, the shrinkage rate of the resist pattern RP4 becomes different due to the difference in these shrinkage rates. There is a difference between the height and the height of each of the resist patterns RP1 to RP3. Generally, the shrinkage rate of each of the unexposed resist patterns RP1 to RP3 is higher than that of the exposed resist pattern RP4. Therefore, the height of each of the resist patterns RP1 to RP3 is lower than the height of the resist pattern RP4. In other words, the thickness of each of the resist patterns RP1 to RP3 is smaller than the thickness of the resist pattern RP4.

Further, such contraction occurs not only in the height direction (Z direction) but also in the lateral direction (X direction, Y direction). In particular, as shown in FIG. 5, when the shapes of the resist pattern RP2 and the resist pattern RP3 existing around the resist pattern RP1 are asymmetric, tensile stress is generated in one direction in the X direction. Such tensile stress is related to the length and volume of each of the resist pattern RP2 and the resist pattern RP3 in the X direction. Further, although such a tensile stress also occurs in the Y direction, in the present embodiment, the tensile stress in the X direction will be described as a typical example.

In the present embodiment, in the X direction, the length of resist pattern RP2 is longer than the length of resist pattern RP1 and the length of resist pattern RP3, and the volume of resist pattern RP2 is the volume of resist pattern RP1 and resist pattern RP3. Larger than the volume of. Therefore, the amount of shrinkage of the entire resist pattern RP2 becomes larger than the amount of shrinkage of the entire resist pattern RP1 and the entire resist pattern RP3, and tensile stress occurs in the direction from the resist pattern RP3 to the resist pattern RP2 in the entire resist film PR. To do. Therefore, as shown in FIG. 5, the resist patterns RP1 to RP4 are shaped so as to be pulled to the left side of the paper surface.

In other words, the positions of the end portions E1a and E1c on the upper surface of the resist pattern RP1 are displaced from the positions of the end portions E1b and E1d on the lower surface of the resist pattern RP1 in the Z direction. Further, the position of the upper end E2a of the resist pattern RP2 is displaced from the position of the lower end E2b of the resist pattern RP2, and the position of the upper end E3a of the resist pattern RP3 is lower than that of the resist pattern RP3. It is displaced from the position of the end portion E3b.

FIG. 6 shows the developing process for the resist patterns RP1 to RP4, which corresponds to step S5 of FIG.

By performing development processing on the resist patterns RP1 to RP4, the resist pattern RP4 is removed and the resist patterns RP1 to RP3 are left. In the cross-sectional view, each of the resist patterns RP1 to RP3 is separated, the resist pattern RP1 is located on the inspection mark MK, and the resist pattern RP2 and the resist pattern RP3 are adjacent to both sides of the resist pattern RP1. ..

Further, as described above, the plan view after the processing of this phenomenon substantially corresponds to FIG. Below, an example of the dimension in the X direction of each configuration shown in FIGS. 2 and 6 will be described. The length of the inspection mark MK is, for example, 5 to 10 μm, and the length of the resist pattern RP1 is, for example, 12 to 20 μm. The distance between the resist pattern RP1 and the resist pattern RP2 and the distance between the resist pattern RP1 and the resist pattern RP3 are, for example, 3 to 10 μm, respectively.

Further, each dimension in the Y direction is the same as the dimension in the X direction. That is, in the Y direction, the length of the inspection mark MK is, for example, 5 to 10 μm, and the length of the resist pattern RP1 is, for example, 12 to 20 μm. In the Y direction, the distance between the resist pattern RP1 and the resist patterns (resist film RF) adjacent to both sides of the resist pattern RP1 is, for example, 3 to 10 μm. In other words, the distance to the resist pattern (resist film RF) surrounding the resist pattern RP1 is the same in the X direction and the Y direction.

Next, the first measurement shown in step S6 of FIG. 1 is performed. In this first measurement, an inspection is performed using the inspection mark MK to determine whether the positions of the resist patterns RP1 to RP3 are misaligned. First, the distance L1 and the distance L2 shown in FIG. 6 are measured, and the difference value between the distance L1 and the distance L2 is obtained. Specifically, the distance L1 is a distance from the end Ema of the inspection mark MK to the end E1a of the resist pattern RP1, and the distance L2 is from the end Emb of the inspection mark MK to the end of the resist pattern RP1. It is the distance to E1c.

After that, normally, the process proceeds to step S15, and it is determined whether or not half of the difference value between the distance L1 and the distance L2 (the value of (L1-L2)/2) is within the allowable range. .. That is, even if the positions of the resist patterns RP1 to RP3 are misaligned, it is determined whether or not the value of the misalignment is within the allowable range.

Here, although the upper portions of the resist patterns RP1 to RP3 are deformed by the heat treatment in step S4, since the resist patterns RP1 to RP3 are in close contact with the semiconductor substrate SUB, the lower portions of the resist patterns RP1 to RP3 are hardly deformed. That is, the positions of the end portions E1b and E1d of the resist pattern RP1, the end portion E2b of the resist pattern RP2, and the end portion E3b of the resist pattern RP3 are almost the same before and after the heat treatment in step S4. Therefore, in the present embodiment, the positions of the resist patterns RP1 to RP3 are almost the same as the design values and do not deviate. Alternatively, the positional deviation of the resist patterns RP1 to RP3 is within the allowable range.

However, since the upper portion of the resist pattern RP1 is deformed as described above, it may be determined (NO) that the positions of the resist patterns RP1 to RP3 are unacceptably displaced. Hereinafter, the amount of positional deviation due to the deformation of the upper portion of the resist pattern RP1 may be referred to as a “deceived amount”.

Further, according to the study by the inventor of the present application, when the resist film RF has a thickness of 4 μm or more, since the volume of the resist film RF is large, the value of the tensile stress is large, so that an erroneous determination easily occurs. I found out. For example, when the thickness of the resist patterns RP1 to RP3 (resist film RF) is 5 μm, the amount of deception in the X direction is 100 nm or more. Usually, when the minimum processing dimension in the manufacturing process of a semiconductor device is 40 to 350 nm, the allowable range of positional deviation of the resist patterns RP1 to RP3 is set to 10 nm or more and less than 100 nm, and thus the deception amount of 100 nm or more is , Not an acceptable value.

For this reason, the positions of the resist patterns RP1 to RP3 are not actually displaced, or the positions of the resist patterns RP1 to RP3 are displaced even though the actual displacement value is within the allowable range. If the value of the positional deviation is out of the allowable range, there is a problem that a misjudgment is made. Then, there is a problem that it is difficult to distinguish between the erroneous determination due to the amount of deception and the normal determination of the positional deviation.

Further, it was found that the amount of deception caused by the tensile stress was affected by a position apart from the inspection mark MK to some extent. FIG. 7 is a graph showing data that the inventor of the present application conducted an experiment. The horizontal axis of FIG. 7 represents the distance from the inspection mark MK to the surrounding resist patterns (resist patterns RP2, RP3, etc.), and the vertical axis of FIG. 7 represents the measured value of the positional deviation of the resist pattern. Further, the mark ● in the graph is measured in the X direction, and the mark ▲ in the graph is measured in the Y direction.

As shown in the graph, when the distance on the horizontal axis is changed from −60 μm to 180 μm, the value of the positional deviation is changed from −100 nm to −50 nm. As a result, it was found that even a resist pattern separated from the inspection mark MK by about 200 μm affected the positional deviation. Generally, since the width of the scribe region is about 100 μm, the shape of the resist pattern formed in the element formation region affects the positional deviation. For example, in the present embodiment, the resist pattern RP2 formed over the scribe region and the element formation region has a great influence on the positional deviation.

From the consideration by the inventor of the present application as described above, in the present embodiment, after the first measurement for the first time, the process does not shift from step S6 to step S15, but step S6 To step S7 and subsequent steps.

Below, a method of determining whether or not the positional deviation of the resist patterns RP1 to RP3 is caused by the deceived amount and a method of feeding back the value of the deceived amount as a correction value to the first measurement in step S6. The method will be described.

First, the second measurement shown in step S7 of FIG. 1 is performed. As will be described later, the second measurement in step S7 does not necessarily have to be performed.

In the second measurement, the distance L3 and the distance L4 shown in FIG. 8 are measured. The state shown in FIG. 7 is the same as the state shown in FIG. 6 except that the distance L3 and the distance L4 are shown. The distance L3 corresponds to the distance between the resist pattern RP1 and the resist pattern RP2, and the distance L4 corresponds to the distance between the resist pattern RP1 and the resist pattern RP3. That is, the distance L3 is the distance from the end E1a of the resist pattern RP1 to the end E2a of the resist pattern RP2, and the distance L4 is the distance from the end E1c of the resist pattern RP1 to the end E3a of the resist pattern RP3. is there.

Here, since the resist patterns RP1 to RP4 were connected during the heat treatment in step S4, the entire resist film RF contracted in the same direction. Therefore, the distance L3 is equal to the distance L4, and the difference value between the distance L3 and the distance L4 is almost zero. In the following steps, changes in the shapes of the resist patterns RP1 to RP3 are measured with the distance L3 or the distance L4 as a reference.

After the second measurement, the heat treatment shown in step S8 of FIG. 1 is performed. The heat treatment is performed, for example, at 80 to 180°C. The heat treatment conditions (temperature, time, etc.) are preferably the same as the heat treatment conditions of step S4. FIG. 9 shows a state in which the resist patterns RP1 to RP3 are contracted by the heat treatment and the shapes of the resist patterns RP1 to RP3 are changed. Since the resist patterns RP1 to RP3 are separated from each other during the heat treatment in step S8, each of the resist patterns RP1 to RP3 shrinks individually. Then, as shown in FIG. 9, the resist pattern RP2 having a large volume has a large shrinkage, but the resist patterns RP1 and RP3 having a small volume have a small shrinkage.

Next, the third measurement shown in step S9 of FIG. 1 is performed. In the third measurement, the distance L5 and the distance L6 shown in FIG. 9 are measured. The distance L5 is the distance from the end E1a of the resist pattern RP1 to the end E2a of the resist pattern RP2, and the distance L6 is the distance from the end E1c of the resist pattern RP1 to the end E3a of the resist pattern RP3.

Next, as shown in step S10 of FIG. 1, a process of determining the presence or absence of the deceived amount is performed. When the distance L5 is different from the reference distance L3 and the distance L6 is different from the reference distance L4, it can be determined that the shape of each of the resist patterns RP1 to RP3 has changed. Next, when the distance L5 and the distance L6 are different from the distance L3 and the distance L4, respectively, the difference value of the distance L5 and the distance L6 is calculated. As a result, it can be seen that when there is a difference between the two, the resist patterns RP1 to RP3 are affected by the tensile stress, and the misalignment of the resist patterns RP1 to RP3 includes the amount of deception.

Here, if the difference value between the distance L5 and the distance L6 is zero, or if the difference value is minute enough to be acceptable, the deceived amount is determined to be “none”. In this case, the process proceeds from step S10 to step S14, the resist patterns RP1 to RP3 are removed by an ashing process, and the resist patterns RP1 to RP3 are formed again through steps S2 to S5. After that, the first measurement in step S6 is performed, and if the result of the positional deviation determination is good in step S15, the process proceeds to step S16.

However, if a difference occurs between the distance L5 and the distance L6 and the difference value is in an unacceptable amount, the deceived amount is determined to be “present”. In this case, the process proceeds from step S10 to step S11, and the deceived amount is calculated.

By the way, in the present embodiment, as described above, the distance L3 and the distance L4 are measured in the second measurement of step S7, but the second measurement of step S7 is omitted, and after the first measurement of step S6, step S8 is performed. The heat treatment of and the third measurement of step S9 may be performed. Also in this case, the distance L5 and the distance L6 are measured, and the difference value between the distance L5 and the distance L6 is calculated. If the difference between the distance L5 and the distance L6 is almost zero, it can be determined that the positional deviation of the resist patterns RP1 to RP3 does not include the amount of deception caused by the tensile stress. Further, if there is a difference between the two, it can be determined that the misregistration amount is included in the positional deviation of the resist patterns RP1 to RP3. As described above, by directly calculating the difference value between the distance L5 and the distance L6 for the resist patterns RP1 to RP3 deformed by the heat treatment in step S8, it is possible to determine the presence or absence of the deceived amount.

When it is determined in step S10 that the deceived amount is “present”, the fourth measurement shown in step S11 of FIG. 1 is performed. In the fourth measurement, the distance L7 and the distance L8 shown in FIG. 9 are measured. The distance L7 is the distance from the end Ema of the inspection mark MK to the end E1a of the resist pattern RP1, and the distance L8 is the distance from the end Emb of the inspection mark MK to the end E1c of the resist pattern RP1. is there. After that, the deceived amount is obtained by calculating half of the difference value between the distance L7 and the distance L8 (value of (L7-L8)/2).

FIG. 10 is a table showing the measurement data obtained as a result of performing the heat treatment of step S8, the third measurement of step S9, the determination process of step S10, and the fourth measurement of step S11 at least twice. Further, FIG. 11 is a table showing a calibration curve (a line shown by a broken line) obtained from the measurement data of FIG. 10, and is a graph showing the relationship between the deformation of the resist patterns RP1 to RP3 and the deceived amount. is there.

Using the calibration curve of FIG. 11, the matching process shown in step S12 of FIG. 1 is performed. That is, it is possible to calculate the amount of deception (value of (L7-L8)/2) corresponding to the value of (L5-L6) based on the prepared calibration curve. For example, when the value of (L5-L6) is 292.4 nm, it can be calculated that the deceived amount is 200 nm. Further, if the condition of the heat treatment of the first step S9 is the same as the condition of the heat treatment of step S4, by collating the value of (L5-L6) of the first time with the calibration curve, the cheat corresponding to the calibration curve is obtained. The amount ((L7−L8)/2 value) can be calculated.

The calibration curve of FIG. 11 created by performing steps S8 to S11 twice or more may be created during the manufacturing process as in the present embodiment, or may be created in advance by an experiment performed under the same conditions. May be created.

Next, as shown in step S13 of FIG. 1, the deceived amount calculated using the calibration curve is fed back to the first measurement of step S6. That is, from the half of the difference value of the distance L1 and the distance L2 (the value of (L1-L2)/2) to the half of the difference value of the correction value of the distance L7 and the distance L8 (the value of (L7-L8)/2) Is corrected so that For example, when the deceived amount is 200 nm, half the difference value between the distance L1 and the distance L2 measured in step S6 is corrected to a value shifted by 200 nm. That is, the deceived amount calculated in step S12 is used as the correction value used for the inspection of the positional deviation between the resist pattern RP1 and the inspection mark MK.

Further, in the present embodiment, the positional deviation in the X direction has been described, but for the positional deviation in the Y direction, the deceived amount is calculated by a similar procedure, and the result is calculated in step S6. 1 Feedback to measurement.

Next, as shown in step S14 of FIG. 1, the resist patterns RP1 to RP3 are removed by an ashing process. Then, the resist patterns RP1 to RP3 are formed again by performing the same processing as steps S2 to S5. Then, in the second measurement of step S6, by using the value fed back in step S13, the positional deviation of the resist patterns RP1 to RP3 is measured, and the determination process of step S15 is performed.

If the determination result of step S15 is good (YES), as shown in step S16, the next manufacturing process using the resist patterns RP1 to RP3, such as an ion implantation process, is performed. If the determination result of step S15 is not good (NO), it means that the formation positions of the resist patterns RP1 to RP3 are deviated, so the resist patterns RP1 to RP3 are once removed, and the resist patterns RP1 to RP1 are again formed in step S2. Remake RP3.

If the same product or a product using the same mask pattern is used, the feedback result may be used. Therefore, in the second and subsequent wafer processing, the steps S7 to S14 are performed again and the deceived amount is calculated again. do not have to. That is, in the semiconductor substrate processed after the semiconductor substrate SUB of the present embodiment, the same processing as steps S1 to S6 is performed, and then the determination processing of step S15 is performed. In step S15, the deception amount (value of (L7-L8)/2) which is a correction value is subtracted from half of the difference value of the distance L1 and the distance L2 (value of (L1-L2)/2). Done. Therefore, when the measured value of the positional deviation in step S6 is determined to be within the allowable range in step S15, the semiconductor substrate is moved to step S16.

As described above, according to the present embodiment, even if the misregistration of the misregistration due to the deceived amount is included in the inspection of the misregistration of the resist patterns RP1 to RP3 using the inspection mark MK, It can be determined whether the positional deviation is due to the deceived amount.

Further, by the collation process (step S12) using the calibration curve shown in FIG. 11, the deceived amount can be measured, and the result can be fed back to the first measurement in step S6. It is possible to perform the measurement of the positional deviation with the exclusion. Therefore, the accuracy of the inspection of the positional deviation of the resist patterns RP1 to RP3 is improved, and the performance of the semiconductor device manufactured using the resist patterns RP1 to RP3 can be improved.

Further, although the case where the element isolation portion STI is used as the inspection mark MK is described in the present embodiment, the inspection mark MK may be a structure other than the element isolation portion STI. For example, the inspection mark MK may be a conductive film in the same layer as the gate electrode of the field effect transistor, or may be a metal film in the same layer as the wiring mainly composed of aluminum or copper.

(Embodiment 2)
The manufacturing method and the inspection method of the semiconductor device according to the second embodiment will be described below with reference to FIGS. 12 and 13. In the following description, differences from the first embodiment will be mainly described. 12 is a plan view of relevant parts of the semiconductor device according to the second embodiment, and FIG. 13 is a sectional view taken along line AA shown in FIG. Further, FIG. 13 corresponds to the state of FIG. 6 of the first embodiment, and FIG. 12 shows a plan view during the manufacturing process of FIG.

In the first embodiment, the area of resist pattern RP1 is larger than the area of inspection mark MK in plan view, and resist pattern RP1 is formed so as to cover the entire inspection mark MK. Further, the resist pattern RP2 and the resist pattern RP3 were formed around the inspection mark MK and the resist pattern RP1. That is, the resist pattern RP2 and the resist pattern RP3 are formed so as not to overlap the inspection mark MK in a plan view.

As shown in FIGS. 12 and 13, in the second embodiment, the area of resist pattern RP1 is smaller than the area of inspection mark MK in plan view, and resist pattern RP1 is included in inspection mark MK. .. A part of the resist pattern RP2 and a part of the resist pattern RP3 are also formed on the inspection mark MK. In the X direction, the inspection mark MK has a length of 12 to 20 μm, the resist pattern RP1 has a length of 4 μm or less, and the distance between the resist pattern RP2 and the resist pattern RP3 is 5 to 10 μm.

Also in the second embodiment, it is possible to determine whether or not the positional deviation of the resist patterns RP1 to RP3 is due to the deceived amount, by using the same method as in the first embodiment, as shown in FIG. By the collation process using the calibration curve (step S12), the deceived amount can be measured, and the result can be fed back to the first measurement in step S6.

(Embodiment 3)
The method of manufacturing the semiconductor device of the third embodiment will be described below with reference to FIGS. 14 and 15. In the third embodiment, a specific example of step S15 of FIG. 1 will be described. That is, FIGS. 14 and 15 show a method of manufacturing the field effect transistor 1Q formed in the region 1A and the field effect transistor 2Q formed in the region 2A of the element formation region.

As shown in FIG. 14, first, a p-type support substrate SS is prepared. Next, the n-type impurity region NBL is formed on the surface of the support substrate SS by the photolithography technique and the ion implantation method. Next, the p-type epitaxial layer EP having a thickness of about 4 μm is formed on the support substrate SS by an epitaxial growth method. As a result, the semiconductor substrate SUB including the support substrate SS including the impurity region NBL and the epitaxial layer EP is formed. Next, the element isolation portion STI is formed near the surface of the semiconductor substrate SUB. The element isolation portion STI is formed by the same step as the step of forming the inspection mark MK in step S1 of FIG.

Next, on the semiconductor substrate SUB, a resist pattern RP5 having a pattern covering the region 2A and opening the region 1A is formed. The resist pattern RP5 used in the third embodiment is formed by patterning the resist film RF similarly to the resist patterns RP1 to RP3 in the first embodiment or the second embodiment. That is, the resist pattern RP5 is a resist pattern formed after the deceived amount calculated using the calibration curve is fed back to the first measurement of step S6 as a correction value.

Next, ion implantation is performed using the resist pattern RP5 as a mask to selectively form the p-type impurity region PiSO in the semiconductor substrate SUB in the region 1A. Impurity region PiSO is formed at a deep position of epitaxial layer EP in semiconductor substrate SUB. As described above, since the thickness of the epitaxial layer EP is about 4 μm, in order for the resist pattern RP5 to function as a mask in this ion implantation, the thickness of the resist pattern RP5 is required to be 4 μm or more, for example. To be

As described in the first embodiment, when the resist pattern (resist film RF) is very thick, the amount of shrinkage of the resist film RF is large and a large tensile stress is likely to occur. Then, due to this, the amount of deception is increased, and there is a problem that it is erroneously determined that the resist pattern is displaced. Here, since the resist pattern RP5 is formed after the deceived amount calculated using the calibration curve is fed back to the first measurement in step S6, the position of the resist pattern RP5 is within the allowable range of design values. Is formed of. Therefore, the impurity region PiSO is accurately formed.

The ion implantation is also performed on the semiconductor substrate SUB between the resist patterns RP1 and RP2 and the semiconductor substrate SUB between the resist patterns RP1 and RP3. Therefore, an impurity region similar to the impurity region PiSO is also formed in these semiconductor substrates SUB.

After that, as shown in FIG. 15, through various steps, the field effect transistor 1Q is formed in the region 1A and the field effect transistor 2Q is formed in the region 2A.

First, the resist pattern RP5 is removed by an ashing process. Next, by photolithography and ion implantation, an n-type well region NW is formed in the semiconductor substrate SUB in the region 1A, and a p-type well region PW is formed in the semiconductor substrate SUB in the regions 1A and 2A. Next, on the semiconductor substrate SUB in the regions 1A and 2A, the gate insulating films GI1 and GI2 made of, for example, silicon oxide are formed by the thermal oxidation method or the CVD method. Next, for example, a polycrystalline silicon film is formed on the gate insulating films GI1 and GI2 by the CVD method, and then the polycrystalline silicon film is patterned to form the gate electrodes GE1 and GE1 on the gate insulating films GI1 and GI2. GE2 is formed respectively.

Next, the n-type impurity regions EXS and EXD are formed in the semiconductor substrate SUB in the region 2A by the photolithography technique and the ion implantation method. Next, a silicon nitride film, for example, is formed on the semiconductor substrate SUB by the CVD method, and then the silicon nitride film is subjected to anisotropic etching to form sidewalls on the side surfaces of the gate electrodes GE1 and GE2. The spacer SW is formed. Next, by photolithography and ion implantation, n-type impurity regions NS and ND are formed in the well region NW and the well region PW in the region 1A and the well region PW in the region 2A, respectively.

In region 1A, impurity region ND and well region NW form the drain region of field effect transistor 1Q, and impurity region NS formed in well region PW forms the source region of field effect transistor 1Q. In region 2A, impurity region ND and impurity region EXD form the drain region of field effect transistor 2Q, and impurity region NS and impurity region EXS form the source region of field effect transistor 2Q.

Next, the interlayer insulating film IL made of, for example, silicon oxide is formed on the semiconductor substrate SUB by the CVD method so as to cover the field effect transistors 1Q and 2Q. Next, a contact hole is formed in the interlayer insulating film IL by a photolithography technique and an etching process, and then a conductive film mainly containing, for example, tungsten is formed by a CVD method so as to fill the contact hole. Next, the conductive film outside the contact hole is removed by a CMP method or an etching process, so that the plug PG made of the conductive film is formed in the contact hole of the interlayer insulating film IL.

Next, the wiring M1 made of, for example, a laminated film of a titanium nitride film, an aluminum film, and a titanium nitride film is formed on the interlayer insulating film IL. The wiring M1 is electrically connected to the impurity regions ND and NS via the plug PG.

After that, a multilayer wiring and an interlayer insulating film are formed on the wiring M1 and the interlayer insulating film IL, but the description thereof is omitted here. Through the above steps, the semiconductor device shown in FIG. 15 is manufactured.

Although the invention made by the inventor of the present application has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Is.

1A, 2A Regions 1Q, 2Q Field effect transistors E1a to E1d, E2a, E2b, E3a, E3b, Ema, Emb Edge EP EP layer EXD Impurity region EXS Impurity region GE1, GE2 Gate electrode GI1, GI2 Gate insulating film IL Interlayer insulation Film M1 Wiring MK Inspection mark NBL Impurity region ND Impurity region NS Impurity region NW Well region RF Resist film PG plug PiSO Impurity region PW Well regions RP1 to RP5 Resist patterns S1 to S16 Step SS Support substrate STI Element isolation part SUB Semiconductor substrate SW Sidewall spacer

Claims (20)

(A) a step of forming an inspection mark on a semiconductor substrate,
(B) a step of forming a resist film on the semiconductor substrate and on the inspection mark,
(C) By patterning the resist film, the first resist pattern located on the inspection mark is adjacent to both sides of the first resist pattern, and is separated from the first resist pattern in a sectional view. Forming a second resist pattern and a third resist pattern,
(D) A first distance between the first end of the upper surface of the first resist pattern on the second resist pattern side and the second end of the upper surface of the inspection mark on the second resist pattern side is set. The second distance between the third end of the upper surface of the first resist pattern on the third resist pattern side and the fourth end of the upper surface of the inspection mark on the third resist pattern side is measured. Measuring and calculating half of a difference value between the first distance and the second distance,
(E) a step of performing a first heat treatment on the first, second and third resist patterns after the step (d),
(F) After the step (e), a fifth distance between the fifth end portion and the first end portion of the upper surface of the second resist pattern on the first resist pattern side is measured to obtain the first resist. Measuring a sixth distance between a sixth end of the upper surface of the third resist pattern on the pattern side and the third end, and calculating a difference value between the fifth distance and the sixth distance,
Having an inspection method. The inspection method according to claim 1,
(G) After the step (f), a seventh distance between the first end portion and the second end portion is measured, and an eighth distance between the third end portion and the fourth end portion is measured. Measuring step,
(H) By performing the steps (e) to (g) at least twice, the difference value between the fifth distance and the sixth distance and the difference value between the seventh distance and the eighth distance can be calculated. Creating a calibration curve showing the relationship with half,
(I) After the step (h), the difference value between the fifth distance and the sixth distance measured for the first time is collated with the calibration curve, and the seventh distance and the eighth distance corresponding to the calibration curve are compared. Calculating a half of the difference value of the distance as the first correction value,
(J) feeding back the first correction value to the step (d) so that the first correction value is subtracted from half of the difference value between the first distance and the second distance;
An inspection method further comprising: The inspection method according to claim 2,
In the step (c),
(C1) a step of selectively performing an exposure process on a part of the resist film,
(C2) a step of performing a second heat treatment on the resist film after the step (c1),
(C3) After the step (c2), a development process is performed on the resist film to remove a portion of the resist film exposed in the step (c1), and expose in the step (c1). A step of leaving a portion which has not been formed as the first, second and third resist patterns,
Having an inspection method. The inspection method according to claim 3,
The first heat treatment is an inspection method performed under the same conditions as the second heat treatment. The inspection method according to claim 3,
The inspection method, wherein the volume of the second resist pattern is larger than the volume of the first resist pattern and the volume of the third resist pattern. The inspection method according to claim 5,
The inspection method, wherein the resist film has a thickness of 4 μm or more. The inspection method according to claim 1,
In the step (c), the distance from the first resist pattern to the resist pattern surrounding the first resist pattern is the same in the first direction and the second direction orthogonal to the first direction in plan view. There is an inspection method. The inspection method according to claim 7,
The inspection method, wherein in the step (c), the distance from the first resist pattern to the resist pattern surrounding the first resist pattern is 3 to 10 μm. The inspection method according to claim 1,
In plan view, the area of the first resist pattern is larger than the area of the inspection mark,
The inspection method, wherein the second resist pattern and the third resist pattern are formed around the inspection mark and the first resist pattern. The inspection method according to claim 1,
In plan view, the area of the first resist pattern is smaller than the area of the inspection mark,
An inspection method, wherein a part of the second resist pattern and a part of the third resist pattern are formed on the inspection mark. A method of manufacturing a semiconductor device comprising a first semiconductor substrate having an element formation region and a scribe region surrounding the element formation region,
(A) forming an inspection mark on the first semiconductor substrate in the scribe region,
(B) forming a resist film on the first semiconductor substrate and on the inspection mark,
(C) By patterning the resist film, in the scribe region, a first resist pattern located on the inspection mark and adjacent to both sides of the first resist pattern, and in cross section, the first resist pattern Forming a second resist pattern and a third resist pattern separated from the resist pattern, and forming a fourth resist pattern in the element forming region,
(D) A first distance between the first end of the upper surface of the first resist pattern on the second resist pattern side and the second end of the upper surface of the inspection mark on the second resist pattern side is set. The second distance between the third end of the upper surface of the first resist pattern on the third resist pattern side and the fourth end of the upper surface of the inspection mark on the third resist pattern side is measured. Measuring and calculating half of a difference value between the first distance and the second distance,
(E) a step of performing a first heat treatment on the first, second, third and fourth resist patterns after the step (d),
(F) After the step (e), a fifth distance between the fifth end portion and the first end portion of the upper surface of the second resist pattern on the first resist pattern side is measured to obtain the first resist. Measuring a sixth distance between a sixth end of the upper surface of the third resist pattern on the pattern side and the third end, and calculating a difference value between the fifth distance and the sixth distance,
(G) After the step (f), a seventh distance between the first end portion and the second end portion is measured, and an eighth distance between the third end portion and the fourth end portion is measured. Measuring step,
(H) By performing the steps (e) to (g) at least twice, the difference value between the fifth distance and the sixth distance and the difference value between the seventh distance and the eighth distance can be calculated. Creating a calibration curve showing the relationship with half,
(I) After the step (h), the difference value between the fifth distance and the sixth distance measured for the first time is collated with the calibration curve, and the seventh distance and the eighth distance corresponding to the calibration curve are compared. Calculating a half of the difference value of the distance as the first correction value,
(J) feeding back the first correction value to the step (d) so that the first correction value is subtracted from half of the difference value between the first distance and the second distance;
(K) a step of removing the first, second, third and fourth resist patterns after the step (j).
(L) After the step (k), in the step (d), the first correction value is subtracted from half of the difference value between the first distance and the second distance. (D) performing step,
(M) In the step (d) performed again after the step (l), a value obtained by subtracting the first correction value from half of the difference value between the first distance and the second distance is an allowable range. The step of determining whether or not
(N) When the determination result of the step (m) is within the allowable range, ion implantation is performed using the fourth resist pattern as a mask to make the first semiconductor substrate in the element formation region first in the first semiconductor substrate. Forming an impurity region,
A method of manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 11,
(O) a step of preparing a second semiconductor substrate different from the first semiconductor substrate after the step (n),
(P) a step of performing the same processing as the steps (a) to (d) on the second semiconductor substrate,
Further having
The method (d) performed on the second semiconductor substrate is performed such that the first correction value is subtracted from half the difference value between the first distance and the second distance. .. The method of manufacturing a semiconductor device according to claim 11,
(Q) after the step (p), forming a field effect transistor on the first semiconductor substrate in which the first impurity region is formed,
A method for manufacturing a semiconductor device, further comprising: The method of manufacturing a semiconductor device according to claim 11,
In the step (n), the first semiconductor substrate between the first resist pattern and the second resist pattern, and the first semiconductor substrate between the first resist pattern and the third resist pattern. Also, a method of manufacturing a semiconductor device, wherein the ion implantation is performed. The method of manufacturing a semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the second resist pattern is formed over the scribe region and the element formation region. The method of manufacturing a semiconductor device according to claim 11,
In the step (c),
(C1) a step of selectively performing an exposure process on a part of the resist film,
(C2) a step of performing a second heat treatment on the resist film after the step (c1),
(C3) After the step (c2), a development process is performed on the resist film to remove a portion of the resist film exposed in the step (c1), and expose in the step (c1). A step of leaving the unremoved part as the first, second, third and fourth resist patterns,
A method of manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 16,
The method for manufacturing a semiconductor device, wherein the first heat treatment is performed under the same conditions as the second heat treatment. The method of manufacturing a semiconductor device according to claim 17,
The method of manufacturing a semiconductor device, wherein the volume of the second resist pattern is larger than the volume of the first resist pattern and the volume of the third resist pattern. The method of manufacturing a semiconductor device according to claim 18,
The method of manufacturing a semiconductor device, wherein the resist film has a thickness of 4 μm or more. The method of manufacturing a semiconductor device according to claim 11,
In the step (c), the distance from the first resist pattern to the resist pattern surrounding the first resist pattern is the same in the first direction and the second direction orthogonal to the first direction in plan view. A method for manufacturing a semiconductor device.

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