JP2014229726A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve overlay accuracy in a main body pattern within a main body chip area in a lithography step.SOLUTION: Within a main body chip area of a mask MSKS of a processing layer which is exposed before a layer to be aligned, a CMP dummy area DAS is provided for disposing a plurality of CMP dummies DP therein and within a main body chip area of a mask MSKG to be used for exposing the layer to be aligned, a CMP dummy area DAG is provided in which an alignment mark AMG and the plurality of CMP dummies DP are disposed. The alignment mark AMG is disposed in an overlap area DAD extracted from the CMP dummy area DAS of the mask MSKS of the processing layer which is exposed before the layer to be aligned, and the CMP dummy area DAG of the mask MSKG of the layer to be aligned. In the mask MSKS of the processing layer which is exposed before the layer to be aligned, no CMP dummy DP is disposed at a position corresponding to the alignment mark AMG.

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and can be suitably used for, for example, an exposure processing method in a lithography process and a semiconductor device using the method.

  In an exposure apparatus used in a lithography process of a semiconductor manufacturing process, alignment of an original plate (mask) and a transferred substrate (semiconductor substrate, semiconductor wafer) is performed.

  For example, in Japanese Patent Application Laid-Open No. 11-097326 (Patent Document 1), in the electron beam exposure method, when a position of an alignment mark is detected, a function used for chip alignment on a wafer is described as follows. A technique using a function including a quadratic term of X · X or X · Y or Y · Y of the coordinate system X and Y on the wafer of the chip is disclosed.

  Japanese Patent Application Laid-Open No. 2000-208392 (Patent Document 2) discloses an alignment mark formed on a scribe line or a non-component part region of a wafer and the periphery of the alignment mark, which is protected from chemical mechanical polishing. An alignment mark structure having a protective dummy pattern is disclosed.

  Japanese Unexamined Patent Application Publication No. 2007-081241 (Patent Document 3) discloses a method of forming alignment marks, which are grooves, on the surface of a wiring film.

  Japanese Laid-Open Patent Publication No. 2001-193268 (Patent Document 4) discloses a technique for reducing dishing of an interlayer insulating film in a peripheral region of an alignment mark used for alignment of a photomask.

JP-A-11-097326 JP 2000-208392 A JP 2007-081241 A JP 2001-193268 A

  Alignment marks and overlay inspection marks used for alignment of the original (mask) and transferred substrate (semiconductor substrate, semiconductor wafer) are located in a scribe area provided around the main body chip area with a high degree of freedom in pattern layout. It is arranged. However, even if the overlay accuracy is improved in the scribe region, there is a problem in that overlay deviation occurs in the main body pattern in the main body chip region, and high overlay accuracy cannot be obtained.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a CMP dummy region is provided in a body chip region of a mask used for exposure of a processed layer before the layer to be bonded, and alignment is performed in the body chip region of a mask used for exposure of the layer to be bonded. A CMP dummy area in which marks are arranged is provided. The alignment mark is arranged in an overlapping area extracted from the CMP dummy area of the mask of the processed layer to be exposed before the layer to be matched and the CMP dummy area of the mask of the layer to be matched, and is exposed before the layer to be matched. A CMP dummy is not arranged at a position corresponding to the alignment mark in the mask of the processed layer to be processed.

  According to one embodiment, a CMP dummy region is provided in the main body chip region of a mask used for exposure of a processed layer before the layer to be bonded, and the main chip region of the mask used for exposure of the layer to be bonded is provided. A CMP dummy region in which a first overlay inspection mark is disposed is provided, and a CMP dummy region in which a second overlay inspection mark is disposed in a main body chip region of a mask used for exposure of the exposure layer. The first and second overlay inspection marks include a CMP dummy region of a mask of a processed layer that is exposed before the layer to be matched, a CMP dummy region of a mask of the layer to be matched, and a CMP dummy region of a mask of the exposure layer. In the mask of the processing layer that is arranged in the overlapping region extracted from the above and exposed before the layer to be bonded, no CMP dummy is arranged at a position corresponding to the first and second overlay inspection marks.

  According to one embodiment, in a lithography process, an alignment mark and an overlay inspection mark used for alignment between an original (mask) and a transferred substrate (semiconductor substrate, semiconductor wafer) are arranged in the main body chip region. The overlay accuracy in the main body pattern in the main body chip region can be improved.

It is process drawing explaining an example of the procedure of the alignment method of a reduction projection exposure apparatus. It is the schematic explaining the example of arrangement | positioning of the conventional alignment mark. It is the schematic explaining the example of arrangement | positioning of the overlay inspection mark arrange | positioned at the conventional exposure layer and a to-be-matched layer. It is the schematic explaining the arrangement | positioning method of the alignment mark by this Embodiment. It is the schematic explaining the arrangement | positioning method of the overlay inspection mark by this Embodiment. It is a schematic diagram explaining the state of distortion of a wafer. It is the schematic explaining the arrangement | positioning method of the alignment mark by this Embodiment. FIG. 5 is a schematic diagram for explaining a method for arranging alignment marks on a mask of a gate layer (layer to be bonded) according to the first embodiment. FIG. 5 is a schematic diagram for explaining a method for arranging overlay inspection marks on a mask for a contact layer (exposure layer) and a mask for a gate layer (matched layer) according to the first embodiment. FIG. 10 is a schematic diagram for explaining a method for arranging alignment marks on a mask of a contact layer (layer to be bonded) according to the second embodiment. It is the schematic explaining the method to arrange | position an overlay inspection mark to the mask of the 1st wiring layer (exposure layer) and contact layer (matching layer) by Embodiment 2, respectively. It is the schematic explaining the method to arrange | position an overlay inspection mark to the mask of the 1st wiring layer (exposure layer) and contact layer (matching layer) by Embodiment 2, respectively. FIG. 10 is a schematic diagram for explaining a method of arranging alignment marks on a mask of a first via hole layer (layer to be bonded) according to a third embodiment. FIG. 10 is a schematic diagram for explaining a method of arranging alignment marks on a mask of a second wiring layer (layer to be bonded) according to the third embodiment. FIG. 10 is a schematic diagram for explaining a method for arranging overlay inspection marks on a mask for a second wiring layer (exposure layer) and a mask for a first via hole layer (matched layer) according to the third embodiment. FIG. 10 is a schematic diagram for explaining a method of placing overlay inspection marks on a mask for a second via hole layer (exposure layer) and a mask for a second wiring layer (matched layer) according to the third embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device showing the method of manufacturing the semiconductor device (field effect transistor) according to the third embodiment. FIG. 17 is an essential part cross-sectional view of the same place as that in FIG. 16 during the manufacturing process of the semiconductor device, following FIG. 16; FIG. 18 is an essential part cross-sectional view of the same place as that in FIG. 16 during the manufacturing process of the semiconductor device, following FIG. 17; FIG. 19 is an essential part cross-sectional view of the same place as that in FIG. 16 during the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is an essential part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 19; FIG. 21 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 20; FIG. 22 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 21; FIG. 23 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 22; FIG. 24 is an essential part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 23; FIG. 25 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 24; FIG. 26 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 25; FIG. 27 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 26; FIG. 28 is a principal part cross-sectional view of the same place as in FIG. 16 in the process of manufacturing the semiconductor device, following FIG. 27;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  The first and second problems to be solved in the exposure processing method found by the present inventors and means for solving each problem will be described.

  First, an alignment method of a conventional reduced projection exposure apparatus performed in an exposure process which is one manufacturing process of a semiconductor device will be described with reference to FIG. FIG. 1 is a process diagram for explaining an example of the procedure of the alignment method of the reduced projection exposure apparatus. In the exposure process, a resist pattern of a processed layer having a plurality of product regions arranged via a scribe region is formed on the wafer, and a mask used in the exposure step is provided on one or more product regions of the processed layer. The pattern data of the corresponding main body chip area is drawn.

  A wafer coated with a resist film is prepared, and the wafer notch is first aligned by pre-alignment.

  Subsequently, using the rough alignment mark of the mating layer arranged in the scribe area of the shot, the rough alignment mark of about 2 shots is detected, and the alignment of the wafer in the X direction, the Y direction, and the rotation direction is performed. Perform (rough alignment).

  Subsequently, the position of the fine alignment mark of about 10 shots is measured using the fine alignment mark of the mating layer arranged in the scribe area of the shot, and the linear misalignment component shift (Sx, Sy) and scaling are performed. (Mx, My), orthorality (θx−θy), and rotation (θy) are calculated (fine alignment).

  After the measurement, global exposure (EGA (Enhanced Global Alignment)) is performed. In global exposure, exposure is performed by predicting the position of each shot based on shift, scaling, authority, and rotation calculated by fine alignment. Also, die-by-die exposure (Die-by-Die Alignment) may be performed. Although there is a drawback that the throughput is low, the overlay accuracy can be increased. In die-by-die exposure, exposure is performed while performing position measurement for each shot after fine alignment.

  After the exposure, the overlay deviation amount between the mating layer and the exposure layer is measured using the overlay inspection mark of the mating layer and the overlay inspection mark of the exposure layer formed with a pattern made of a resist film. . Thereafter, the measured overlay deviation amount is fed back to the next lot exposure to correct the alignment.

<About the first issue>
A conventional arrangement example of alignment marks will be described with reference to FIG. The exposure layer described in FIG. 2 is the first wiring (M1) layer, the mating layer is the contact layer, and the processing layer exposed before the mating layer is the gate layer or element isolation (STI (Shallow)). Trench Isolation)) layer, and is exposed in the order of STI layer → Gate layer → Contact layer → M1 layer.

  The alignment mark AMC formed on the mask MSKC of the mating layer is arranged in the scribe area SA around the main body chip area SC. An extra pattern is not arranged in the vicinity of the alignment mark AMC of the layer to be bonded. Further, with respect to the masks MSKG and MSKS of the processed layer that are exposed before the layer to be matched, a pattern is not arranged in and around the location corresponding to the alignment mark AMC of the layer to be matched. This prevents erroneous mark detection during exposure.

  An arrangement example of overlay inspection marks arranged on a conventional exposure layer and a layer to be bonded will be described with reference to FIG. The exposure layer described in FIG. 3 is the first wiring (M1) layer, the mating layer is a contact layer, and the processing layer exposed before the mating layer is a gate layer or an element isolation (STI) layer. The exposure is performed in the order of STI layer → Gate layer → Contact layer → M1 layer.

  The overlay inspection mark IMC formed on the mask MSKC of the mating layer and the overlay inspection mark IMM1 formed on the mask MSKM1 of the exposure layer are arranged in the scribe area SA around the main body chip area SC. In the vicinity of the overlay inspection mark IMC for the layer to be mated and the overlay inspection mark IMM1 for the exposure layer, no extra pattern is arranged. In addition, regarding the masks MSKG and MSKS of the processed layer that are exposed before the layer to be bonded, a pattern is arranged at and near the position corresponding to the overlay inspection mark IMC of the layer to be bonded and the overlay inspection mark IMM1 of the exposure layer. Do not. This prevents erroneous mark detection during overlay inspection.

  As described above, the alignment mark and the overlay inspection mark need to be laid out in consideration of the influence on not only the exposed layer and the layer to be combined but also the processed layer processed before that. For this reason, the alignment mark and the overlay inspection mark are arranged in a scribe region having a high degree of freedom in pattern layout.

  However, when alignment marks and overlay inspection marks are arranged in the scribe area, the main body pattern in the main body chip area can be improved for the following reasons (1) and (2). Then, overlay deviation occurs.

  Reason (1): Actually, the distance between the main body pattern in the main body chip area that requires overlay accuracy and the alignment mark and overlay inspection mark is large.

  Reason (2): The main body pattern in the main body chip area and the scribe area have slightly different processing shapes and the like due to differences in pattern density and the like.

  It is only necessary that the alignment mark and the overlay inspection mark can be arranged in the vicinity of the main body pattern that requires overlay accuracy. However, since the alignment mark and overlay inspection mark must be placed in the main body chip area so as not to affect the main body pattern, the alignment mark and overlay inspection mark should simply be placed in the main body chip area. Is not easy.

  In the present embodiment, alignment marks and overlay inspection marks can be easily arranged in the main body chip area without using a new DA (Design Automation) tool or the like. As a result, alignment marks and overlay inspection marks can be arranged in the vicinity of the main body pattern in the main body chip area that actually requires overlay accuracy, and the overlay accuracy can be improved.

<About the first means for solving the first problem>
In the processed layer, a dummy pattern called a CMP (Chemical Mechanical Polishing) dummy is often arranged in a region having no pattern in the main body chip region. By using the CMP dummy to uniformize the pattern density in the main body chip region, it becomes possible to improve the CMP processing flatness. The CMP dummy is automatically arranged using a tool according to a certain arrangement rule.

  An example of the placement rule for the CMP dummy placed in the first wiring layer is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. It is preferable that the pattern used for the CMP dummy has a wide process margin and is not too large so that the pattern density can be adjusted to be constant in various pattern layouts, but there is no significant limitation on the shape or the like. Therefore, in the region where the CMP dummy is arranged, a pattern used for the CMP dummy can be placed relatively freely if no significant difference is generated in the pattern density.

  In the present embodiment, an alignment mark and an overlay inspection mark are arranged in a region where a CMP dummy is arranged in the main body chip region. Usually, since a CMP dummy exists, even if an alignment mark and an overlay inspection mark are arranged there, the influence on the main body pattern is hardly seen.

  A method of arranging alignment marks in the main body chip region of the layer to be bonded will be described with reference to FIG. FIG. 4 is a schematic diagram for explaining a method of arranging alignment marks on the mask of the layer to be bonded according to the present embodiment. The exposure layer described in FIG. 4 is a contact layer, the mating layer is a gate layer, and the processing layer exposed before the mating layer is an element isolation (STI) layer. STI layer → Gate layer → The exposure is performed in the order of the Contact layer.

1. First Step First, the CMP dummy arrangement region DAG in the main body chip region is extracted from the layout of the mask MSKG of the mating layer, and the mask layer MSKS of the processing layer exposed before the mating layer is extracted from the layout of the main chip region. The CMP dummy arrangement area DAS is extracted.

2. Second Step A CMP dummy overlapping area DAD between the CMP dummy arrangement area DAG and the CMP dummy arrangement area DAS is extracted.

3. Third Step A position AMP where the alignment mark is to be arranged is determined from within the CMP dummy overlapping area DAD. The alignment mark is preferably arranged near the main body pattern that requires high overlay accuracy in the main body chip region.

4). 4th step Alignment mark AMG is arrange | positioned in position AMP which arrange | positions the alignment mark of a to-be-matched layer.

5. Fifth Step A plurality of CMP dummy DPs are arranged in the CMP dummy arrangement region DAG in the main body chip region of the mating layer. Similarly, the CMP dummy DP is arranged in the CMP dummy arrangement area DAS in the main body chip area of the processed layer to be exposed before the layer to be bonded.

  In order to prevent erroneous mark detection in the vicinity of the alignment mark AMG, the CMP dummy DP is not disposed at a predetermined distance from the pattern end of the alignment mark AMG. That is, the mark region AG is composed of a first region where the alignment mark AMG is arranged, and a second region around the first region and a predetermined distance from the pattern end of the alignment mark AMG, for example, within 0.3 μm. Does not arrange a CMP dummy DP.

  Similarly, in the processed layer exposed before the layer to be bonded, in order to prevent erroneous mark detection, the CMP dummy DP is not arranged in the mark area AS corresponding to the mark area AG where the CMP dummy DP is not arranged. .

  However, if the areas AG and AS in which the CMP dummy DP is not disposed are remarkably increased, the pattern density is changed to affect the processing flatness of the CMP. Therefore, the mark areas AG and AS in which the CMP dummy DP is not disposed are within a predetermined range. It is necessary to.

  By using the method of arranging the alignment mark in the main body chip region described above, the alignment mark can be arranged in the vicinity of the main body pattern that requires high overlay accuracy in the main body chip region. By not arranging a CMP dummy in the vicinity of the alignment mark of the mating layer and at the same position of the processed layer exposed before the mating layer, erroneous mark detection is prevented. When there is a processed layer in which no CMP dummy is arranged, a temporary CMP dummy arrangement rule is set in the processed layer, and a temporary CMP dummy arrangement region is calculated. The CMP dummy overlap area is extracted including the provisional CMP dummy arrangement area.

  The location of the alignment mark placed on the layer to be bonded is usually the place where the CMP dummy is placed. If the alignment mark is not remarkably large, even if the CMP dummy is replaced with the alignment mark, the influence on the main body pattern due to the optical proximity effect or the like is small. Since there is no significant change in the pattern density, there is no deterioration in CMP processing flatness. In the processed layer exposed before the layer to be bonded, the CMP dummy is not disposed at the position corresponding to the alignment mark. However, if the alignment mark is not significantly large, the effect on the main body pattern due to the optical proximity effect or the like is small. Since there is no significant change in the pattern density, there is no deterioration in CMP processing flatness.

  Basically, no CMP dummy is disposed at the same position of the processed layer exposed before the layer to be bonded, but a CMP dummy may be disposed for a layer whose pattern cannot be recognized when exposing the exposed layer.

  Next, a method for arranging the overlay inspection mark in the main body chip region of the layer to be bonded and the exposure layer will be described with reference to FIG. FIG. 5 is a schematic diagram for explaining a method of arranging overlay inspection marks on the mask of the layer to be bonded and the mask of the exposure layer according to the present embodiment. The exposure layer described in FIG. 5 is a contact layer, the mating layer is a gate layer, and the processing layer exposed before the mating layer is an element isolation (STI) layer. STI layer → Gate layer → The exposure is performed in the order of the Contact layer.

1. First Step First, the CMP dummy area DAC in the main body chip area is extracted from the layout of the mask MSKC of the exposure layer, and the CMP dummy area DAG in the main body chip area is extracted from the layout of the mask MSKG of the mating layer. The CMP dummy arrangement area DAS in the main body chip area is extracted from the layout of the mask MSKS of the processing layer exposed before the layer.

  However, since the exposure layer is a layer that does not use the CMP dummy DP, a provisional CMP dummy arrangement rule is set, and a provisional CMP dummy arrangement area DAC is extracted.

2. Second Step The CMP dummy overlapping area DAD of the CMP dummy arrangement area DAC, the CMP dummy arrangement area DAG, and the CMP dummy arrangement area DAS is extracted.

3. Third Step From the CMP dummy overlap area DAD, a position IMP at which the overlay inspection mark is arranged is determined. The overlay inspection mark is preferably arranged near the main body pattern that requires high overlay accuracy in the main body chip region.

4). Fourth Step The overlay inspection mark IMC is disposed at the position IMP where the overlay inspection mark of the exposure layer is disposed, and the overlay inspection mark IMG is disposed at the position IMP where the overlay inspection mark of the layer to be matched is disposed.

5. Fifth Step A plurality of CMP dummy DPs are arranged in the CMP dummy arrangement region DAG in the main body chip region of the mating layer. Similarly, the CMP dummy DP is arranged in the CMP dummy arrangement area DAS in the main body chip area of the processed layer to be exposed before the layer to be bonded.

  In the layer to be bonded, the CMP dummy DP is not arranged at a predetermined distance from the pattern end of the overlay inspection mark IMG in order to prevent erroneous mark detection in the vicinity of the overlay inspection mark IMG. That is, it includes a first area where the overlay inspection mark IMG is arranged, and a second area around the first area and within a predetermined distance from the pattern end of the overlay inspection mark IMG, for example, within 0.3 μm. The CMP dummy DP is not arranged in the inspection mark area BG.

  Similarly, in the processed layer exposed before the mating layer, in order to prevent erroneous mark detection, the CMP dummy DP is provided in the inspection mark area BS corresponding to the inspection mark area BG in which the CMP dummy DP of the mating layer is not disposed. Do not place.

  However, if the inspection mark areas BG and BS where the CMP dummy DP is not disposed are significantly increased, the pattern density is changed and the processing flatness of the CMP is affected. Therefore, the inspection mark areas BG and BS where the CMP dummy DP is not disposed are predetermined. Must be within the range.

  By using the above-described method of arranging the overlay inspection mark in the main body chip area, it is possible to place the overlay inspection mark in the vicinity of the main body pattern that requires high overlay accuracy in the main body chip area. . By not providing a CMP dummy in the vicinity of the overlay inspection mark of the mating layer and at the same position of the processed layer exposed before the mating layer, erroneous mark detection is prevented. When there is a processed layer in which no CMP dummy is arranged, a temporary CMP dummy arrangement rule is set in the processed layer, and a temporary CMP dummy arrangement region is calculated. The CMP dummy overlap area is extracted including the provisional CMP dummy arrangement area.

  The location of the overlay inspection mark placed on the exposure layer and the overlay inspection mark placed on the layer to be mated are usually locations where CMP dummy is placed. If the overlay inspection mark is not significantly large, even if the CMP dummy is replaced with the overlay inspection mark, the influence on the main body pattern due to the optical proximity effect or the like is small. Since there is no significant change in the pattern density, there is no deterioration in CMP processing flatness. Further, in the processed layer exposed before the layer to be bonded, the CMP dummy is not disposed at the position corresponding to the overlay inspection mark. The impact is small. Since there is no significant change in the pattern density, there is no deterioration in CMP processing flatness.

  Basically, no CMP dummy is disposed at the same position of the processed layer exposed before the layer to be bonded, but a CMP dummy may be disposed for a layer whose pattern cannot be recognized when exposing the exposed layer.

  As described above, by using this embodiment, an alignment mark and an overlay inspection mark can be easily located in the vicinity of a pattern that actually requires overlay accuracy in the main body chip area without using a new DA tool or the like. Can be arranged, and the actual overlay accuracy can be improved.

<About the second issue>
For example, when an SOI (Silicon On Insulator) wafer is used or when a flash (FLASH) mixed chip is formed, there is a problem that the wafer WAF or the chip is complicatedly distorted by applying heat treatment as shown in FIG. is there. Since the distortion of the wafer WAF is complicated, it is difficult to correct this by EGA.

  However, it is possible to obtain high alignment accuracy by measuring the shot shape of the layer to be matched in shot units and correcting the shot shape for each shot and performing exposure.

  In this embodiment, in order to achieve higher overlay accuracy, alignment marks and overlay inspection marks are arranged in the main body chip region by the above-described method, and these marks are used after rough alignment and EGA. Die-by-die alignment is performed in which position measurement is performed for each chip and shape correction is performed for each chip for exposure.

<About the second means for solving the second problem>
A method for arranging alignment marks will be described with reference to FIG. FIG. 7 is a schematic diagram for explaining an alignment mark arrangement method according to the present embodiment. Here, the alignment mark arranging method will be described, but the overlay inspection mark arranging method is also the same.

  Lattice points are provided at a first pitch in the main body chip region SC, and a lattice in the CMP dummy overlap region DAD between the CMP dummy placement region of the mating layer and the CMP dummy placement region of the processed layer exposed before the mating layer The alignment mark AM of the layer to be bonded is arranged at the point position. By arranging the plurality of alignment marks AM at the first pitch in the main body chip area SC, it becomes possible to obtain the position information in the main body chip area SC on average.

  The alignment mark AM is preferably measured by the same stage operation as the actual exposure. By doing so, it is possible to reduce misalignment due to variations between apparatus operations during position measurement and exposure.

  Since die-by-die alignment takes time to process, in order to shorten the processing time, a shot with a large residual component is extracted as a result of EGA performed before performing die-by-die alignment, and only a shot with a large residual component is described above. It is preferable to perform die-by-die alignment using the alignment mark AM. It is also effective as a countermeasure against throughput to perform die-by-die alignment according to the present embodiment only in a process that requires high overlay accuracy and perform exposure using a conventional alignment method in other processes.

  In the second means described above, alignment marks and overlay inspection marks are arranged at the lattice point positions. This is because the position information is obtained uniformly in the main body chip area. If the mark arrangement is such that the position information can be obtained uniformly, the alignment mark and overlay inspection mark need not necessarily be arranged at the lattice point position.

  If there is a pattern that requires superposition accuracy in the main body pattern, position information weighted on the main body pattern can be obtained by placing many alignment marks and overlay inspection marks near the main body pattern. become. For example, a plurality of first lattice points having a first pitch are provided in the vicinity of a pattern that does not require overlay accuracy, and a second pitch smaller than the first pitch is provided in the vicinity of a pattern that requires overlay accuracy. A plurality of second lattice points may be provided.

  In addition, among the position information obtained from alignment marks and overlay inspection marks, weighting the position information obtained from alignment marks and overlay inspection marks in the vicinity of the highly important body pattern makes the body pattern more important Information can be obtained.

  Hereinafter, specific means for solving the first and second problems described above will be described in the first to fourth embodiments.

(Embodiment 1)
A method for arranging alignment marks in the pattern data of the layer to be bonded according to the first embodiment will be described with reference to FIG. FIG. 8 is a schematic diagram for explaining a method of arranging alignment marks on the mask of the gate layer (matched layer) according to the first embodiment.

  The exposure layer described in FIG. 8 is a contact layer, the bonding layer is a gate layer, and the processing layer exposed before the bonding layer is an element isolation (STI) layer. The STI layer → Gate layer → The exposure is performed in the order of the Contact layer.

  In the pattern data of the Gate layer drawn on the mask MSKG and the pattern data of the STI layer drawn on the mask MSKS, a CMP dummy is arranged in an area without the main body pattern in the main body chip area.

  An example of the CMP dummy generation rule for the STI layer is shown below.

(A) The pattern is a groove pattern having a size of 1.5 μm × 0.5 μm. (B) A CMP dummy is placed in an area of 3.0 μm × 3.0 μm or more. (C) CMP is performed from a position 1.0 μm away from the main body pattern. Arrangement of dummy In addition, an example of a CMP dummy generation rule for the Gate layer is shown below.

(A) The pattern is a line pattern having a size of 0.3 μm × 1.7 μm. (B) A CMP dummy is arranged in an area of 3.0 μm × 3.0 μm or more. (C) CMP is performed from a position 1.0 μm away from the main body pattern. Place a dummy First Step First, the CMP dummy arrangement area DAG of the Gate layer is extracted from the pattern data of the mask MSKG, and the CMP dummy arrangement area DAS of the STI layer is extracted from the pattern data of the mask MSKS.

2. Second Step A CMP dummy overlap area DAD between the CMP dummy arrangement area DAG of the Gate layer and the CMP dummy arrangement area DAS of the STI layer is extracted.

3. Third Step Place the alignment mark of the Gate layer in the vicinity of the main body pattern that requires high overlay accuracy between the Contact layer and the Gate layer, and from the place where the CMP dummy placement area DAG, DAS overlaps the DAD. Decide where to go.

4). Fourth Step An alignment mark AMG is arranged on the Gate layer. For the alignment mark AMG, for example, a pattern having a size of 1.4 μm × 1.4 μm is used.

5. Fifth Step A CMP dummy DP is disposed in the CMP dummy region DAG of the Gate layer and the CMP dummy region DAS of the STI layer. For the CMP dummy DP disposed in the CMP dummy region DAG of the Gate layer, for example, a line pattern having a size of 0.3 μm × 1.7 μm is used. For the CMP dummy DP disposed in the CMP dummy area DAS of the STI layer, for example, a groove pattern having a size of 1.5 μm × 0.5 μm is used. For the Gate layer, the CMP dummy DP is not disposed in the range (mark area AG) of 2.0 μm × 2.0 μm centering on the alignment mark AMG. For the STI layer, the CMP dummy DP is not arranged in the 2.0 μm × 2.0 μm range (mark region AS) at the same position corresponding to the mark region AG of the Gate layer.

  Next, a method for arranging overlay inspection marks in the pattern data of the exposure layer and the pattern data of the layer to be matched according to the first embodiment will be described with reference to FIG. FIG. 9 is a schematic diagram for explaining a method of arranging overlay inspection marks on the mask of the contact layer (exposure layer) and the mask of the gate layer (matched layer) according to the first embodiment.

  The exposure layer described in FIG. 9 is a contact layer, the mating layer is a gate layer, and the processing layer exposed before the mating layer is an element isolation (STI) layer. STI layer → Gate layer → The exposure is performed in the order of the Contact layer.

  In the pattern data of the Gate layer drawn on the mask MSKG and the pattern data of the STI layer drawn on the mask MSKS, a CMP dummy is arranged in the area without the main body pattern in the main body chip area, but the mask dummy is drawn on the mask MSKS. The CMP dummy is not arranged in the pattern data of the contact layer.

1. First Step First, the CMP dummy arrangement area DAG of the Gate layer is extracted from the pattern data of the mask MSKG, and the CMP dummy arrangement area DAS of the STI layer is extracted from the pattern data of the mask MSKS.

  Next, a provisional CMP dummy generation rule is set in the Contact layer, and a provisional CMP dummy arrangement area DAC is set in the pattern data of the mask MSKC. An example of a provisional CMP dummy generation rule for the Contact layer is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. Place dummy Second Step A CMP dummy overlapping area DAD of the CMP dummy arrangement area DAC of the Contact layer, the CMP dummy arrangement area DAG of the Gate layer, and the CMP dummy arrangement area DAS of the STI layer is extracted.

3. Third Step In the contact layer and the gate layer, in the vicinity of the main body pattern that requires high overlay accuracy and the CMP dummy overlapping area DAD of the CMP dummy arrangement areas DAC, DAG, and DAS, The position where the overlay inspection mark and the overlay inspection mark of the Gate layer are arranged is determined.

4). Fourth Step The overlay inspection mark IMC is disposed on the Contact layer, and the overlay inspection mark IMG is disposed on the Gate layer. For example, a pattern having a size of 0.75 μm × 0.75 μm is used for the overlay inspection mark IMC disposed in the Contact layer, and for the overlay inspection mark IMG disposed in the Gate layer, for example, 1.4 μm × 1. A pattern with a size of 4 μm was used.

5. Fifth Step A CMP dummy DP is disposed in the CMP dummy region DAG of the Gate layer and the CMP dummy region DAS of the STI layer. For the CMP dummy DP disposed in the CMP dummy region DAG of the Gate layer, for example, a line pattern having a size of 0.3 μm × 1.7 μm is used. For the CMP dummy DP disposed in the CMP dummy area DAS of the STI layer, for example, a groove pattern having a size of 1.5 μm × 0.5 μm is used. For the Gate layer, the CMP dummy DP is not arranged in the range of 2.0 μm × 2.0 μm (inspection mark region BG) centering on the overlay inspection mark IMG. In addition, for the STI layer, the CMP dummy DP is not arranged in a 2.0 μm × 2.0 μm range (inspection mark region BS) at the same position corresponding to the inspection mark region BG of the Gate layer.

  The above-described alignment mark information and overlay inspection mark information are included in the pattern data, and reticles of the STI layer, the Gate layer, and the Contact layer are manufactured.

  Next, an example of a method for manufacturing a field effect transistor using the reticle according to the first embodiment will be described.

  A p-type silicon substrate is prepared, and after a silicon oxide film and a silicon nitride film are formed on the silicon substrate, a resist pattern is formed on the silicon nitride film using an STI layer reticle. Subsequently, the silicon nitride film, the silicon oxide film, and the silicon substrate are sequentially processed using the resist pattern as a mask to form an isolation groove in the silicon substrate. Subsequently, after removing the resist pattern, an element isolation portion is formed by embedding a silicon oxide film inside the isolation trench.

  Next, a gate oxide film is formed on the main surface of the silicon substrate, a polycrystalline silicon film having a thickness of, for example, about 200 nm is deposited on the gate oxide film, and then a gate layer reticle is used to form the gate oxide film on the polycrystalline silicon film. A resist pattern is formed on the substrate. Subsequently, the polycrystalline silicon film is processed using the resist pattern as a mask to form a gate electrode. Subsequently, after removing the resist pattern, n-type impurities are introduced into the silicon substrate on both sides of the gate electrode to form source / drain regions. Thereafter, a sidewall is formed on the side wall of the gate electrode, and a silicide film is formed on the upper surface of the gate electrode and the main surface of the silicon substrate.

  Next, after depositing a silicon oxide film having a thickness of, for example, about 850 nm by a CVD (Chemical Vapor Deposition) method, the upper surface of the silicon oxide film is planarized by a CMP method to form an interlayer insulating film.

  Next, alignment is performed with reference to the gate alignment mark arranged in the main body chip region, and a resist pattern is formed on the interlayer insulating film using a contact layer reticle. Subsequently, using the overlay inspection mark of the Gate layer in the main body chip region formed when the gate electrode is processed, and the overlay inspection mark of the Contact layer formed in the resist pattern by resist patterning of the Contact layer. Measure overlay deviation. The result of this measurement is fed back to the exposure parameter of the Contact layer in the next lot processing.

  Next, the interlayer insulating film is processed using the resist pattern as a mask to form a connection hole in the interlayer insulating film, and then the resist pattern is removed, and the main surface of the silicon substrate exposed at the bottom of the connection hole is washed to naturally The oxide film is removed.

  Next, a barrier metal film is formed by depositing a titanium (Ti) film and a titanium nitride (TiN) film by a collimation sputtering method. Subsequently, after depositing, for example, a tungsten (W) film having a thickness of about 600 nm on the interlayer insulating film including the inside of the connection hole, the tungsten (W) film other than the inside of the connection hole is polished and removed by a CMP method. By doing so, a plug is formed inside the connection hole. Thereafter, a first wiring layer electrically connected to the plug is formed. Through the above steps, the field effect transistor is substantially completed.

  As described above, according to the first embodiment, the gate layer and the contact layer are required to have high overlay accuracy, but the alignment mark and overlay inspection mark can be arranged in the vicinity of the main body pattern. By performing the exposure process using the alignment mark and the overlay inspection mark, it is possible to reduce the overlay deviation and realize high overlay accuracy.

(Embodiment 2)
A method for arranging alignment marks in the pattern data of the layer to be bonded according to the second embodiment will be described with reference to FIG. FIG. 10 is a schematic diagram for explaining a method of arranging alignment marks on the mask of the contact layer (matched layer) according to the second embodiment.

  The exposure layer described in FIG. 10 is the first wiring (M1) layer, the mating layer is a contact layer, and the processing layer exposed before the mating layer is a gate layer and an element isolation (STI) layer. The exposure is performed in the order of STI layer → Gate layer → Contact layer → M1 layer.

  In the pattern data of the Gate layer drawn on the mask MSKG and the pattern data of the STI layer drawn on the mask MSKS, a CMP dummy is arranged in the area without the main body pattern in the main body chip area, but the mask dummy is drawn on the mask MSKS. The CMP dummy is not arranged in the pattern data of the contact layer.

  An example of the CMP dummy generation rule for the STI layer is shown below.

(A) The pattern is a groove pattern having a size of 1.5 μm × 0.5 μm. (B) A CMP dummy is placed in an area of 3.0 μm × 3.0 μm or more. (C) CMP is performed from a position 1.0 μm away from the main body pattern. Arrangement of dummy In addition, an example of a CMP dummy generation rule for the Gate layer is shown below.

(A) The pattern is a line pattern having a size of 0.3 μm × 1.7 μm. (B) A CMP dummy is arranged in an area of 3.0 μm × 3.0 μm or more. (C) CMP is performed from a position 1.0 μm away from the main body pattern. Place a dummy First Step First, the CMP dummy arrangement area DAG of the Gate layer is extracted from the pattern data of the mask MSKG, and the CMP dummy arrangement area DAS of the STI layer is extracted from the pattern data of the mask MSKS.

  Next, a provisional CMP dummy generation rule is set in the Contact layer, and a provisional CMP dummy arrangement area DAC is set in the pattern data of the mask MSKC. An example of a provisional CMP dummy generation rule for the Contact layer is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. Place dummy Second Step A CMP dummy overlapping area DAD of the CMP dummy arrangement area DAC of the Contact layer, the CMP dummy arrangement area DAG of the Gate layer, and the CMP dummy arrangement area DAS of the STI layer is extracted.

3. Third Step In the vicinity of the main body pattern that requires high overlay accuracy in the M1 layer and the Contact layer, and in the CMP dummy overlapping area DAD of the CMP dummy arrangement areas DAC, DAG, and DAS, The position where the alignment mark is arranged is determined.

4). Fourth Step An alignment mark AMC is placed on the contact layer. For the alignment mark AMC, for example, a pattern having a size of 1.4 μm × 1.4 μm was used.

5. Fifth Step A CMP dummy DP is disposed in the CMP dummy region DAG of the Gate layer and the CMP dummy region DAS of the STI layer. For the CMP dummy DP disposed in the CMP dummy region DAG of the Gate layer, for example, a line pattern having a size of 0.3 μm × 1.7 μm is used. For the CMP dummy DP disposed in the CMP dummy area DAS of the STI layer, for example, a groove pattern having a size of 1.5 μm × 0.5 μm is used. For the Gate layer and the STI layer, a CMP dummy DP is disposed in a 2.0 μm × 2.0 μm range (mark regions AG, AS) corresponding to the region where the alignment mark AMC of the Contact layer is disposed. Do not.

  Next, a method for arranging overlay inspection marks in the pattern data of the exposure layer and the pattern data of the layer to be matched according to the second embodiment will be described with reference to FIGS. 11A and 11B. FIGS. 11A and 11B are schematic diagrams for explaining a method of arranging overlay inspection marks on the mask of the first wiring layer (exposure layer) and the mask of the contact layer (matched layer) according to the second embodiment.

  The exposure layer described in FIG. 11 is the first wiring (M1) layer, the mating layer is a contact layer, and the processing layer exposed before the mating layer is a gate layer and an element isolation (STI) layer. The exposure is performed in the order of STI layer → Gate layer → Contact layer → M1 layer.

  The pattern data of the M1 layer drawn on the mask MSKM1, the pattern data of the Gate layer drawn on the mask MSKG, and the pattern data of the STI layer drawn on the mask MSKS are areas without a main body pattern in the main body chip area, respectively. However, no CMP dummy is arranged in the pattern data of the Contact layer drawn on the mask MSKC.

  An example of a CMP dummy generation rule for the M1 layer is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. Place a dummy First Step First, the CMP dummy arrangement area DAM1 of the M1 layer is extracted from the pattern data of the mask MSKM1, the CMP dummy arrangement area DAG of the Gate layer is extracted from the pattern data of the mask MSKG, and the STI layer of the mask MSKS pattern data is extracted. The CMP dummy arrangement area DAS is extracted.

  Next, the provisional CMP dummy generation rule is set in the Contact layer as described above, and the provisional CMP dummy arrangement area DAC is set in the pattern data of the mask MSKC.

2. Second Step Extract CMP dummy overlapping area DAD of CMP dummy arrangement area DAM1 of M1 layer, CMP dummy arrangement area DAC of Contact layer, CMP dummy arrangement area DAG of Gate layer, and CMP dummy arrangement area DAS of STI layer To do.

3. Third Step M1 is located in the vicinity of the main body pattern that requires high overlay accuracy between the M1 layer and the Gate layer, and from among the CMP dummy overlapping areas DAD of the CMP dummy arrangement areas DAM1, DAC, DAG, and DAS, M1 The position where the layer overlay alignment inspection mark and the contact layer overlay inspection mark are arranged is determined.

4). Fourth Step The overlay inspection mark IMM1 is disposed on the M1 layer, and the overlay inspection mark IMC is disposed on the Contact layer. For example, a pattern having a size of 0.75 μm × 0.75 μm is used for the overlay inspection mark IMM1 disposed in the M1 layer, and for the overlay inspection mark IMC disposed in the Contact layer, for example, 1.4 μm × 1. A pattern with a size of 4 μm is used.

5. Fifth Step A CMP dummy DP is arranged in the CMP dummy area DAM1 of the M1 layer, the CMP dummy area DAG of the Gate layer, and the CMP dummy area DAS of the STI layer. A hole pattern having a size of 0.4 μm × 0.4 μm is used for the CMP dummy DP disposed in the CMP dummy region DAM1 of the M1 layer. For the CMP dummy DP disposed in the CMP dummy region DAG of the Gate layer, for example, a line pattern having a size of 0.3 μm × 1.7 μm is used. For the CMP dummy DP disposed in the CMP dummy area DAS of the STI layer, for example, a groove pattern having a size of 1.5 μm × 0.5 μm is used. For the M1 layer, the CMP dummy DP is not arranged in the range of 2.0 μm × 2.0 μm (inspection mark region BM1) centering on the overlay inspection mark IMM1. For the Gate layer and the STI layer, the CMP dummy DP is not arranged in the 2.0 μm × 2.0 μm range (inspection mark regions BG, BS) corresponding to the inspection mark region BM1 of the M1 layer. To do.

  The alignment mark information and overlay inspection mark information described above are included in the pattern data, and the STI layer, Gate layer, Contact layer, and M1 layer reticles are manufactured.

  Next, an example of a method for manufacturing a field effect transistor using the reticle according to the second embodiment will be described.

  A p-type silicon substrate is prepared, and after a silicon oxide film and a silicon nitride film are formed on the silicon substrate, a resist pattern is formed on the silicon nitride film using an STI layer reticle. Subsequently, the silicon nitride film, the silicon oxide film, and the silicon substrate are sequentially processed using the resist pattern as a mask to form an isolation groove in the silicon substrate. Subsequently, after removing the resist pattern, an element isolation portion is formed by embedding a silicon oxide film inside the isolation trench.

  Next, a gate oxide film is formed on the main surface of the silicon substrate, a polycrystalline silicon film having a thickness of, for example, about 200 nm is deposited on the gate oxide film, and then a gate layer reticle is used to form the gate oxide film on the polycrystalline silicon film. A resist pattern is formed on the substrate. Subsequently, the polycrystalline silicon film is processed using the resist pattern as a mask to form a gate electrode. Subsequently, after removing the resist pattern, n-type impurities are introduced into the silicon substrate on both sides of the gate electrode to form source / drain regions. Thereafter, a sidewall is formed on the side wall of the gate electrode, and a silicide film is formed on the upper surface of the gate electrode and the main surface of the silicon substrate.

  Next, after a silicon oxide film having a thickness of, for example, about 850 nm is deposited by CVD, the upper surface of the silicon oxide film is planarized by CMP to form a first interlayer insulating film.

  Next, a resist pattern is formed on the second interlayer insulating film using a contact layer reticle. Subsequently, the first interlayer insulating film is processed using the resist pattern as a mask to form a connection hole in the first interlayer insulating film. Then, the resist pattern is removed, and the main surface of the silicon substrate exposed at the bottom of the connection hole is removed. Clean and remove the native oxide film.

  Next, a barrier metal film is formed by depositing a titanium (Ti) film and a titanium nitride (TiN) film by a collimation sputtering method. Subsequently, after depositing, for example, a tungsten (W) film having a thickness of about 600 nm on the first interlayer insulating film including the inside of the connection hole, the tungsten (W) film other than the inside of the connection hole is polished by a CMP method. By removing them, a plug is formed inside the connection hole.

  Next, after a second interlayer insulating film is formed on the first interlayer insulating film, alignment is performed with reference to the contact alignment mark arranged in the main body chip region, and the second interlayer insulating is performed using the M1 layer reticle. A resist pattern is formed on the film. Subsequently, using the overlay inspection mark of the Contact layer in the main body chip region formed when the connection hole is processed, and the overlay inspection mark of the M1 layer formed in the resist pattern by resist patterning of the M1 layer. Measure overlay deviation. The result of this measurement is fed back to the exposure parameter of the M1 layer in the next lot processing.

  Next, the second interlayer insulating film is processed using the resist pattern as a mask to form a wiring groove in the second interlayer insulating film. Subsequently, after removing the resist pattern, a barrier conductor film made of a tantalum (Ta) film or a titanium (Ti) film is formed by sputtering, and copper (Cu) is mainly used so as to cover the barrier conductor film. A seed layer made of a conductor film is formed by a sputtering method. Thereafter, a conductor film for wiring mainly composed of copper (Cu) is formed so as to fill the wiring groove on the seed layer by electrolytic plating. Subsequently, the barrier conductor film and the conductor film other than the inside of the wiring groove are polished and removed by CMP to form a first wiring layer inside the wiring groove. Through the above steps, the field effect transistor is substantially completed.

  As described above, according to the second embodiment, the M1 layer and the Contact layer are required to have high overlay accuracy, but the alignment mark and overlay inspection mark can be arranged in the vicinity of the main body pattern. By performing the exposure process using the alignment mark and the overlay inspection mark, it is possible to reduce the overlay deviation and realize high overlay accuracy.

(Embodiment 3)
In the third embodiment, for example, after the first via hole layer (V1 layer) is formed on the interlayer insulating film by using the method for manufacturing a semiconductor device disclosed in Japanese Patent Laid-Open No. 2-241919 by Kashiwagashi et al. An opaque film is formed on the interlayer insulating film. After the opaque film is formed, the alignment marks of the M1 layer, the Contact layer, the Gate layer, and the STI layer are not visible by the opaque film. Therefore, it is not necessary to change the pattern layout of the M1 layer, Contact layer, Gate layer, and STI layer with respect to the alignment mark arrangement of the V1 layer and the M1 layer.

  A method for arranging alignment marks in the pattern data of the layer to be bonded according to the third embodiment will be described with reference to FIGS. In the third embodiment, the pattern data of the first via hole (V1) layer connecting the first wiring (M1) layer and the second wiring (M2) layer, and the pattern of the second wiring (M2) layer An alignment mark is placed on each data. FIG. 12 is a schematic diagram for explaining a method of arranging alignment marks on the mask of the first via hole layer (matched layer) according to the third embodiment. FIG. 13 is a schematic diagram for explaining a method of arranging alignment marks on the mask of the second wiring layer (matched layer) according to the third embodiment.

  The mating layer described in FIG. 12 is the first via hole (V1) layer, the mating layer described in FIG. 13 is the second wiring (M2) layer, and the processed layer exposed before the mating layer is the first layer. 1 via hole (V1) layer, which is exposed in the order of M1 layer → V1 layer → M2 layer.

  In the pattern data of the V1 layer drawn on the mask MSKV1 and the pattern data of the M2 layer drawn on the mask MSKM2, a CMP dummy is arranged in a region without the main body pattern in the main body chip region.

  An example of CMP dummy generation rules for the V1 layer and the M2 layer is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. Arrangement of Dummy First, as shown in FIG. 12, alignment marks are arranged on the pattern data of the V1 layer.

1. First Step First, the CMP dummy arrangement area DAV1 of the V1 layer is extracted from the pattern data of the mask MSKV1.

2. Second Step In the vicinity of the main body pattern that requires high overlay accuracy between the M2 layer and the V1 layer, the position where the alignment mark of the V1 layer is arranged is determined from the location that is the CMP dummy arrangement area DAV1.

3. Third Step An alignment mark AMV1 is placed on the V1 layer. A pattern having a size of 1.4 μm × 1.4 μm is used for the alignment mark AMV1.

4). Fourth Step A CMP dummy DP is arranged in the CMP dummy area DAV1 of the V1 layer. For the CMP dummy DP disposed in the CMP dummy area DAV1 of the V1 layer, for example, a hole pattern having a size of 0.4 μm × 0.4 μm is used. The CMP dummy DP is not arranged in the range of 2.0 μm × 2.0 μm centering on the alignment mark AMV1.

  Next, as shown in FIG. 13, alignment marks are arranged on the pattern data of the M2 layer.

1. First Step First, the CMP dummy arrangement area DAM2 of the M2 layer is extracted from the pattern data of the mask MSKM2, and the CMP dummy arrangement area DAV1 of the V1 layer is extracted from the pattern data of the mask MSKV1.

2. Second Step A CMP dummy overlapping area DAD between the CMP dummy arrangement area DAM2 of the M2 layer and the CMP dummy arrangement area DAV1 of the V1 layer is extracted.

3. Third step: An alignment mark for the M2 layer from the vicinity of the main body pattern that requires high overlay accuracy between the V1 layer and the M2 layer and the CMP dummy overlapping area DAD of the CMP dummy arrangement areas DAM2 and DAV1. Decide where to place.

4). Fourth Step An alignment mark AMM2 is placed on the M2 layer. For the alignment mark AMM2, for example, a pattern having a size of 1.4 μm × 1.4 μm is used.

5. Fifth Step A CMP dummy DP is arranged in the CMP dummy area DAM2 of the M2 layer and the CMP dummy area DAV1 of the V1 layer. A hole pattern having a size of 0.4 μm × 0.4 μm, for example, is used for the CMP dummy DP disposed in the CMP dummy area DAM2 of the M2 layer and the CMP dummy DP disposed in the CMP dummy area DAV1 of the V1 layer. In the M2 layer, the CMP dummy DP is not disposed in the range of 2.0 μm × 2.0 μm (inspection mark area AM2) centering on the alignment mark AMM2. In addition, for the V1 layer, the CMP dummy DP is not arranged in the 2.0 μm × 2.0 μm range (inspection mark area AV1) at the same position corresponding to the inspection mark area AM2 of the M2 layer.

  Next, a method for arranging overlay inspection marks in the pattern data of the exposure layer and the pattern data of the layer to be matched according to the third embodiment will be described with reference to FIGS. In the third embodiment, the overlay inspection mark between the second wiring (M2) layer and the first via hole (V1) layer, and the second via hole (V2) layer and the second wiring (M2) layer Each overlay mark is arranged in the pattern data. FIG. 14 is a schematic diagram for explaining a method for arranging overlay inspection marks on the mask of the second wiring layer (exposure layer) and the mask of the first via hole layer (matched layer) according to the third embodiment. . FIG. 15 is a schematic diagram for explaining a method of placing overlay inspection marks on the mask of the second via hole layer (exposure layer) and the mask of the second wiring layer (matched layer) according to the third embodiment. .

  The exposure layer described in FIG. 14 is the second wiring (M2) layer, the layer to be bonded is the first via hole (V1) layer, and the exposure layer described in FIG. 15 is the second via hole (V2) layer, The mating layer is the second wiring (M2) layer, and the processed layer exposed before the mating layer is the first via hole (V1), which is exposed in the order of M1 layer → V1 layer → M2 layer → V2 layer. .

  The pattern data of the V1 layer drawn on the mask MSKV1, the pattern data of the M2 layer drawn on the mask MSKM2, and the pattern data of the V2 layer drawn on the mask MSKV2 are areas without body patterns in the body chip area, respectively. A CMP dummy is disposed on the substrate.

  An example of the V2 layer CMP dummy generation rule is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. Arrangement of Dummy First, as shown in FIG. 14, an overlay inspection mark is arranged in each pattern data of the M2 layer and the V1 layer.

1. First Step First, the CMP dummy arrangement area DAM2 of the M2 layer is extracted from the pattern data of the mask MSKM2, and the CMP dummy arrangement area DAV1 of the V1 layer is extracted from the pattern data of the mask MSKV1.

2. Second Step A CMP dummy overlapping area DAD between the CMP dummy arrangement area DAM2 of the M2 layer and the CMP dummy arrangement area DAV1 of the V1 layer is extracted.

3. Third Step The M2 layer and the V1 layer are located in the vicinity of the main body pattern that requires high overlay accuracy between the M2 layer and the V1 layer and from the CMP dummy overlapping area DAD of the CMP dummy arrangement areas DAM2 and DAV1. The position for arranging the overlay inspection mark is determined.

4). Fourth Step The overlay inspection mark IMM2 is disposed on the M2 layer, and the overlay inspection mark position IMV1 is disposed on the V1 layer. For example, a pattern having a size of 0.75 μm × 0.75 μm is used for the overlay inspection mark IMM2 arranged in the M2 layer, and 1.4 μm × 1 is used for the overlay inspection mark IMV1 arranged in the V1 layer. A pattern with a size of 4 μm is used.

5. Fifth Step A CMP dummy DP is arranged in the CMP dummy area DAM2 of the M2 layer and the CMP dummy area DAV1 of the V1 layer. A hole pattern having a size of 0.4 μm × 0.4 μm, for example, is used for the CMP dummy DP disposed in the CMP dummy area DAM2 of the M2 layer and the CMP dummy DP disposed in the CMP dummy area DAV1 of the V1 layer. For the M2 layer and the V1 layer, the CMP dummy DP is not arranged in the range of 2.0 μm × 2.0 μm (inspection mark regions BM2, BV1) centering on the overlay inspection marks IMM2, IMV1. .

  Next, as shown in FIG. 15, overlay inspection marks are arranged in the pattern data of the V2 layer and the M2 layer.

1. First Step First, the CMP dummy arrangement area DAV2 of the V2 layer is extracted from the pattern data of the mask MSKV2, the CMP dummy arrangement area DAM2 of the M2 layer is extracted from the pattern data of the mask MSKM2, and the V1 layer is extracted from the pattern data of the mask MSKV1. The CMP dummy arrangement area DAV1 is extracted.

2. Second Step A CMP dummy overlapping area DAD of the CMP dummy arrangement area DAM2 of the V2 layer, the CMP dummy arrangement area DAM2 of the M2 layer, and the CMP dummy arrangement area DAV1 of the V1 layer is extracted.

3. Third Step In the vicinity of the main body pattern that requires high overlay accuracy in the V2 layer and the M2 layer, and in the CMP dummy overlapping area DAD of the CMP dummy arrangement areas DAV2, DAM2, and DAV1, the V2 layer and The position of each overlay inspection mark on the M2 layer is determined.

4). Fourth Step The overlay inspection mark IMV2 is disposed on the V2 layer, and the overlay inspection mark position IMM2 is disposed on the M2 layer. A pattern having a size of, for example, 0.75 μm × 0.75 μm is used for the overlay inspection mark IMV2 arranged in the V2 layer, and for example, 1.4 μm × 1 is used for the overlay inspection mark IMM2 arranged in the M2 layer. A pattern with a size of 4 μm is used.

5. Fifth Step A CMP dummy DP is arranged in the CMP dummy area DAV2 in the V2 layer, the CMP dummy area DAM2 in the M2 layer, and the CMP dummy area DAV1 in the V1 layer. The CMP dummy DP disposed in the CMP dummy area DAV2 in the V2 layer, the CMP dummy DP disposed in the CMP dummy area DAM2 in the M2 layer, and the CMP dummy DP disposed in the CMP dummy area DAV1 in the V1 layer include, for example,. A hole pattern having a size of 4 μm × 0.4 μm is used. For the V2 layer and the M2 layer, the CMP dummy DP is not arranged in the range of 2.0 μm × 2.0 μm (inspection mark regions BV2, BM2) centering on the overlay inspection marks IMV2, IMM2. . For the V1 layer, the CMP dummy DP is not disposed in the 2.0 μm × 2.0 μm range (inspection mark region BV1) at the same position corresponding to the inspection mark regions BV2 and BM2 of the V2 layer and the M2 layer. To do.

  The above-described alignment mark information and overlay inspection mark information are included in the pattern data, and reticles for the V1, M1, and V2 layers are manufactured.

  Next, an example of a method for manufacturing a field effect transistor using the reticle according to the third embodiment will be described with reference to FIGS. 16 to 28 are cross-sectional views of main parts of the semiconductor device showing the method for manufacturing the semiconductor device (field effect transistor) according to the third embodiment.

  As shown in FIG. 16, a p-type silicon substrate SUB is prepared, a silicon oxide film and a silicon nitride film are formed on the silicon substrate SUB, and then a resist pattern is formed on the silicon nitride film using an STI layer reticle. To do. Subsequently, the silicon nitride film, the silicon oxide film, and the silicon substrate SUB are sequentially processed using the resist pattern as a mask to form separation grooves in the silicon substrate SUB. Subsequently, after removing the resist pattern, an element isolation portion STI is formed by embedding a silicon oxide film inside the isolation trench. Thereafter, the exposed silicon nitride film and silicon oxide film on the silicon substrate SUB are removed.

  Next, a gate oxide film GI is formed on the main surface of the silicon substrate SUB, a polycrystalline silicon film having a thickness of, for example, about 200 nm is deposited on the gate oxide film GI, and then polycrystalline using a gate layer reticle. A resist pattern is formed on the silicon film. Subsequently, the polycrystalline silicon film is processed using the resist pattern as a mask to form the gate electrode GE.

  Next, as shown in FIG. 17, after removing the resist pattern, n-type impurities are introduced into the silicon substrate SUB on both sides of the gate electrode GE to form source / drain regions SD. Subsequently, after forming a sidewall SW on the side wall of the gate electrode GE, an n-type impurity is introduced into the silicon substrate SUB on both sides of the sidewall SW.

  Next, as shown in FIG. 18, a silicide film SI is formed on the upper surface of the gate electrode GE and the exposed main surface of the silicon substrate SUB.

  Next, as shown in FIG. 19, a liner silicon nitride film SN is deposited by the CVD method. Subsequently, after depositing a silicon oxide film having a thickness of, for example, about 850 nm, the upper surface of the silicon oxide film is planarized by CMP to form a first interlayer insulating film IS1.

  Next, as shown in FIG. 20, a resist pattern is formed on the first interlayer insulating film IS1 using a contact layer reticle. Subsequently, the first interlayer insulating film IS1 and the liner silicon nitride film SN are processed using the resist pattern as a mask to form connection holes CNT1 in the first interlayer insulating film IS1 and the liner silicon nitride film SN, and then the resist pattern is removed. Then, the main surface of the silicon substrate SUB exposed at the bottom of the connection hole CNT1 is washed to remove the natural oxide film.

  Next, a titanium (Ti) film and a titanium nitride (TiN) film are deposited by collimation sputtering to form a barrier metal film (not shown). Subsequently, a tungsten (W) film having a thickness of, for example, about 600 nm is deposited on the first interlayer insulating film IS1 including the inside of the connection hole CNT1, and then a tungsten (W) film and an aryl metal other than the inside of the connection hole CNT1. The film is polished and removed by the CMP method to form a plug PLG inside the connection hole CNT1.

  Next, as shown in FIG. 21, a first wiring layer is formed by a single damascene method.

  First, a second interlayer insulating film IS2 is formed on the first interlayer insulating film IS1, and then a resist pattern is formed on the second interlayer insulating film IS2 using an M1 layer reticle.

  Next, the second interlayer insulating film IS2 is processed using the resist pattern as a mask to form a wiring trench MT1 in the second interlayer insulating film IS2. Subsequently, after removing the resist pattern, a barrier conductor film made of a tantalum (Ta) film or a titanium (Ti) film is formed by sputtering, and copper (Cu) is mainly used so as to cover the barrier conductor film. A seed layer made of a conductor film is formed by a sputtering method. Thereafter, a conductor film for wiring mainly composed of copper (Cu) is formed by embedding the wiring groove MT1 on the seed layer by electrolytic plating. Subsequently, the barrier conductor film and the conductor film other than the inside of the wiring trench MT1 are polished and removed by CMP to form the first wiring layer M1 inside the wiring trench MT1.

  Next, as shown in FIGS. 22 to 26, a second wiring layer is formed by a dual damascene method.

  First, as shown in FIG. 22, a third interlayer insulating film IS3 is formed on the second interlayer insulating film IS2 and the first wiring layer M1.

  Next, a resist pattern is formed on the third interlayer insulating film IS3 using a V1 layer reticle.

  Next, as shown in FIG. 23, the third interlayer insulating film IS3 is processed using the resist pattern as a mask, and the first via holes V1 and V1 are formed in the main body chip region so as not to penetrate the third interlayer insulating film IS3. A layer alignment mark AMV1 is formed.

  Next, as shown in FIG. 24, after removing the resist pattern, an opaque film NT is formed on the third interlayer insulating film IS3 including the inner wall of the first via hole V1 and the alignment mark AMV1 of the V1 layer. Since the first via hole V1 includes a step including the alignment mark AMV1 of the V1 layer, the shape of the first via hole V1 can be detected. However, the pattern below the first wiring layer M1 cannot be seen by the opaque film NT.

  Next, as shown in FIG. 25, the alignment mark AMV1 in the first via hole V1 and the V1 layer is filled with a via fill material BF, for example, by spin coating, and then the alignment of the V1 layer disposed in the main body chip region is performed. Alignment is performed with reference to the mark AMV1, and a resist pattern RP is formed on the opaque film NT using an M2 layer reticle.

  Next, the first via hole V1 and the alignment mark AMV1 of the V1 layer were formed on the resist pattern RP by the overlay inspection mark of the V1 layer in the main body chip region and the resist patterning of the M2 layer. The overlay deviation is measured using the overlay inspection mark of the M2 layer. The result of this measurement is fed back to the exposure parameter of the M2 layer in the next lot processing.

  Next, as shown in FIG. 26, the opaque film NT, the via fill material BF, and the third interlayer insulating film IS3 are processed using the resist pattern RP as a mask, and the wiring trench MT2 and the connection hole CNT2 are formed in the third interlayer insulating film IS3. And form. The connection hole CNT2 is formed at a position corresponding to the position where the first via hole V1 described above is formed in plan view, one end of the connection hole CNT2 is connected to a part of the wiring trench MT2, and the other end is the first wiring layer. Connected to a part of M1. Further, an alignment mark AMM2 of the M2 layer is formed in the third interlayer insulating film IS3 in the main body chip region.

  Next, after removing the resist pattern, a barrier conductor film made of a tantalum (Ta) film or a titanium (Ti) film is formed by sputtering, and copper (Cu) is mainly used so as to cover the barrier conductor film. A seed layer made of a conductor film is formed by a sputtering method. Thereafter, a conductor film mainly composed of copper (Cu) is formed so as to bury the wiring trench MT2 and the connection hole CNT2 on the seed layer by electrolytic plating. Subsequently, the second conductor layer M2 is formed inside the wiring groove MT2 by polishing and removing the barrier conductor film and the conductor film other than the inside of the wiring groove MT2 and the connection hole CNT2 by the CMP method. A connection member C2 formed integrally with the second wiring layer M2 is formed inside the CNT2.

  Next, as shown in FIGS. 27 and 28, a third wiring layer is formed by a dual damascene method.

  First, as shown in FIG. 27, a fourth interlayer insulating film IS4 is formed on the opaque film NT and the second wiring layer M2.

  Next, alignment is performed on the basis of the alignment mark AMM2 of the M2 layer disposed in the main body chip region, and a resist pattern is formed on the fourth interlayer insulating film IS4 using a reticle of the V2 layer.

  Next, the overlay inspection mark of the M2 layer in the main body chip region formed when the alignment mark AMM2 of the wiring trench MT2 and the M2 layer is processed, and the V2 layer formed in the resist pattern by resist patterning of the V2 layer The overlay deviation is measured using the overlay inspection mark. The result of this measurement is fed back to the exposure parameter of the V2 layer in the next lot processing.

  Next, the fourth interlayer insulating film IS4 is processed using the resist pattern as a mask to form the second via hole V2 and the alignment mark AMV2 of the V2 layer in the main body chip region so as not to penetrate the fourth interlayer insulating film IS4. To do.

  Next, after removing the resist pattern, alignment is performed with reference to the alignment mark AMV2 of the V2 layer disposed in the main body chip region, and the resist pattern is formed on the fourth interlayer insulating film IS4 using the M3 layer reticle. Form.

  Next, the overlay inspection mark of the V2 layer in the main body chip region formed when the second via hole V2 and the alignment mark AMV2 of the V2 layer are processed, and M3 formed in the resist pattern by resist patterning of the M3 layer The overlay deviation is measured using the overlay inspection mark of the layer. The result of this measurement is fed back to the exposure parameter of the M3 layer in the next lot processing.

  Next, as shown in FIG. 28, the fourth interlayer insulating film IS4 is processed using the resist pattern as a mask to form wiring trenches MT3 and connection holes CNT3 in the fourth interlayer insulating film IS4. The connection hole CNT3 is formed at a position corresponding to the position where the second via hole V2 described above is formed in plan view, one end of the connection hole CNT3 is connected to a part of the wiring trench MT3, and the other end is the second wiring layer. Connected to part of M2.

  Next, after removing the resist pattern, a barrier conductor film made of a tantalum (Ta) film or a titanium (Ti) film is formed by sputtering, and copper (Cu) is mainly used so as to cover the barrier conductor film. A seed layer made of a conductor film is formed by a sputtering method. Thereafter, a conductor film mainly composed of copper (Cu) is formed so as to bury the wiring trench MT3 and the connection hole CNT3 on the seed layer by electrolytic plating. Subsequently, the third conductor layer M3 is formed inside the wiring groove MT3 by polishing and removing the barrier conductor film and the conductor film other than the inside of the wiring groove MT3 and the connection hole CNT3 by the CMP method. A connection member C3 formed integrally with the third wiring layer M3 is formed inside the CNT3. Through the above steps, the field effect transistor is substantially completed.

  As described above, according to the third embodiment, the M2 layer and the V1 layer, and the V2 layer and the M2 layer are required to have high overlay accuracy, but the alignment mark and overlay inspection mark are provided in the vicinity of the main body pattern. Therefore, by performing exposure processing using the alignment mark and the overlay inspection mark, it is possible to reduce overlay deviation and to achieve high overlay accuracy.

(Embodiment 4)
A method for arranging alignment marks in the pattern data of the layer to be bonded according to the fourth embodiment will be described.

  The exposure layer is a contact layer, the mating layer is a gate layer, and the processing layer exposed before the mating layer is an element isolation (STI) layer, in the order of STI layer → Gate layer → Contact layer. Exposed.

  In the pattern data of the Gate layer drawn on the mask of the Gate layer and the pattern data of the STI layer drawn on the mask of the STI layer, a CMP dummy is arranged in a region without the main body pattern in the main body chip region.

  An example of the CMP dummy generation rule for the STI layer is shown below.

(A) The pattern is a groove pattern having a size of 1.5 μm × 0.5 μm. (B) A CMP dummy is placed in an area of 3.0 μm × 3.0 μm or more. (C) CMP is performed from a position 1.0 μm away from the main body pattern. Arrangement of dummy In addition, an example of a CMP dummy generation rule for the Gate layer is shown below.

(A) The pattern is a line pattern having a size of 0.3 μm × 1.7 μm. (B) A CMP dummy is arranged in an area of 3.0 μm × 3.0 μm or more. (C) CMP is performed from a position 1.0 μm away from the main body pattern. Place a dummy First Step First, a CMP dummy placement region of the Gate layer is extracted from the pattern data of the Gate layer mask, and a CMP dummy placement region of the STI layer is extracted from the pattern data of the STI layer mask.

2. Second Step A CMP dummy overlap area between the CMP dummy arrangement area of the Gate layer and the CMP dummy arrangement area of the STI layer is extracted.

3. Third Step The main body chip region is provided with lattice points at a first pitch, for example, at an interval of 3,000 μm (wafer conversion).

4). Fourth Step Alignment marks are arranged at lattice point positions within the CMP dummy overlap region. For the alignment mark, for example, a pattern having a size of 1.4 μm × 1.4 μm is used.

5. Fifth Step A CMP dummy is disposed in the CMP dummy region of the Gate layer and the CMP dummy region of the STI layer. For the CMP dummy disposed in the CMP dummy region of the Gate layer, for example, a line pattern having a size of 0.3 μm × 1.7 μm is used. For the CMP dummy disposed in the CMP dummy region of the STI layer, for example, a groove pattern having a size of 1.5 μm × 0.5 μm is used. For the Gate layer, no CMP dummy is arranged in the range of 2.0 μm × 2.0 μm centered on the alignment mark. For the STI layer, the CMP dummy is not disposed within the range of 2.0 μm × 2.0 μm at the same position corresponding to the region of the Gate layer where the CMP dummy is not disposed.

  Next, a method for arranging overlay inspection marks in the pattern data of the exposure layer and the pattern data of the layer to be matched according to the fourth embodiment will be described.

  The exposure layer is a contact layer, the mating layer is a gate layer, and the processing layer exposed before the mating layer is an element isolation (STI) layer, in the order of STI layer → Gate layer → Contact layer. Exposed.

  In the pattern data of the Gate layer drawn on the mask of the Gate layer and the pattern data of the STI layer drawn on the mask of the STI layer, a CMP dummy is arranged in a region without the main body pattern in the main body chip region. The CMP dummy is not arranged in the pattern data of the contact layer drawn on the contact layer mask.

1. First Step First, a CMP dummy placement region of the Gate layer is extracted from the pattern data of the Gate layer mask, and a CMP dummy placement region of the STI layer is extracted from the pattern data of the STI layer mask.

  Next, a provisional CMP dummy generation rule is set in the Contact layer, and a provisional CMP dummy arrangement area is set in the pattern data of the Contact layer mask. An example of a provisional CMP dummy generation rule for the Contact layer is shown below.

(A) The pattern is a 0.4 μm × 0.4 μm hole pattern. (B) A CMP dummy is placed in an area of 2.0 μm × 2.0 μm or more. (C) CMP is performed from a position 0.8 μm away from the main body pattern. Place dummy Second Step Next, a CMP dummy overlapping area is extracted from the CMP dummy arrangement area of the Contact layer, the CMP dummy arrangement area of the Gate layer, and the CMP dummy arrangement area of the STI layer.

3. Third Step The main body chip region is provided with lattice points at a first pitch, for example, at an interval of 3,000 μm (wafer conversion).

4). Fourth Step An overlay inspection mark is arranged at a lattice point position in the CMP dummy overlap region. For example, a pattern having a size of 0.75 μm × 0.75 μm is used for the overlay inspection mark disposed in the contact layer, and for example, 1.4 μm × 1.4 μm is employed for the overlay inspection mark disposed in the Gate layer. Use a pattern of size.

5. Fifth Step A CMP dummy is disposed in the CMP dummy region of the Gate layer and the CMP dummy region of the STI layer. For the CMP dummy disposed in the CMP dummy region of the Gate layer, for example, a line pattern having a size of 0.3 μm × 1.7 μm is used. For the CMP dummy disposed in the CMP dummy region of the STI layer, for example, a groove pattern having a size of 1.5 μm × 0.5 μm is used. For the Gate layer, no CMP dummy is arranged within a range of 2.0 μm × 2.0 μm centered on the overlay inspection mark. For the STI layer, the CMP dummy is not disposed within the range of 2.0 μm × 2.0 μm at the same position corresponding to the region of the Gate layer where the CMP dummy is not disposed.

  The above-described alignment mark information and overlay inspection mark information are included in the pattern data, and reticles of the STI layer, the Gate layer, and the Contact layer are manufactured.

  Next, an example of a method for manufacturing a field effect transistor using the reticle according to the fourth embodiment will be described.

  A p-type silicon substrate is prepared, and after a silicon oxide film and a silicon nitride film are formed on the silicon substrate, a resist pattern is formed on the silicon nitride film using an STI layer reticle. Subsequently, the silicon nitride film, the silicon oxide film, and the silicon substrate are sequentially processed using the resist pattern as a mask to form an isolation groove in the silicon substrate. Subsequently, after removing the resist pattern, an element isolation portion is formed by embedding a silicon oxide film inside the isolation trench.

  Next, a gate oxide film is formed on the main surface of the silicon substrate, a polycrystalline silicon film having a thickness of, for example, about 200 nm is deposited on the gate oxide film, and then a gate layer reticle is used to form the gate oxide film on the polycrystalline silicon film. A resist pattern is formed on the substrate. Subsequently, the polycrystalline silicon film is processed using the resist pattern as a mask to form a gate electrode. Subsequently, after removing the resist pattern, n-type impurities are introduced into the silicon substrate on both sides of the gate electrode to form source / drain regions. Thereafter, a sidewall is formed on the side wall of the gate electrode, and a silicide film is formed on the upper surface of the gate electrode and the main surface of the silicon substrate.

  Next, after a silicon oxide film having a thickness of, for example, about 850 nm is deposited by CVD, the upper surface of the silicon oxide film is planarized by CMP to form an interlayer insulating film.

  Next, a resist film is applied on the interlayer insulating film, and exposure is performed using a contact layer reticle. For exposure of the contact layer, rough alignment and EGA are performed, and then position information of each shot is obtained using gate alignment marks arranged at the first pitch in the main body chip region, and die-by-die is obtained based on the data. Align.

  Next, using the overlay inspection mark of the Gate layer in the main body chip region formed when the gate electrode is processed, and the overlay inspection mark of the Contact layer formed in the resist pattern by resist patterning of the Contact layer. Measure overlay deviation. The result of this measurement is fed back to the exposure parameter of the Contact layer in the next lot processing.

  Next, the interlayer insulating film is processed using the resist pattern as a mask to form a connection hole in the interlayer insulating film, and then the resist pattern is removed, and the main surface of the silicon substrate exposed at the bottom of the connection hole is washed to naturally The oxide film is removed.

  Next, a barrier metal film is formed by depositing a titanium (Ti) film and a titanium nitride (TiN) film by a collimation sputtering method. Subsequently, after depositing, for example, a tungsten (W) film having a thickness of about 600 nm on the interlayer insulating film including the inside of the connection hole, the tungsten (W) film other than the inside of the connection hole is polished and removed by a CMP method. By doing so, a plug is formed inside the connection hole. Thereafter, a first wiring layer electrically connected to the plug is formed. Through the above steps, the field effect transistor is substantially completed.

  As described above, according to the fourth embodiment, the gate layer and the contact layer are required to have high overlay accuracy. However, the position information in the main body chip area is obtained for each exposure shot, and is obtained for each shot. By performing die-by-die alignment while correcting based on the position information, it is possible to reduce overlay deviation and to realize high overlay accuracy.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

AG, AM2, AS, AV1 Mark area AM, AMC, AMG, AMM2, AMV1, AMV2 Alignment mark AMP Position where alignment mark is placed BF Viafill material BG, BM1, BM2, BS, BV1, BV2 Inspection mark area C2, C3 Connection Member CNT1, CNT2, CNT3 Connection hole DAC, DAG, DAS, DAM1, DAM2 CMP dummy arrangement area DAV1, DAV2 CMP dummy arrangement area DAD CMP dummy overlap area DP CMP dummy GI Gate oxide film GE Gate electrodes IMC, IMG, IMM1, IMM2 , IMV1, IMV2 Overlay inspection mark IMP Position where overlay inspection mark is placed IS1 First interlayer insulating film IS2 Second interlayer insulating film IS3 Third interlayer insulating film IS4 Fourth interlayer insulating film M1 First wiring layer M2 Second wiring layer M3 Third wiring layer MSKC, MSKG, MSKM1, MSKM2, MSKS Mask MSKV1, MSKV2 Mask MT1, MT2, MT3 Wiring trench NT Opaque film SA Scribe area SC Body chip area SD Source / drain area SI Silicide film SN Liner silicon nitride film STI Element isolation part SUB Silicon substrate SW Side wall PLG Plug RP Resist pattern V1 First via hole V2 Second via hole WAF Wafer

Claims (16)

The first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer are the first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer. A method of manufacturing a semiconductor device that performs exposure in the order of layers,
When the layer to be bonded is the m-th processed layer (1 ≦ m ≦ n−1) and the exposure layer is the n-th processed layer,
The first mask to the (n-1) th mask used when exposing the pattern data of the first processed layer to the (n-1) th processed layer are respectively the first processed layer to the (n-1) th. In the main body chip area where the pattern data of the product area of the processed layer is drawn, the first dummy area to the (n-1) th dummy area are provided,
In the mth dummy area of the mth mask, an alignment mark is disposed in an overlapping area of the dummy area extracted from the first dummy area to the (n-1) th dummy area,
A pattern is not arranged at a position corresponding to the alignment mark in the first dummy area to the (n-1) th dummy area of the first mask to the (n-1) th mask other than the mth mask. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first dummy region to the (n−1) th dummy region are regions in which a dummy pattern for improving processing flatness in CMP is disposed. The method of manufacturing a semiconductor device according to claim 2.
In the first processing layer to the (n−1) th processing layer in which no dummy pattern for improving processing flatness in CMP is arranged, a temporary dummy pattern is generated to calculate an overlapping region of the dummy region. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
In the mth dummy region of the mth mask,
The alignment mark is arranged in an m-th mark area comprising a first area where the alignment mark is arranged and a second area around the first area and having a certain width from the pattern end of the alignment mark. There is no pattern other than
In the first dummy region to the (n−1) th dummy region of the first mask to the (n−1) th mask other than the mth mask,
A method of manufacturing a semiconductor device, wherein no pattern is arranged in a first mark area to an (n-1) th mark area at a position corresponding to the m-th mark area. In the manufacturing method of the semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the second region has a width of 0.3 μm or more from a pattern end of the alignment mark. The first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer are the first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer. A method of manufacturing a semiconductor device that performs exposure in the order of layers,
When the layer to be bonded is the m-th processed layer (1 ≦ m ≦ n−1) and the exposure layer is the n-th processed layer,
The first mask to nth mask used when exposing the pattern data of the first processed layer to the nth processed layer are drawn with the pattern data of the product region of the first processed layer to the nth processed layer, respectively. Having a first dummy area to an nth dummy area in the main body chip area;
In the mth dummy area of the mth mask, a first overlay inspection mark is disposed in an overlapping area of dummy areas extracted from the first dummy area to the nth dummy area,
A second overlay inspection mark is disposed at a position corresponding to the first overlay inspection mark in the nth dummy region of the nth mask;
Positions corresponding to the first and second overlay inspection marks in the first dummy area to the (n-1) dummy area of the first mask to the (n-1) mask other than the m-th mask. A method for manufacturing a semiconductor device, wherein no pattern is disposed on the substrate. The method of manufacturing a semiconductor device according to claim 6.
The method for manufacturing a semiconductor device, wherein the first to nth dummy regions are regions in which dummy patterns for improving processing flatness in CMP are disposed. The method of manufacturing a semiconductor device according to claim 7.
Manufacturing of a semiconductor device in which a dummy pattern is generated and an overlapping area of the dummy area is calculated in the first to n-th processing layers where no dummy pattern for improving processing flatness in CMP is arranged Method. The method of manufacturing a semiconductor device according to claim 6.
In the mth dummy region of the mth mask and the nth dummy region of the nth mask,
An m-th inspection mark region comprising: a first region in which an overlay inspection mark is disposed; and a second region around the first region and having a certain width from the pattern end of the overlay inspection mark; No pattern other than the overlay inspection mark is arranged in the nth inspection mark region,
In the first dummy region to the (n−1) th dummy region of the first mask to the (n−1) th mask other than the mth mask,
A method of manufacturing a semiconductor device, wherein a pattern is not arranged in a first inspection mark region to an (n-1) th inspection mark region at positions corresponding to the mth inspection mark region and the nth inspection mark region. In the manufacturing method of the semiconductor device according to claim 9,
The semiconductor device manufacturing method, wherein the second region has a width of 0.3 μm or more from a pattern end of the overlay inspection mark. The first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer are the first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer. A method of manufacturing a semiconductor device that performs exposure in the order of layers,
When the layer to be bonded is the m-th processed layer (1 ≦ m ≦ n−1) and the exposure layer is the n-th processed layer,
The first mask to the (n-1) th mask used when exposing the pattern data of the first processed layer to the (n-1) th processed layer are respectively the first processed layer to the (n-1) th. In the main body chip area where the pattern data of the product area of the processed layer is drawn, the first dummy area to the (n-1) th dummy area are provided,
In the mth dummy region of the mth mask, a plurality of alignment marks are arranged in an overlapping region of the dummy region extracted from the first dummy region to the (n−1) th dummy region,
A method for manufacturing a semiconductor device, wherein die-by-die alignment is performed using the plurality of alignment marks. The method of manufacturing a semiconductor device according to claim 11.
A method of manufacturing a semiconductor device, wherein a plurality of first lattice points having a first pitch are provided in an overlapping region of the dummy region, and the alignment marks are respectively disposed at the plurality of first lattice points. The method of manufacturing a semiconductor device according to claim 11.
A plurality of first lattice points having a first pitch and a plurality of second lattice points having a second pitch smaller than the first pitch are provided in an overlapping region of the dummy region, and the plurality of first lattice points and A method for manufacturing a semiconductor device, wherein the alignment marks are respectively arranged at a plurality of second lattice points. The first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer are the first processed layer, the second processed layer, the (n-1) processed layer, and the nth processed layer. A method of manufacturing a semiconductor device that performs exposure in the order of layers,
When the layer to be bonded is the m-th processed layer (1 ≦ m ≦ n−1) and the exposure layer is the n-th processed layer,
The first mask to nth mask used when exposing the pattern data of the first processed layer to the nth processed layer are drawn with the pattern data of the product region of the first processed layer to the nth processed layer, respectively. Having a first dummy area to an nth dummy area in the main body chip area;
In the m-th dummy area of the m-th mask, a plurality of first overlay inspection marks are arranged in an overlapping area of dummy areas extracted from the first dummy area to the n-th dummy area,
In the nth dummy area of the nth mask, a plurality of second overlay inspection marks are arranged at positions corresponding to the plurality of first overlay inspection marks,
A method of manufacturing a semiconductor device, wherein die-by-die alignment is performed by feeding back a result of misalignment measurement using the plurality of first overlay inspection marks and the plurality of second overlay inspection marks. 15. The method of manufacturing a semiconductor device according to claim 14,
A method of manufacturing a semiconductor device, wherein a plurality of first lattice points having a first pitch are provided in an overlapping region of the dummy region, and an overlay inspection mark is disposed at each of the plurality of first lattice points. 15. The method of manufacturing a semiconductor device according to claim 14,
A plurality of first lattice points having a first pitch and a plurality of second lattice points having a second pitch smaller than the first pitch are provided in an overlapping region of the dummy region, and the plurality of first lattice points and A method for manufacturing a semiconductor device, wherein an overlay inspection mark is arranged at each of the plurality of second lattice points.

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