CN112558407A

CN112558407A - Method for manufacturing semiconductor device

Info

Publication number: CN112558407A
Application number: CN202010673245.6A
Authority: CN
Inventors: 林汉仲; 林忠亿; 王彦森
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-09-26
Filing date: 2020-07-14
Publication date: 2021-03-26

Abstract

The present disclosure provides a method of manufacturing a semiconductor device, comprising receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the post-routing layout to obtain a post-OPC layout; and modifying the post-OPC layout to obtain a modified layout. The modification of the post-routing layout includes inserting a plurality of first dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a plurality of second dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the plurality of first dummy vias.

Description

Method for manufacturing semiconductor device

Technical Field

The present disclosure relates to a method and structure for preventing plasma-generated damage, and more particularly, to a method and structure for modifying a dummy via to prevent plasma-generated damage.

Background

The Integrated Circuit (IC) industry has experienced rapid growth. As ICs evolve, functional density (e.g., the number of interconnects per unit of chip area) generally increases, while geometries (e.g., the smallest component (or line) that can be created using a fabrication process) shrink. This process of scaling generally provides benefits by increasing production efficiency and reducing associated costs. However, such scaling is also accompanied by an increase in the complexity of the design and fabrication of the devices incorporating these ICs, and similar developments in IC fabrication are required to achieve these advances.

The IC chip includes interconnect structures to interconnect various active and passive components in the IC chip. The interconnect structure includes a plurality of thin layers of conductive lines embedded in a plurality of inter-metal dielectric (IMD) layers, wherein the conductive lines in different thin layers are connected by contact vias (contacts via) formed in each of the plurality of IMD layers. Although these wires and contact vias (collectively referred to as conductive patterns) meet the interconnect requirements, they may not be uniformly distributed. The non-uniformly distributed conductive pattern may include isolated regions, which may be polished at different rates during a Chemical Mechanical Polishing (CMP) process, thereby causing dishing or erosion. Dummy (dummy) vias (i.e., non-functional vias) are inserted into the isolated regions to compensate for the non-uniform distribution of the conductive patterns. Sometimes, the inserted dummy vias (dummy vias) help to form electrically floating daisy chain blocks (floating daisy chain blocks) that extend through the IMD layers. Charge may be generated by exposure to plasma during the manufacturing process and accumulate in the electrically floating daisy chain block. As device sizes shrink in IC chips, the thickness of IMD layers and interlayer dielectric (ILD) layers also decrease. The accumulated charge may cause breakdown (breakdown) of the IMD or ILD layer of reduced thickness. Thus, while conventional integrated circuits are adequate for their intended purposes, they are not satisfactory in all respects.

Disclosure of Invention

Embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the routed layout to obtain a post-OPC layout, the post-OPC layout comprising a plurality of dense areas and a plurality of isolated areas; determining a first number of nominal virtual vias to be inserted into the plurality of islands; lowering the first number of nominal virtual vias to a second number of nominal virtual vias; and modifying the post-OPC layout based on the second number of nominal virtual vias to obtain a modified layout. The modification of the post-OPC layout includes inserting a second number of nominal virtual vias in the post-OPC layout.

The disclosed embodiments provide a system for manufacturing a semiconductor device. The system for inserting a virtual via includes a computing device configured to: receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the routed layout to obtain a post-OPC layout, the post-OPC layout comprising a plurality of dense areas and a plurality of isolated areas; determining a first number of nominal virtual vias to be inserted into the plurality of islands; lowering the first number of nominal virtual vias to a second number of nominal virtual vias; and modifying the post-OPC layout based on the second number of nominal virtual vias to obtain a modified layout. In this embodiment, the modification of the post-OPC layout includes inserting a second number of nominal virtual vias in the post-OPC layout.

Embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the routed layout to obtain a post-OPC layout, the post-OPC layout comprising a plurality of dense areas and a plurality of isolated areas; determining a number of nominal virtual vias into which the plurality of islands are to be inserted; and modifying the post-OPC layout based on the number of nominal virtual vias to obtain a modified layout. The modification of the post-OPC layout includes removing the nominal dummy vias among the above-mentioned number of nominal dummy vias to avoid horizontal bridging between two adjacent metal lines in the first metal layer.

Drawings

Embodiments of the present disclosure may be better understood from the following description and accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a simplified block diagram of an Integrated Circuit (IC) manufacturing system and associated IC manufacturing process flow, according to an embodiment of the present disclosure.

Fig. 2 is a cross-sectional view of a semiconductor device including an electrically floating daisy chain block, according to an embodiment of the present disclosure.

FIG. 3 is a diagram illustrating a short circuit loop of the electrically floating daisy chain block of FIG. 2 due to plasma charging, according to an embodiment of the present disclosure.

Fig. 4-6 are diagrams illustrating mechanisms for avoiding the short circuit loop of fig. 3, according to embodiments of the present disclosure.

Fig. 7 is a flow chart illustrating a method for inserting a virtual via according to an embodiment of the present disclosure.

Description of reference numerals:

100: IC manufacturing system

120: design studio

122: IC design layout

130: photomask studio

132: mask data preparation

144: photomask fabrication

150: IC manufacturer

152: production wafer

160: IC device

20: plasma body

200: semiconductor device with a plurality of semiconductor chips

202: substrate

204-1: first contact via

204-2: second contact via

206-1,206-2: conducting wire

208-1,208-2: conducting wire

210-1,210-2: conducting wire

212-1,212-2: conducting wire

214-1,214-2: conducting wire

216-1,216-2: conducting wire

218-1,218-2: conducting wire

220-1,220-2: conducting wire

222-1,222-2: conducting wire

224: IMD layer

226: etch stop layer

230: a first series of contact vias

240: second series of contact vias

250: electric floating splice chrysanthemum refining block

252: first point of approach

254: second point of approach

260: first salient point

270: second salient point

280: interconnect structure

290: short-circuit loop

300: first local interconnect structure

302-308: etch stop layer

312-316: IMD layer

322: conducting wire

331,332: contact via

341 to 344: conducting wire

351 to 354: contact via

361,362: conducting wire

400: second local interconnection structure

402-408: etch stop layer

412 to 416: IMD layer

421,422: conducting wire

431 to 434: contact via

441-444: conducting wire

452: contact via

461,462: conducting wire

470: conductive path

480: boundary of

490: virtual via free zones

D: buffer distance

I, II: region(s)

500: third local interconnect structure

502 to 508: etch stop layer

512-516: IMD layer

521-525: conducting wire

531 to 536: dummy vias

541,542: conducting wire

L: first chrysanthemum refining block

R: second chrysanthemum refining block

600: method of producing a composite material

602-616: square block

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of the components and arrangements of the present disclosure are set forth below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, the description herein of a first feature formed over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, forming, connecting, and/or coupling one feature over, to, and/or to another feature described below may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features are formed interposing the features, such that the features are not in direct contact. Furthermore, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "upper," "lower," "below," "up," "down," "top," "bottom," etc., and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to facilitate understanding of the relationship of one feature of the disclosure to another feature. The spatially relative terms are intended to encompass different orientations of the device in which the features are included. Further, when a number or range of numbers is described in terms of "about," "approximately," or the like, the term is intended to encompass reasonable numbers including the number, such as +/-10% of the number or other value as understood by one of ordinary skill in the art. For example, the term "about 5 nanometers (nm)" encompasses a size range from 4.5nm to 5.5 nm.

The present disclosure relates to methods and structures for preventing plasma-generated damage. In some embodiments of the present disclosure, the above method includes reducing a number of dummy (non-functional) vias (via) vertically aligned with another overlying or underlying dummy via coupled to an overlying (overlying) via, removing dummy vias of a horizontal bridging dummy interconnect block and an operational interconnect block, and reducing a number of dummy vias coupling two vertically adjacent lamellae. When the dummy vias are inserted following the methods of the present disclosure, the resulting structure is less likely to include electrically floating daisy-chain blocks that can be charged by exposure to plasma. The risk of breakdown of the IMD/ILD layer due to charge accumulation is mitigated when there is no electrically floating stud.

Referring initially to fig. 1, fig. 1 illustrates a simplified block diagram of an Integrated Circuit (IC) manufacturing system 100 and associated IC manufacturing flow that may benefit from various embodiments of the present disclosure. The IC manufacturing system 100 includes a plurality of entities, such as a design studio 120, a mask studio 130, and an IC manufacturer 150, which interact with each other in the design, development, and manufacturing cycles and/or services associated with manufacturing Integrated Circuit (IC) devices 160. The entities are linked by a communication network, which may be a single network or a variety of different networks, such as an intranet and the Internet, and may include wired and/or wireless communication channels. Each entity may interact with other entities and may provide services to and/or receive services from other entities. One or more of the design studio 120, the reticle studio 130, and the IC fab 150 may have the same owner and may coexist in a common facility and use common resources.

In various embodiments, a design studio 120, which may include one or more design teams, generates an IC design layout 122. The IC design layout 122 may include various geometric patterns (layouts) designed for the fabrication of the IC device 160. For example, the geometric pattern may correspond to a pattern of thin layers of metal, oxide, or semiconductor that make up various components of the IC device 160 to be fabricated. The various thin layers are combined to form various features of the IC device 160. For example, various portions of an IC design layout may include features such as active regions (active regions), gate electrodes, source and drain regions, metal lines or vias for metal interconnects, openings for bond pads, and other features formed in a semiconductor substrate (e.g., a silicon wafer) and various layers of materials disposed thereon as is known in the art. Furthermore, in accordance with an embodiment of the present disclosure, the IC design layout 122 may include overlay test pattern cells (overlay test pattern cells). In various examples, the design studio 120 executes a design program to form the IC design layout 122. Design programs may include logic designs, physical designs, and/or placement and routing. The IC design layout 122 may be presented in one or more data files having information about the geometric patterns to be used in the fabrication of the IC device 160. In some examples, the IC design layout 122 may be represented in a graphic database system II (GDSII) file format, or a DF II file format.

In some embodiments, the design studio 120 may transfer the IC design layout 122 to the reticle studio 130, for example, via the network connection described above. The mask shop 130 may then use the IC design layout 122 to manufacture one or more masks to be used to manufacture the various layers of the IC device 160 according to the IC design layout 122. In various examples, the mask studio 130 performs mask data preparation 132, wherein the IC design layout 122 is converted into a form that can be written to physically by a mask writer (physical), the mask studio 130 performs mask fabrication 144, wherein the data prepared by the mask data preparation 132 is modified to conform to a particular mask writer and/or mask fab and then performs fabrication. In the example of FIG. 1, mask data preparation 132 and mask fabrication 144 are depicted as individual elements, however, in other embodiments, mask data preparation 132 and mask fabrication 144 may be collectively referred to as mask preparation.

In some examples, mask data preparation 132 includes applying one or more Resolution Enhancement Technologies (RET) to compensate for potential lithography errors, such as may be caused by diffraction (diffraction), interference (interference), or other process effects. In some examples, Optical Proximity Correction (OPC) may be used to adjust the line width according to the density of the surrounding geometry, to add a "dog-bone" end cap (end-cap) at the end of the wire segment to prevent shortening of the end of the wire segment, to correct electron beam (e-beam) proximity effects, or for other purposes known in the art. For example, OPC techniques may incorporate sub-resolution assist features (SRAFs), which may include, for example, scattering bars (scattering bars), serifs (serifs), and/or hammerheads (hammerheads) into the IC design layout 122 according to an optical model or rules, such that the final pattern on the wafer is improved with enhanced resolution and precision (precision) after the lithography process. The mask data preparation 132 may also include other resolution enhancement techniques, such as off-axis illumination (OAI), phase shift mask (PMS), other suitable techniques, or combinations thereof. In addition, mask data preparation 132 may also include inserting dummy metal lines and dummy vias into the isolated (loosely packed) regions to increase pattern density. For example, the reticle data preparation 132 may include a method for inserting a virtual via, such as the method 600, which will be described below. The mask data preparation 132 modifies the IC design layout 122 to output the modified IC design layout 122 for further processing. In some embodiments presented in FIG. 1, reticle data preparation 132 is performed by the reticle studio 130. In other embodiments, the mask data preparation 132 may be performed partially or entirely by the IC fab 150, with the IC fab 150 having better equipment to evaluate process related features (attributes).

After mask data preparation 132 and during mask fabrication 144, a mask or set of masks may be fabricated based on the modified IC design layout 122. For example, an electron beam (e-beam) writer or a multiple electron beam mechanism is used to pattern a reticle (reticle) based on the modified IC design layout 122. The mask can be formed using various techniques. In one embodiment, the mask is formed using binary technology (binary technology). In some embodiments, the mask pattern includes opaque (opaque) regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, is used to expose a layer of radiation-sensitive material (e.g., photoresist) applied to a wafer, which is blocked by an opaque region and passes through a transparent region. In one example, a binary reticle includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) applied to opaque regions of the reticle. In some examples, the mask is formed using a phase shift technique. In phase shift reticles, various features in the pattern formed on the reticle are configured to have a pre-configured phase difference (phase difference) to enhance image resolution and imaging quality. In various embodiments, the phase shift mask may be an attenuated (attenuated) PSM or an alternating (alternating) PSM.

In some embodiments, IC fab 150 (e.g., a semiconductor foundry (foundry)) uses a mask (or masks) manufactured by mask shop 130 to transfer one or more mask patterns onto production wafer 152 and thereby manufacture IC devices 160 on production wafer 152. IC fabrication facility 150 may include an IC fabrication facility, which may include a myriad of fabrication facilities for fabricating a variety of different IC products. For example, an IC fab 150 may include a first fabrication facility (i.e., front-end-of-line (FEOL)) for front-end fabrication of a plurality of IC products, while a second fabrication facility may provide back-end-of-line (BEOL) for interconnection and packaging of the IC products, and a third fabrication facility may provide other services (e.g., research and development) for wafer foundry. In various embodiments, the semiconductor wafer (i.e., production wafer 152) in which the IC devices 160 are fabricated may include a silicon substrate or other substrate having a thin layer of material formed thereon. Other substrate materials may include another suitable elemental semiconductor such as diamond or germanium (germanium), a suitable compound semiconductor such as silicon carbide (silicon carbide), indium arsenide (indium arsenide) or indium phosphide (indium phosphide), or a suitable alloy semiconductor such as silicon germanium carbide (silicon germanium carbide), gallium arsenic phosphide (gallium arsenic phosphide) or gallium indium phosphide (gallium indium phosphide). In some embodiments, the semiconductor wafer may further include differently doped regions, dielectric features, and multilevel interconnects (formed in subsequent fabrication operations).

Referring now to fig. 2, fig. 2 illustrates a cross-sectional view of a semiconductor device 200 including an electrically floating daisy chain block 250. The semiconductor device 200 includes a substrate 202. The substrate 202 may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes (diodes), p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), Laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The substrate 202 may include an interconnect structure 280, the interconnect structure 280 interconnecting devices in the substrate 202 and coupling the devices in the substrate 202 to external circuitry.

As shown in fig. 2, the interconnect structure 280 includes a plurality of conductive lines 206-1,206-2, 208-1,208-2, 210-1,210-2, 212-1,212-2, 214-1,214-2, 216-1,216-2, 218-1,218-2, 220-1,220-2, 222-1, and 222-2 formed in a plurality of inter-metal dielectric (ILD) layers. One of the plurality of IMD layers is IMD layer 224. The IMD layers are divided by Etch Stop Layers (ESLs). One of the plurality of etch stop layers is etch stop layer 226, and etch stop layer 226 may be formed of silicon nitride. Leads 206-1 and 206-2 are disposed in the same IMD layer. Similarly, leads 208-1 and 208-2, leads 210-1 and 210-2, leads 212-1 and 212-2, leads 214-1 and 214-2, leads 216-1 and 216-2, leads 218-1 and 218-2, leads 220-1 and 220-2, and leads 222-1 and 222-2 of each pair are disposed in the same IMD layer. The semiconductor device 200 includes a first contact via 204-1 and a second contact via 204-2 electrically coupled to a device formed in the substrate 202. The first contact via 204-1 is electrically coupled to a first bump (bump)260 through the wires 206-1, 208-1, 210-1, 212-1, 214-1, 216-1, 218-1, 220-1, and 222-1 and the first series of contact vias 230, the first bump 260 for connection to external circuitry. Similarly, the second contact via 204-2 is electrically connected to the second bump 270 and the second bump 270 is used to connect to external circuitry through the wires 206-2, 208-2, 210-2, 212-2, 214-2, 216-2, 218-2, 220-2, and 222-2 and the second series of contact vias 240. The second contact via 204-2, the conductive lines, the first series of contact vias 230, and the second series of contact vias 240 are functional conductive lines and contact vias that electrically couple devices in the substrate 202 to the outside world.

Reference is briefly made to fig. 1. When the portion of primary interest is conductive pattern density uniformity, dummy vias can be inserted into the IC design layout 122 in the mask data preparation 132 without loss, such that the low pattern density in the isolated regions becomes the high pattern density in the dense regions. In those cases, the interposed dummy vias may interconnect the plurality of dummy vias and the plurality of dummy conductive lines to form electrically floating daisy-chain blocks. Referring back to fig. 2, semiconductor device 200 also includes one such electrically floating daisy chain block, namely electrically floating daisy chain block 250. The electrically floating stud 250 is electrically floating and is not coupled to any functional conductive lines, functional contact vias, devices formed in the substrate 202, or the bump 260 or the bump 270. As shown in FIG. 2, electrically floating daisy chain block 250 may approach conductive line 206-1 at a first proximity point 252 and approach conductive line 206-2 at a second proximity point 254. At each of the first and

second access points

252, 254, the electrically floating stud 250 is electrically insulated from the functional conductive pattern (the conductive lines 206-1,206-2 and all conductive lines and contact vias coupled thereto) by the thickness of the IMD layer 224 and the etch stop layer 226. During the fabrication of the semiconductor device 200, a plasma 20 may be generated over the semiconductor device 200 to facilitate the deposition or etching of various thin layers. It has been observed that electrically floating daisy chain block 250 can be used as an "antenna (antenna)" to be charged by plasma 20. The charge induced by plasma 20 may accumulate in electrically floating daisy chain block 250. In some cases, when sufficient charge is accumulated in the electrically floating daisy chain block 250, dielectric breakdown may occur at the first proximity point 252 and the second proximity point 254. A short circuit loop 290 in fig. 3 may result. The first bump 260 is shorted to the second bump 270 via a shorting loop 290.

The present disclosure provides exemplary mechanisms for preventing the formation of electrically floating daisy-chained blocks. A first exemplary mechanism for reducing/avoiding vertical coupling is described in conjunction with the first local interconnect structure 300 in fig. 4. The first local interconnect structure 300 includes a plurality of Etch Stop Layers (ESLs) 302, 304, 306, and 308, and a plurality of IMD layers 312, 314, and 316. IMD layer 312 includes leads 322; IMD layer 314 includes

leads

341, 342, 343, and 344; and IMD layer 316 includes

conductive lines

361 and 362. Conductive line 341 and conductive line 343 are vertically coupled to conductive line 322 through

contact vias

331 and 332, respectively. When contact via 351 is implemented,

conductive lines

361, 341, and 322 become electrically coupled because contact via 351 and contact via 331 are both coupled to conductive line 341. However, when contact via 352 is implemented instead, conductive line 361 is only coupled to floating conductive line 342 and not to underlying conductive line 322. That is, by avoiding connecting a contact via to the same wire at the same time as the contact via above, the number of wires that become interconnected is reduced. Thus, the first exemplary mechanism may reduce vertical coupling of wires in different layers. Similarly, when the contact via 353 is implemented, the

wires

362, 343, and 322 become electrically coupled because the contact via 353 and the contact via 332 are coupled to the wire 343. However, when contact via 354 is implemented instead, conductive line 362 is coupled only to floating conductive line 344 and not to underlying conductive line 322. It can be seen that even if electrically floating daisy-chain blocks are formed, applying the first exemplary mechanism can reduce the mass/volume of the electrically floating daisy-chain blocks, thereby reducing the amount of charge stored in the electrically floating daisy-chain blocks.

A second exemplary mechanism for reducing/avoiding horizontal bridging is described in conjunction with the second local interconnect structure 400 in fig. 5. The second local interconnect structure 400 includes a plurality of Etch Stop Layers (ESLs) 402, 404, 406, and 408, and includes a plurality of IMD layers 412, 414, and 416. IMD layer 412 comprises

conductive lines

421 and 422; IMD layer 414 includes

conductive lines

441, 442, 443, and 444; IMD layer 316 includes

conductive lines

461 and 462. The conductive traces 421 and 422 in the IMD layer 412 are not electrically coupled to each other by any feature in the IMD layer 412. When contact vias 432 and 433 are implemented, a conductive path 470 may be formed that includes contact via 432, contact via 433, and conductive line 442, bridging

conductive lines

421 and 422. However, when the

contact vias

431 and 434 are implemented instead, no conductive path is formed to bridge the

conductive lines

421 and 422. That is, by avoiding the formation of a conductive path bridging two horizontally spaced wires, the number of wires that can become interconnected may be less. Thus, the second exemplary scheme reduces horizontal coupling of wires disposed within the same interconnect layer. In some embodiments, the second local interconnect structure 400 is disposed at a boundary 480 between region I and region II. In some embodiments, region I includes OPC features such as scattering bars (scattering bars), serifs (serifs), hammerheads (hammerheads), OPC dummy wires (i.e., OPC dummy metal lines), and may be referred to as OPC regions. Area II does not contain any OPC features and may be referred to as a non-OPC area. The area I may be adjacent to functional features that may be affected by OPC corrections. The area II may be spaced apart from any functional features that may be affected by OPC corrections. Generally, the size of the conductive lines in region I will tend to be smaller than the conductive lines in region II. In some embodiments, the first exemplary mechanism may not include identifying two horizontally spaced conductive lines within the same lamina. In those embodiments, a computer program or algorithm may be executed by the computing device to identify (identify) the boundary 480 and then define the dummy-via-free zone 490. In some cases, the virtual via-free zone 490 is defined by a buffer distance (buffer distance) D measured from the boundary 480. In some embodiments, the buffer distance D is between about 0.5 μm and about 2 μm. In the embodiment shown in fig. 5, the contact vias 452 in the IMD layer 416 do not fall into the non-dummy via regions 490.

A third exemplary mechanism for reducing the density of dummy vias is described in conjunction with the third local interconnect structure 500 in fig. 6. The third local interconnect structure 500 includes a plurality of Etch Stop Layers (ESLs) 502, 504, 506, and 508, and a plurality of IMD layers 512, 514, and 516. IMD layer 512 includes

leads

521, 522, 523, 524, and 525; IMD layer 514 includes

conductive lines

541 and 542; and IMD layer 516 includes

conductive lines

461 and 462. When conventional dummy via insertion methods are used, dummy vias 531, 532, 533, 534, 535, and 536 electrically couple

conductive traces

521, 522, 523, 524, and 525 in IMD layer 512 to

conductive traces

541 and 542 in IMD layer 514. In addition, dummy vias 451 and 452 electrically couple

conductive lines

541 and 542 in IMD layer 514 to

conductive lines

461 and 462 in IMD layer 516. Specifically, dummy vias 533 and 534 facilitate horizontal bridging of

conductive lines

541 and 542 in IMD layer 514, thereby electrically coupling first daisy-chain block L and second daisy-chain block R. Each of the first daisy chain block L and the second daisy chain block R includes a plurality of interconnected contact vias and conductive lines. However, when the number of dummy vias in IMD layer 514 is reduced by removing (or not inserting) dummy vias 531, 533, 534, and 536, the electrical coupling between first daisy chain block L and second daisy chain block R is cut off. In some examples, the density or number of dummy vias within the IMD layer may be reduced by about 10% to about 20%. The reduction of dummy vias not only reduces the horizontal bridging shown in fig. 6, but also reduces the vertical coupling between the conductive layers.

Fig. 7 shows a flow chart of a method 600 for inserting a virtual via. The method 600 utilizes the three exemplary mechanisms described above and may be performed by a virtual plug-in system that includes a computing device executing one or more software programs. Method 600 may not be performed by a human in view of the complexity of modern IC designs and the number of conductive patterns. The method 600 includes a block 602, where the layout is received in the block 602. In some embodiments, the layout may include a plurality of active devices and a plurality of passive devices.

Still referring to FIG. 7, the method 600 includes a block 604 where routing of the layout is performed in block 604. At block 604, a design of an interconnect structure may be created to functionally interconnect a plurality of active devices and a plurality of passive devices in a layout. The interconnect structure includes a plurality of metal layers (i.e., conductive line layers). In some embodiments, each of the plurality of metal layers includes an inter-metal dielectric (IMD) layer and a plurality of conductive patterns. In some cases, each of the plurality of metal layers may include an Etch Stop Layer (ESL). The routing operation in block 604 may consider subsequent operations. For example, the routing operation in block 604 would make room for Optical Proximity Correction (OPC) features that can be inserted in block 606. In some cases, if the routing operation in block 604 does not take OPC into account, the conductive lines may contact OPC features and cause electrical shorts.

Referring to FIG. 7, the method 600 includes a block 606 where Optical Proximity Correction (OPC) of the layout is performed in the block 606. In some embodiments, the OPC operations at block 606 include adjusting the line width based on the surrounding geometry density, adding a "dog bone" end cap at the end of the line to prevent shortening of the segment ends, correcting for E-beam proximity effects, or inserting dummy metal features (e.g., dummy conductive lines). For example, the OPC operation in block 606 may add sub-resolution assist features (SRAFs), for example, the addition of SRAFs may include adding scattering bars, serifs, and/or hammerheads to the layout received from block 602 according to an optical model or criteria, such that the final pattern on the wafer is improved and has enhanced resolution and accuracy after the lithography process. Since OPC features only affect lithography patterning when they are within a certain distance from a main feature (e.g., a small-sized functional metal layer or functional conductive line), the layout may include a plurality of OPC areas around the main feature and a plurality of non-OPC areas outside the plurality of OPC areas. For ease of reference, after performing the OPC operation of block 606 on the layout, the layout may be referred to as a post-OPC (OPC' ed) layout.

Referring to FIG. 7, the method 600 includes a block 608 in which a first number of nominal (nominal) virtual vias is determined based on a pattern density of the post-OPC layout in the block 608. In some embodiments, the post-OPC layout comprises dense (i.e., densely packed) areas and isolated (i.e., loosely packed) areas. To prevent dishing or wear in the isolated regions due to subsequent CMP processes, a first number of nominal dummy vias may be inserted at block 608 to approximate the difference in pattern density between dense and isolated regions. In some embodiments, the operations in block 608 may represent conventional methods of inserting a virtual via. In block 608, horizontal bridging and vertical coupling have not been considered.

Referring to fig. 7, method 600 includes block 610 where the first number of nominal virtual vias is reduced to obtain a second number of nominal virtual vias in block 610. As described above in the third exemplary mechanism shown in fig. 6, the first number of nominal virtual vias is reduced by between about 10% and about 20% to obtain a second number of virtual vias. That is, the second amount is between about 80% to about 90% of the first amount. Given the same total area for each of the plurality of metal layers, the reduction from the first number to the second number also results in a reduction in pattern density of about 10% to about 20%. The reduced pattern density generally reduces the likelihood of horizontal bridging of horizontally spaced conductive lines and reduces the likelihood of vertical coupling between conductive lines in adjacent metal layers. In some embodiments, the method 600 for inserting a dummy via may end at block 610 because the block 610 may substantially avoid large electrically floating daisy-chained structures. In those embodiments, the virtual vias to be inserted comprise a second number of nominal virtual vias. In some alternative embodiments, after performing the operations of block 610, method 600 proceeds to

blocks

612 and 614. In other alternative embodiments, method 600 omits block 610 and proceeds directly to

blocks

612 and 614. In some embodiments, block 610 of method 600 is performed only on the non-OPC areas to reduce the first nominal virtual vias in the non-OPC areas.

Referring to fig. 7, method 600 includes a block 612 in which a plurality of first dummy vias are inserted between a first metal layer and an overlying second metal layer to reduce horizontal bridging in block 612. In some cases, block 612 practices the first exemplary mechanism shown in fig. 5 based on the reduced second number of nominal virtual vias. In some other cases, block 612 practices the first exemplary mechanism based on the first number of nominal virtual vias. In some embodiments, the first metal layer may be a metal layer disposed directly above a substrate, wherein the substrate includes fabricated active devices. In some embodiments, the first metal layer may be electrically connected to fabricated active devices in the substrate through MEOL contact features, such as source/drain contacts or gate contacts. In some embodiments, the second metal layer on the first metal layer is disposed directly on the first metal layer. In some embodiments, block 612 includes identifying conductive lines (or metal lines) in the second metal layer that may be bridged. A possible bridged conductor in the second metal layer is a conductor that vertically overlaps two closely spaced and horizontally spaced conductors. Once the potentially bridged conductive lines are identified, block 612 may remove/eliminate any second number of nominal dummy vias electrically coupled to the potentially bridged conductive lines to prevent the potentially bridged conductive lines from landing on vertically overlapping conductive lines in the first metal layer. By preventing a potentially bridged wire from landing, any horizontal bridging through the potentially bridged wire is avoided.

In some alternative embodiments, block 612 does not identify a wire in the second metal layer that may be bridged. Instead, block 612 includes an operation of identifying boundaries between OPC areas and non-OPC areas and virtual-via-free zones immediately adjacent the boundaries. In these alternative embodiments, block 612 removes/cancels the virtual vias in the virtual-via-free zones. In these alternative embodiments, block 612 is performed only for the boundaries between OPC areas and non-OPC areas.

Referring to fig. 7, method 600 includes a block 614 in which a plurality of second dummy vias are inserted between the second metal layer and the overlying third metal layer to reduce horizontal bridging and vertical coupling with the first plurality of dummy vias. In some embodiments, block 614 practices both the first exemplary mechanism of fig. 4 and the second exemplary mechanism of fig. 5 based on the reduced second number. In some other embodiments, block 614 practices the first and second exemplary mechanisms based on a first number of nominal virtual vias. The operations in block 614 for preventing horizontal bridging are similar to those described above with respect to block 612 and are not repeated here. Block 614 differs from block 612 in that block 614 requires further consideration to avoid dummy vias vertically coupled between the first metal layer and the second metal layer, as has been presently determined. To practice the first exemplary mechanism, block 614 identifies connected wires in the second metal layer. Herein, the connected wire in the second metal layer refers to a wire electrically coupled to at least one of the dummy vias between the first metal layer and the second metal layer. Thereafter, block 614 removes/deselects the first or second number of nominal dummy vias (between the second metal layer and the overlying third metal layer, depending on whether block 614 is based on the first or second number of dummy vias) that are electrically connected to the connected wires. By preventing additional dummy vias from coupling to underlying connected wires, vertical coupling between wires in the third metal layer and wires in the second metal layer is avoided.

Referring to FIG. 7, method 600 includes a block 616, in which operations of block 614 are repeated to insert a dummy via between additional metal layers on the third metal layer. In some embodiments, the interconnect structure for layout may include additional metal layers. Block 616 repeats the operations in block 614 to insert a dummy via between the third metal layer and the additional metal layer. For example, the interconnect structure of the layout may include 9 metal layers. In this example, block 616 may repeat the operations in block 614 to insert dummy vias between the third metal layer and the fourth metal layer, between the fourth metal layer and the fifth metal layer, between the fifth metal layer and the sixth metal layer, between the sixth metal and the seventh metal layer, between the seventh metal layer and the eighth metal layer, and between the eighth metal layer and the ninth metal layer. For each inter-metal level dummy via layer, horizontal bridging between the same metal levels is avoided by practicing the second exemplary mechanism shown in fig. 5, while vertical coupling between two metal levels is avoided by practicing the first exemplary mechanism. In some embodiments, the number of virtual vias to be inserted includes the second number of virtual vias minus the number of virtual vias removed/cancelled in

blocks

612, 614, and 616. In some alternative embodiments, the number of virtual vias to be inserted includes the first number of virtual vias minus the number of virtual vias removed/cancelled in

blocks

612, 614, and 616.

The present disclosure provides methods and structures for preventing plasma-induced damage. The method of the present disclosure practices a plurality of mechanisms to reduce the number of dummy vias, remove/eliminate dummy vias that may bridge horizontally spaced wires, and remove/eliminate dummy vias that may vertically couple wires in vertically adjacent metal layers. In contrast to conventional dummy via insertion processes, the method of the present disclosure may prevent the formation of large electrically floating stud structures that may accumulate excessive charges caused by the plasma.

In one embodiment, a method of manufacturing a semiconductor device is provided. The method includes receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the routed layout to obtain a post-OPC layout, the post-OPC layout comprising a plurality of dense areas and a plurality of isolated areas; determining a first number of nominal virtual vias to be inserted into the plurality of islands; lowering the first number of nominal virtual vias to a second number of nominal virtual vias; and modifying the post-OPC layout based on the second number of nominal virtual vias to obtain a modified layout. The modification of the post-OPC layout includes inserting a second number of nominal virtual vias in the post-OPC layout.

In some embodiments, the second amount is between about 80% and about 90% of the first amount. In some embodiments, the modification of the post-OPC layout includes removing the nominal virtual vias in the second number of nominal virtual vias to avoid horizontal bridging between two adjacent metal lines in the first metal layer. In some embodiments, the removing of the nominal virtual vias of the second number of nominal virtual vias comprises: identifying a bridging metal line in the second metal layer, wherein the bridging metal line spans two adjacent metal lines in the first metal layer; and removing the nominal dummy vias electrically coupled to the bridging metal line from the second number of nominal dummy vias. In some embodiments, the removing of the nominal virtual vias of the second number of nominal virtual vias comprises: identifying a boundary between an OPC area and a non-OPC area; identifying a virtual via free zone proximate to the boundary; and removing nominal virtual vias of the second number of nominal virtual vias that are entirely in the virtual-via-free zone. In some embodiments, the modification of the post-OPC layout includes removing the nominal virtual vias in the second number of nominal virtual vias to avoid vertical coupling between the conductive lines in the first metal layer and the conductive lines in the second metal layer. In some embodiments, the removing of the nominal virtual vias of the second number of nominal virtual vias comprises: identifying a connected metal line in the second metal layer, wherein the connected metal line is electrically coupled to a metal line in the first metal layer; and removing the nominal dummy vias of the second number of nominal dummy vias that are electrically coupled to the connected metal line. In some embodiments, the method further comprises fabricating a set of lithography masks based on the modified layout. In some embodiments, the method further comprises fabricating the semiconductor device using a set of lithography masks.

In another embodiment, a system for manufacturing a semiconductor device is provided. The system includes a computing device configured to perform the following operations: receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the routed layout to obtain a post-OPC layout, the post-OPC layout comprising a plurality of dense areas and a plurality of isolated areas; determining a first number of nominal virtual vias to be inserted into the plurality of islands; lowering the first number of nominal virtual vias to a second number of nominal virtual vias; and modifying the post-OPC layout based on the second number of nominal virtual vias to obtain a modified layout. In this embodiment, the modification of the post-OPC layout includes inserting a second number of nominal virtual vias in the post-OPC layout.

In some embodiments, the second amount is between about 80% and about 90% of the first amount. In some embodiments, the modification of the post-OPC layout includes removing the nominal virtual vias in the second number of nominal virtual vias to avoid horizontal bridging between two adjacent metal lines in the first metal layer. In some embodiments, the removing of the nominal virtual vias of the second number of nominal virtual vias comprises: identifying a bridging metal line in the second metal layer, wherein the bridging metal line spans two adjacent metal lines in the first metal layer; and removing the nominal dummy vias electrically coupled to the bridging metal line from the second number of nominal dummy vias. In some embodiments, the removing of the nominal virtual vias of the second number of nominal virtual vias comprises: identifying a boundary between an OPC area and a non-OPC area; identifying a virtual via free zone proximate to the boundary; and removing nominal virtual vias of the second number of nominal virtual vias that are entirely in the virtual-via-free zone. In some embodiments, the modification of the post-OPC layout includes removing the nominal virtual vias in the second number of nominal virtual vias to avoid vertical coupling between the conductive lines in the first metal layer and the conductive lines in the second metal layer. In some embodiments, the removing of the nominal virtual vias of the second number of nominal virtual vias comprises: identifying a connected metal line in the second metal layer, wherein the connected metal line is electrically coupled to a metal line in the first metal layer; and removing the nominal dummy vias of the second number of nominal dummy vias that are electrically coupled to the connected metal line. In some embodiments, the system for manufacturing a semiconductor device described above is in communication with an electron beam writer, wherein the computing device is further configured to output the modified layout to the electron beam writer for manufacturing the set of lithography masks based on the modified layout.

In yet another embodiment, a method of manufacturing a semiconductor device is provided. The method includes receiving a design layout; performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias; performing an Optical Proximity Correction (OPC) operation on the routed layout to obtain a post-OPC layout, the post-OPC layout comprising a plurality of dense areas and a plurality of isolated areas; determining a number of nominal virtual vias into which the plurality of islands are to be inserted; and modifying the post-OPC layout based on the number of nominal virtual vias to obtain a modified layout. The modification of the post-OPC layout includes removing the nominal dummy vias among the above-mentioned number of nominal dummy vias to avoid horizontal bridging between two adjacent metal lines in the first metal layer.

In some embodiments, the modifying of the post-OPC layout further includes removing the nominal virtual vias among the number of nominal virtual vias to avoid vertical coupling between the conductive lines in the first metal layer and the conductive lines in the second metal layer. In some embodiments, the modification of the post-OPC layout further includes reducing the number of nominal virtual vias to reduce the number of nominal virtual vias.

The foregoing has outlined various embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

receiving a design layout;

performing routing on the design layout to obtain a post-routing layout, the post-routing layout including an interconnect structure, the interconnect structure including a first metal layer, a second metal layer on the first metal layer, a third metal layer on the second metal layer, and a plurality of functional vias;

performing an optical proximity correction operation on the post-routing layout to obtain an optical proximity corrected layout, the optical proximity corrected layout including a plurality of dense areas and a plurality of isolated areas;

determining a first number of nominal virtual vias to be inserted into the isolated regions;

lowering the first number of nominal dummy vias to a second number of nominal dummy vias; and

modifying the optical proximity corrected layout based on the second number of nominal virtual vias to obtain a modified layout,

wherein the modifying of the optical proximity corrected layout comprises inserting the second number of nominal virtual vias in the optical proximity corrected layout.