TWI694165B - Method of measuring offset of pvd material layer and calibration of offset - Google Patents

Method of measuring offset of pvd material layer and calibration of offset Download PDF

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TWI694165B
TWI694165B TW108119387A TW108119387A TWI694165B TW I694165 B TWI694165 B TW I694165B TW 108119387 A TW108119387 A TW 108119387A TW 108119387 A TW108119387 A TW 108119387A TW I694165 B TWI694165 B TW I694165B
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material layer
offset
trench
physical vapor
substrate
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TW108119387A
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TW202045759A (en
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陳永珅
翁堂鈞
林佳弘
陳彥溥
江彥樟
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聯華電子股份有限公司
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Abstract

A method of measuring offset includes providing substrate. A big trench and a small trench are embedded in the substrate. The big trench has a first vertical center line. The small trench has a second vertical center line. A first distance is between the first vertical center line and the second vertical center line. Then, a physical vapor deposition process is performed to form a material layer fills into the big trench and the small trench. The material layer in the big trench forms a first recess, and the material layer in the small trench forms a second recess. The thicknesses of the material layer on the opposing sidewalls of the big trench are different. Then, a position of a third vertical center line of the first recess and a position of a fourth vertical center line of the second recess are detected. A second distance is between the third vertical center line and the fourth vertical center line. Finally, the difference between the second distance and the first distance is calculated to get an offset.

Description

物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法Method for measuring offset of physical vapor deposition material layer and method for correcting offset

本發明係關於一種材料層的偏移量的測量方法以及偏移量的校正方法,特別是一種用於物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法。The invention relates to a method for measuring the offset of a material layer and a method for correcting the offset, in particular to a method for measuring the offset for a physical vapor deposition material layer and a method for correcting the offset.

積體電路的製作過程,乃由矽晶圓開始,經過一連串製程步驟;氧化過程、光學顯影、化學氣相沉積、離子植入、蝕刻、化學機械研磨等前段製程,以及封裝、測試等後段製程方始完成。為了能夠在晶圓上的晶粒佈局完整的電子電路,在過程中,依據電路之設計,藉由光學顯影技術將在所選擇的區域從事離子佈植或金屬接線,同時,並且必須保護其他曝露的表面區域。The manufacturing process of the integrated circuit starts from the silicon wafer and goes through a series of process steps; the oxidation process, optical development, chemical vapor deposition, ion implantation, etching, chemical mechanical polishing and other front-end processes, as well as packaging and testing and other back-end processes Just finished. In order to be able to lay out a complete electronic circuit on the die on the wafer, in the process, according to the design of the circuit, by optical development technology, ion implantation or metal wiring will be performed in the selected area, and at the same time, other exposures must be protected Surface area.

光學顯影主要包含了光阻塗佈、烘烤、光罩對準、曝光和顯影等程序。將電子電路之設計圖在晶圓上塗佈光阻後,再經過光罩對準、曝光和顯影的程序,把光罩上的圖形轉換到光阻上,於是晶圓表面上的光阻便具備與光罩上具有相同的圖形。為了確保半導體製程中上層膜層與下層膜層間之內連線率確無誤,光罩顯影間的對準步驟顯得格外重要。Optical development mainly includes procedures such as photoresist coating, baking, reticle alignment, exposure and development. After coating the design of the electronic circuit on the wafer with photoresist, and then through the process of photomask alignment, exposure and development, the pattern on the photomask is converted to the photoresist, so the photoresist on the wafer surface will be It has the same figure as the mask. In order to ensure that the interconnection rate between the upper film layer and the lower film layer in the semiconductor manufacturing process is correct, the alignment step between the development of the photomask is particularly important.

然而在材料層形成之後,經常發生材料層的厚度不均,影響到光罩對準,造成之後曝光後的光阻圖案發生偏移。However, after the material layer is formed, uneven thickness of the material layer often occurs, which affects the alignment of the photomask and causes a shift in the photoresist pattern after subsequent exposure.

有鑑於此,本發明提供一種材料層的偏移量的測量方法以及偏移量的校正方法,以確保曝光後的光阻圖案之位置的正確性。In view of this, the present invention provides a method of measuring the offset of the material layer and a method of correcting the offset to ensure the correctness of the position of the photoresist pattern after exposure.

根據本發明之一較佳實施例,一種物理氣相沉積材料層的偏移量的測量方法包含:提供一第一基底,其中至少一第一大溝渠和至少一小溝渠埋入第一基底,第一大溝渠具有一第一垂直中心線,小溝渠具有一第二垂直中心線,其中第一垂直中心線和第二垂直中心線之間具有一第一距離,然後進行一第一物理氣相沉積製程,以形成一第一材料層填入第一大溝渠和小溝渠,其中第一材料層在第一大溝渠中形成一第一凹槽,在小溝渠中形成一第二凹槽,第一材料層在第一大溝渠的相對兩個側壁上的厚度不同,接著偵測第一凹槽的一第三垂直中心線之位置並且偵測第二凹槽的一第四垂直中心線之位置,其中第三垂直中心線和第四垂直中心線之間具有一第二距離,最後計算第一距離和第二距離之間的差值以獲得一偏移量。According to a preferred embodiment of the present invention, a method for measuring the offset of a physical vapor deposition material layer includes: providing a first substrate, wherein at least one first large trench and at least one small trench are buried in the first substrate, The first large ditch has a first vertical centerline, and the small ditch has a second vertical centerline, wherein there is a first distance between the first vertical centerline and the second vertical centerline, and then a first physical vapor phase is performed A deposition process to form a first material layer to fill the first large trench and the small trench, wherein the first material layer forms a first groove in the first large trench, and forms a second groove in the small trench, the first A material layer has different thicknesses on two opposite sidewalls of the first large trench, and then detects the position of a third vertical centerline of the first groove and detects the position of a fourth vertical centerline of the second groove , Where there is a second distance between the third vertical centerline and the fourth vertical centerline, and finally the difference between the first distance and the second distance is calculated to obtain an offset.

為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者In order to make the above objects, features and advantages of the present invention more obvious and understandable, the preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail below. However, the following preferred embodiments and drawings are for reference and description only, and are not intended to limit the invention

第1圖至第6圖為根據本發明之第一較佳實施例所繪示的物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法。FIGS. 1 to 6 are a method for measuring the offset of the physical vapor deposition material layer and a method for correcting the offset according to the first preferred embodiment of the present invention.

如第1圖所示,提供一第一基底10,至少一第一大溝渠12和至少一小溝渠14埋入第一基底10,第一大溝渠12的數量可以為1個或是多個,小溝渠14的數量可以為1個或是多個,在本發明的實施例中以第一大溝渠12和小溝渠14的數量各自為1個為例。第一基底10可以為半導體晶圓,例如矽晶圓、矽鍺晶圓。第一基底10也可以為其它絶緣材料,例如氧化矽、氮化矽或是氮氧化矽。第一基底10可以是一測試基底,也就是在實際量產前用於測試製程並以其測試結果調整製程參數,降低實際量產時製程的誤差值所使用的基底。此外,第一基底10也可以是生產用基底,也就是用於正式製作半導體元件用的基底。第一大溝渠12和小溝渠14可以設置在第一基底10的切割道上、或是未來會形成晶粒的位置上,第一大溝渠12和小溝渠14係作為對準標記(alignment mark)。As shown in FIG. 1, a first substrate 10 is provided, at least one first large trench 12 and at least one small trench 14 are buried in the first substrate 10, and the number of the first large trenches 12 may be one or more, The number of the small trenches 14 may be one or more. In the embodiment of the present invention, the number of the first large trenches 12 and the small trenches 14 is one as an example. The first substrate 10 may be a semiconductor wafer, such as a silicon wafer or a silicon germanium wafer. The first substrate 10 may also be other insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride. The first substrate 10 may be a test substrate, that is, a substrate used for testing the process before actual mass production and adjusting process parameters based on the test results to reduce the error value of the process during actual mass production. In addition, the first substrate 10 may be a substrate for production, that is, a substrate for formal production of semiconductor elements. The first large trench 12 and the small trench 14 may be disposed on the scribe line of the first substrate 10 or at a position where a grain will be formed in the future. The first large trench 12 and the small trench 14 serve as alignment marks.

請繼續參閱第1圖,測量第一大溝渠12和小溝渠14的垂直中心線位置,獲得第一垂直中心線M1和第二垂直中心線M2。第一垂直中心線M1和第二垂直中心線M2之間具有一第一距離D1。接著形成一緩衝層16於第一大溝渠12和小溝渠14的側壁和底部,緩衝層16較佳可以是氮化鈦。根據本發明之另一較佳實施例,也可以不形成緩衝層16。第一垂直中心線M1和第二垂直中心線M2係指分別垂直於第一大溝渠12的底部和小溝渠14的底部並且分別把第一大溝渠12和小溝渠14左右平分的基準線。Please continue to refer to FIG. 1 to measure the vertical centerline positions of the first large ditch 12 and the small ditch 14 to obtain the first vertical centerline M1 and the second vertical centerline M2. There is a first distance D1 between the first vertical centerline M1 and the second vertical centerline M2. Next, a buffer layer 16 is formed on the sidewalls and bottom of the first large trench 12 and the small trench 14. The buffer layer 16 may preferably be titanium nitride. According to another preferred embodiment of the present invention, the buffer layer 16 may not be formed. The first vertical center line M1 and the second vertical center line M2 refer to reference lines perpendicular to the bottom of the first large ditch 12 and the bottom of the small ditch 14 respectively, and bisecting the first large ditch 12 and the small ditch 14 respectively.

如第2圖所示,進行一物理氣相沉積製程18以形成一第一材料層20填入第一大溝渠12和小溝渠14,其中第一材料層20第一大溝渠12中形成一第一凹槽22,在小溝渠14中形成一第二凹槽24,第一材料層20在第一大溝渠12的相對兩個側壁上的厚度不同,較佳地第一材料層20在小溝渠14的相對兩側壁上的厚度本質上相同。第一材料層20形成之後,第一凹槽22和第二凹槽24作為第一材料層20這一層的對準標記。然而第一材料層20在相對兩側壁上的厚度不同會在後續會造成光罩定位時的偏差。第一材料層20較佳為導電材料,例如鎢、鈦、銅或是其它可導電的材料,但不限於此,第一材料層20可以是任何以物理氣相沉積製程所形成的材料,包含導電或絶緣的材料皆可以。As shown in FIG. 2, a physical vapor deposition process 18 is performed to form a first material layer 20 to fill the first large trench 12 and the small trench 14, wherein the first material layer 20 forms a first A groove 22, forming a second groove 24 in the small trench 14, the thickness of the first material layer 20 on the two opposite sidewalls of the first large trench 12 is different, preferably the first material layer 20 is in the small trench The thickness on the opposite side walls of 14 is essentially the same. After the first material layer 20 is formed, the first groove 22 and the second groove 24 serve as alignment marks for the first material layer 20. However, the different thicknesses of the first material layer 20 on the opposite side walls may cause deviations in the positioning of the photomask later. The first material layer 20 is preferably a conductive material, such as tungsten, titanium, copper, or other conductive materials, but is not limited thereto. The first material layer 20 may be any material formed by a physical vapor deposition process, including Conductive or insulating materials are acceptable.

第一材料層20的厚度較佳為60奈米,但可以依據不同的需求作調整。此外,需要控制小溝渠14的開口寬度與第一材料層20的厚度比例,以確保第一材料層20填入小溝渠14之後,小溝渠14內還會有凹槽存在,在後續才能偵測凹槽的垂直中心線,小溝渠14的開口寬度與第一材料層20的厚度比值較佳大於2.5。The thickness of the first material layer 20 is preferably 60 nm, but can be adjusted according to different requirements. In addition, the ratio of the opening width of the small trench 14 to the thickness of the first material layer 20 needs to be controlled to ensure that after the first material layer 20 fills the small trench 14, there will be grooves in the small trench 14 that can be detected later The vertical center line of the groove, the ratio of the opening width of the small trench 14 to the thickness of the first material layer 20 is preferably greater than 2.5.

物理氣相沉積製程18藉由高能量的離子束或原子束轟擊靶材(也就是待鍍材料),然後將靶材上的原子撞擊下來,並沉積在第一基底10上,被撞擊下來的各個原子會有各種不同的反射角度,依據第一大溝渠12在第一基底10上不同的座標軸位置,第一大溝渠12所接收到入射原子的角度會有偏性。因為靶材通常設置在第一基底10的中心上方位置,若是第一大溝渠12位在第一基底10的中心,其會接收到平均從各方向來的原子,如此第一材料層20在第一大溝渠12中的相對兩側壁上的厚度就會相同。若是第一大溝渠12位在第一基底10左邊的邊緣,其會接收到比較多由右邊入射的原子,反之若是第一大溝渠12位在第一基底10右邊的邊緣其會接收到比較多由左邊入射的原子,如此便會造成第一材料層20在第一大溝渠12中的相對兩側壁上的厚度有些不同。但小溝渠14因為開口較小,第一材料層20在其兩側厚度的差距小到在實務上可以視為0。根據本發明之較佳實施例,小溝渠14的高與寬的比值介於0.333~1.066之間,第一大溝渠12的高與寬的比值介於0.038~0.123之間。舉例而言,小溝渠14的寬度較佳為150奈米,第一大溝渠12的寬度較佳為1300奈米,小溝渠14和第一大溝渠12的深度相同,較佳介於50奈米和160奈米之間。The physical vapor deposition process 18 bombards the target material (that is, the material to be plated) with a high-energy ion beam or atomic beam, and then strikes the atoms on the target material and deposits them on the first substrate 10. Each atom will have various reflection angles. According to different coordinate axis positions of the first large trench 12 on the first substrate 10, the angle of the incident atoms received by the first large trench 12 may be biased. Because the target material is usually placed above the center of the first substrate 10, if the first large trench 12 is located in the center of the first substrate 10, it will receive atoms from all directions on average, so the first material layer 20 is in the first The thickness of the opposite side walls in the large trench 12 will be the same. If the first large ditch 12 is located on the left edge of the first substrate 10, it will receive more atoms incident from the right, otherwise if the first large ditch 12 is located on the right edge of the first substrate 10, it will receive more The atoms incident from the left will cause the thickness of the first material layer 20 on the opposite side walls of the first large trench 12 to be somewhat different. However, because the small trench 14 has a small opening, the difference in thickness of the first material layer 20 on both sides is so small that it can be regarded as zero in practice. According to a preferred embodiment of the present invention, the ratio of the height and width of the small trench 14 is between 0.333 and 1.066, and the ratio of the height and width of the first large trench 12 is between 0.038 and 0.123. For example, the width of the small trench 14 is preferably 150 nm, the width of the first large trench 12 is preferably 1300 nm, and the depth of the small trench 14 and the first large trench 12 are the same, preferably between 50 nm and Between 160 nanometers.

如第3圖所示,平坦化第一材料層20,使得第一材料層20在第一基底10上表面的厚度變小,舉例而言在平坦化之後,第一材料層20在基底10上表面的厚度較佳為10奈米。然後偵測第一凹槽22的一第三垂直中心線M3之位置並且偵測第二凹槽24的一第四垂直中心線M4之位置,其中第三垂直中心線M3和第四垂直中心線M4係指分別垂直於第一凹槽22的底部和第二凹槽24的底部並且分別把第一凹槽22和第二凹槽24左右平分的基準線。第三垂直中心線M3和第四垂直中心線M4之間具有一第二距離D2,接著計算第一距離D1和第二距離D2之間的差值以獲得一偏移量X。此外,第一材料層20在小溝渠14相對兩側的側壁上厚度相同,所以第二凹槽24的第四垂直中心線M4之位置係和小溝渠14的第二垂直中心線M2之位置重合。而因為第一材料層20在第一大溝渠12兩側的厚度不同,因此在第一材料層20沉積之後,第一凹槽22所形成的對準標記其位置就和第一大溝渠12所形成的對準標記的位置不同,也就是說第一凹槽22的第三垂直中心線M3就會和第一垂直中心線M1位置不同,進而造成偏移量X。As shown in FIG. 3, the first material layer 20 is planarized so that the thickness of the first material layer 20 on the upper surface of the first substrate 10 becomes smaller, for example, after planarization, the first material layer 20 is on the substrate 10 The thickness of the surface is preferably 10 nm. Then, the position of a third vertical center line M3 of the first groove 22 and the position of a fourth vertical center line M4 of the second groove 24 are detected, wherein the third vertical center line M3 and the fourth vertical center line M4 refers to a reference line that is perpendicular to the bottom of the first groove 22 and the bottom of the second groove 24 and bisects the first groove 22 and the second groove 24, respectively. There is a second distance D2 between the third vertical center line M3 and the fourth vertical center line M4, and then the difference between the first distance D1 and the second distance D2 is calculated to obtain an offset X. In addition, the first material layer 20 has the same thickness on the sidewalls of the opposite sides of the small trench 14, so the position of the fourth vertical centerline M4 of the second groove 24 coincides with the position of the second vertical centerline M2 of the small trench 14 . Since the thickness of the first material layer 20 on both sides of the first large trench 12 is different, after the first material layer 20 is deposited, the alignment mark formed by the first groove 22 is positioned to be the same as that of the first large trench 12 The positions of the formed alignment marks are different, that is to say, the position of the third vertical center line M3 of the first groove 22 is different from the position of the first vertical center line M1, thereby causing an offset X.

如第4圖所示,選擇地形成一第二材料層26順應地覆蓋第一大溝渠12和小溝渠14並且全面覆蓋第一基底10的上表面,小溝渠14的第二凹槽24會被第二材料層26填滿。第二材料層26較佳為磁穿隧接面(magnetic tunnel junction, MTJ)的複合材料層。舉例而言第二材料層26包含有鐵磁性材料和絶緣層。鐵磁性材料例如為鈷、鉑、鈷/鎳合金、鈷/鈀合金、鐵/硼合金、鈷/鉑合金、釓(Gd)/ 鐵合金、鈷鐵合金、鈷/鐵/硼合金或鉭/鐵/鈷合金。絶緣層可以為氧化鎂(MgO)或氧化鋁(Al 2O 3)。但依據產品需求不同第二材料層26可以是其它材料,例如半導體材料、絶緣層或金屬。 As shown in FIG. 4, a second material layer 26 is selectively formed to conform to cover the first large trench 12 and the small trench 14 and fully cover the upper surface of the first substrate 10, and the second groove 24 of the small trench 14 will be The second material layer 26 is filled. The second material layer 26 is preferably a composite material layer of a magnetic tunnel junction (MTJ). For example, the second material layer 26 includes a ferromagnetic material and an insulating layer. Ferromagnetic materials are, for example, cobalt, platinum, cobalt/nickel alloy, cobalt/palladium alloy, iron/boron alloy, cobalt/platinum alloy, gadolinium/iron alloy, cobalt-iron alloy, cobalt/iron/boron alloy or tantalum/iron/ Cobalt alloy. The insulating layer may be magnesium oxide (MgO) or aluminum oxide (Al 2 O 3 ). However, depending on product requirements, the second material layer 26 may be other materials, such as semiconductor materials, insulating layers, or metals.

接著形成一光阻層28全面覆蓋第二材料層26,之後將偏移量X輸入一曝光機台27校正一光罩30位置後,曝光光阻層28。一般而言光罩30位置應該對準第一大溝渠12的位置,但是因為第一材料層20在第一大溝渠12兩側的厚度不同,因此在第一材料層20疊加在第一大溝渠12之後,所形成的第一凹槽22的位置和第一大溝渠12不同,造成光罩30對不準。此外因為第一材料層20在第一大溝渠12兩側的厚度不同,因此在第一材料層20形成之後,第一凹槽22的第三垂直中心線M3和第一垂直中心線M1位置不同,但之後形成的第二材料層26其整體的厚度都相同,所以第二材料層26在第一大溝渠12中所形成的凹槽,其垂直中心線的位置就是第三垂直中心線M3的位置。也就是說在第二材料層26形成後,曝光機台27會以第三垂直中心線M3來定位,但這是不正確的位置,所以本發明藉由輸入偏移量X至曝光機台27,將偵測到的第三垂直中心線M3之位置校正回第一垂直中心線M1的位置後,也就是第一大溝渠12所形成的對準標記的位置,就可以把光罩30調整為正確位置。Next, a photoresist layer 28 is formed to fully cover the second material layer 26, and then the offset X is input to an exposure machine 27 to correct the position of a photomask 30, and then the photoresist layer 28 is exposed. Generally speaking, the position of the photomask 30 should be aligned with the position of the first large trench 12, but because the thickness of the first material layer 20 on both sides of the first large trench 12 is different, the first material layer 20 is superimposed on the first large trench After 12, the position of the first groove 22 formed is different from that of the first large trench 12, resulting in misalignment of the photomask 30. In addition, because the thickness of the first material layer 20 on both sides of the first large trench 12 is different, after the first material layer 20 is formed, the positions of the third vertical center line M3 and the first vertical center line M1 of the first groove 22 are different , But the second material layer 26 formed later has the same overall thickness, so the vertical centerline of the groove formed in the first large trench 12 by the second material layer 26 is the third vertical centerline M3 position. That is to say, after the second material layer 26 is formed, the exposure machine 27 will be positioned with the third vertical center line M3, but this is an incorrect position, so the present invention inputs the offset X to the exposure machine 27 After correcting the detected position of the third vertical center line M3 back to the position of the first vertical center line M1, that is, the position of the alignment mark formed by the first large trench 12, the reticle 30 can be adjusted to Correct location.

根據本發明的另一較佳實施例,也可以不形成第二材料層26,就直接形成光阻層28,然後輸入偏移量X至曝光機台27校正光罩30的位置。According to another preferred embodiment of the present invention, the photoresist layer 28 may be directly formed without forming the second material layer 26, and then the offset X is input to the exposure machine 27 to correct the position of the photomask 30.

如第5圖所示,將光阻層28顯影後形成一圖案化光阻層32。如第6圖所示,以圖案化光阻層32為遮罩,蝕刻第二材料層26、第一材料層20和緩衝層16,最後移除圖案化光阻層32。As shown in FIG. 5, the photoresist layer 28 is developed to form a patterned photoresist layer 32. As shown in FIG. 6, using the patterned photoresist layer 32 as a mask, the second material layer 26, the first material layer 20 and the buffer layer 16 are etched, and finally the patterned photoresist layer 32 is removed.

如前文所述,第一材料層20厚度的分佈狀況會因為第一大溝渠12在第一基底10不同的位置而改變,所以上面獲得偏移量X的方法可以重覆進行,以得到在第一基底10上位於不同座標軸位置的第一大溝渠12其經過物理氣相沉積後所發生的不同偏移量。As described above, the distribution of the thickness of the first material layer 20 will change because the first large trench 12 is at different positions on the first substrate 10, so the above method of obtaining the offset X can be repeated to obtain the The first large trench 12 on a substrate 10 at different coordinate axis positions undergoes different offsets after physical vapor deposition.

從第一基底10得到偏移量X後,可將偏移量X使用於另一片基底。第7圖至第10圖為根據本發明之第二較佳實施例所繪示的偏移量的校正方法。After the offset X is obtained from the first substrate 10, the offset X can be used for another substrate. 7 to 10 are the offset correction methods according to the second preferred embodiment of the present invention.

如第7圖所示,提供一第二基底50其上設置有一第二大溝渠52,第一大溝渠12和第二大溝渠52的大小相同並且第一大溝渠12在第一基底10上的座標軸位置和第二大溝渠52在第二基底50上的座標軸位置相同,也就是說在曝光機台上,第一大溝渠12的第一垂直中心線M1和第二大溝渠52的垂直中心線(圖未示)會被曝光機台認為在相同位置。第二基底50和第一基底10大小相同,第二基底50係用於正式製作半導體元件用的基底,其上沒有設置如同第一基底10上的小溝渠14。接著形成一緩衝層56覆蓋第二大溝渠52的側壁和底部,然後進行一物理氣相沉積製程58,形成一第三材料層60填入第二大溝渠52,第三材料層60和第一材料層20的厚度和材料相同,也就是說第三材料層60在第二大溝渠52的相對兩個側壁上的厚度也是不同。As shown in FIG. 7, a second substrate 50 is provided on which a second large trench 52 is provided, the first large trench 12 and the second large trench 52 are the same size and the first large trench 12 is on the first substrate 10 The coordinate axis position is the same as the coordinate axis position of the second large ditch 52 on the second substrate 50, that is to say, on the exposure machine, the first vertical center line M1 of the first large ditch 12 and the vertical center line of the second large ditch 52 (Not shown) will be considered to be in the same position by the exposure machine. The second substrate 50 and the first substrate 10 have the same size. The second substrate 50 is a substrate used for the formal production of semiconductor devices, and the small trench 14 on the first substrate 10 is not provided thereon. Next, a buffer layer 56 is formed to cover the sidewalls and bottom of the second large trench 52, and then a physical vapor deposition process 58 is performed to form a third material layer 60 to fill the second large trench 52, the third material layer 60 and the first The thickness of the material layer 20 is the same as the material, that is to say, the thickness of the third material layer 60 on the two opposite sidewalls of the second large trench 52 is also different.

如第8圖所示,選擇性地形成一第四材料層66順應地覆蓋第二大溝渠52並且全面覆蓋第二基底50的上表面,第四材料層66和第二材料層26的厚度和材料相同。接著形成一光阻層68全面覆蓋第四材料層66。然後將由第一基底10得到的偏移量X輸入曝光機台27校正光罩30’位置後,曝光光阻層68。如第9圖所示,將光阻層68顯影後形成一圖案化光阻層72,如第10圖所示接著以圖案化光阻層72為遮罩,蝕刻第四材料層66、第三材料層60和緩衝層56,最後移除圖案化光阻層72。As shown in FIG. 8, a fourth material layer 66 is selectively formed to conformally cover the second large trench 52 and fully cover the upper surface of the second substrate 50. The thicknesses of the fourth material layer 66 and the second material layer 26 and The material is the same. Next, a photoresist layer 68 is formed to fully cover the fourth material layer 66. Then, the offset X obtained from the first substrate 10 is input to the exposure machine 27 to correct the position of the photomask 30', and the photoresist layer 68 is exposed. As shown in FIG. 9, the photoresist layer 68 is developed to form a patterned photoresist layer 72. As shown in FIG. 10, the patterned photoresist layer 72 is used as a mask to etch the fourth material layer 66 and the third The material layer 60 and the buffer layer 56 finally remove the patterned photoresist layer 72.

第11圖為根據本發明之第三較佳實施例所繪示的未校正偏移量的圖案化光阻層位置之示意圖,其中具相同功能的元件將延用第二較佳實施例中的元件標號。如第11圖所示,提供另一個第二基底50,第三材料層60填入第二大溝渠52中形成一凹槽62,由於曝光機台沒有偏移量X的校正,所以光罩的對齊位置是以凹槽62的位置為對準標記,也就是以第三材料層60中的凹槽62之第五垂直中心線M5為基準,第五垂直中心線M5為垂直凹槽62的底部並且把凹槽62左右平分的基準線。和第9圖的圖案化光阻72位置相較,第11圖最後曝光顯影後的圖案化光阻72’位置會有偏移。FIG. 11 is a schematic diagram of the position of a patterned photoresist layer with an uncorrected offset according to a third preferred embodiment of the present invention, in which elements with the same function will continue to be used in the second preferred embodiment Component label. As shown in FIG. 11, another second substrate 50 is provided, and the third material layer 60 is filled into the second large trench 52 to form a groove 62. Since the exposure machine has no correction for the offset X, the mask The alignment position is based on the position of the groove 62 as the alignment mark, that is, based on the fifth vertical center line M5 of the groove 62 in the third material layer 60, and the fifth vertical center line M5 is the bottom of the vertical groove 62 And the reference line that divides the groove 62 right and left. Compared with the position of the patterned photoresist 72 in Fig. 9, the position of the patterned photoresist 72' after the final exposure and development in Fig. 11 is shifted.

本發明偏移量的測量方法適用於所有以物理氣相沉積製程所形成的材料層,不只限於上文中所提到的材料,本發明可適用於其它例如溝渠式電晶體、溝渠式電容、溝渠式絶緣結構等的製作,只要是製程中有溝渠加上物理氣相沉積製程形成的材料沉積於溝渠中,之後的曝光製程都可以搭配本發明之方法。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The method for measuring the offset of the present invention is applicable to all material layers formed by a physical vapor deposition process, and is not limited to the materials mentioned above. The present invention can be applied to other trench transistors, trench capacitors, trenches, etc. As long as the manufacturing process of the insulating structure and the like is made by depositing the material formed by the trench and the physical vapor deposition process in the trench, the subsequent exposure process can be matched with the method of the present invention. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10:第一基底 12:第一大溝渠 14:小溝渠 16:緩衝層 18:物理氣相沉積製程 20:第一材料層 22:第一凹槽 24:第二凹槽 26:第二材料層 27:曝光機台 28:光阻層 30:光罩 30’:光罩 32:圖案化光阻層 50:第二基底 52:第二大溝渠 56:緩衝層 58:物理氣相沉積製程 60:第三材料層 62:凹槽 66:第四材料層 68:光阻層 72:圖案化光阻 72’:圖案化光阻 D1:第一距離 D2:第二距離 M1:第一垂直中心線 M2:第二垂直中心線 M3:第三垂直中心線 M4:第四垂直中心線 M5:第五垂直中心線 X:偏移量10: The first base 12: The first big ditch 14: Small ditch 16: Buffer layer 18: Physical vapor deposition process 20: first material layer 22: First groove 24: second groove 26: Second material layer 27: Exposure machine 28: photoresist layer 30: Mask 30’: Mask 32: Patterned photoresist layer 50: second base 52: The second largest ditch 56: buffer layer 58: Physical vapor deposition process 60: third material layer 62: groove 66: fourth material layer 68: photoresist layer 72: Patterned photoresist 72’: Patterned photoresist D1: First distance D2: Second distance M1: first vertical centerline M2: Second vertical centerline M3: Third vertical centerline M4: Fourth vertical centerline M5: Fifth vertical centerline X: offset

第1圖至第6圖為根據本發明之第一較佳實施例所繪示的物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法。 第7圖至第10圖為根據本發明之第二較佳實施例所繪示的物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法。 第11圖為根據本發明之第三較佳實施例所繪示的圖案化光阻發生偏移狀況的示意圖。 FIGS. 1 to 6 are a method for measuring the offset of the physical vapor deposition material layer and a method for correcting the offset according to the first preferred embodiment of the present invention. 7 to 10 are a method for measuring the offset of the physical vapor deposition material layer and a method for correcting the offset according to the second preferred embodiment of the present invention. FIG. 11 is a schematic diagram showing that the patterned photoresist is shifted according to the third preferred embodiment of the present invention.

10:第一基底 10: The first base

12:第一大溝渠 12: The first big ditch

14:小溝渠 14: Small ditch

16:緩衝層 16: Buffer layer

20:第一材料層 20: first material layer

22:第一凹槽 22: First groove

24:第二凹槽 24: second groove

D1:第一距離 D1: First distance

D2:第二距離 D2: Second distance

M1:第一垂直中心線 M1: first vertical centerline

M3:第三垂直中心線 M3: Third vertical centerline

M4:第四垂直中心線 M4: Fourth vertical centerline

X:偏移量 X: offset

Claims (8)

一種物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,包含: 提供一第一基底,其中至少一第一大溝渠和至少一小溝渠埋入該第一基底,該第一大溝渠具有一第一垂直中心線,該小溝渠具有一第二垂直中心線,其中該第一垂直中心線和該第二垂直中心線之間具有一第一距離; 進行一第一物理氣相沉積製程,以形成一第一材料層填入該第一大溝渠和該小溝渠,其中該第一材料層在該第一大溝渠中形成一第一凹槽,在該小溝渠中形成一第二凹槽,該第一材料層在該第一大溝渠的相對兩個側壁上的厚度不同; 偵測該第一凹槽的一第三垂直中心線之位置並且偵測該第二凹槽的一第四垂直中心線之位置,其中該第三垂直中心線和該第四垂直中心線之間具有一第二距離;以及 計算該第一距離和該第二距離之間的差值以獲得一偏移量。 A physical vapor deposition material layer offset measurement method and offset correction method, including: A first substrate is provided, wherein at least one first large ditch and at least one small ditch are buried in the first substrate, the first large ditch has a first vertical centerline, and the small ditch has a second vertical centerline, wherein There is a first distance between the first vertical centerline and the second vertical centerline; Performing a first physical vapor deposition process to form a first material layer to fill the first large trench and the small trench, wherein the first material layer forms a first groove in the first large trench, in A second groove is formed in the small trench, and the thickness of the first material layer on two opposite sidewalls of the first large trench is different; Detecting the position of a third vertical center line of the first groove and detecting the position of a fourth vertical center line of the second groove, wherein between the third vertical center line and the fourth vertical center line Have a second distance; and The difference between the first distance and the second distance is calculated to obtain an offset. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,另包含:在偵測該第三垂直中心線之位置和該第四垂直中心線之位置之前,進行一平坦化製程以去除部分之該第一材料層。The method for measuring the offset of the physical vapor deposition material layer and the method for correcting the offset as described in claim 1 further include: detecting the position of the third vertical centerline and the fourth vertical centerline Before the position, a planarization process is performed to remove part of the first material layer. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,其中在獲得該偏移量之後,另包含: 形成一第二材料層填入該第一大溝渠和該小溝渠並且全面覆蓋該第一基底的上表面; 形成一光阻層全面覆蓋該第二材料層: 將該偏移量輸入一曝光機台校正一光罩位置後,曝光該光阻層; 將該光阻層顯影後形成一圖案化光阻層;以及 以該圖案化光阻層為遮罩,蝕刻該第一材料層和該第二材料層。 The method for measuring the offset of the physical vapor deposition material layer and the method for correcting the offset as described in claim 1, wherein after obtaining the offset, the method further includes: Forming a second material layer to fill the first large trench and the small trench and fully cover the upper surface of the first substrate; Form a photoresist layer to fully cover the second material layer: After inputting the offset into an exposure machine to correct the position of a photomask, expose the photoresist layer; Developing the photoresist layer to form a patterned photoresist layer; and Using the patterned photoresist layer as a mask, the first material layer and the second material layer are etched. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,其中在獲得該偏移量之後,另包含: 提供一第二基底其上設置有一第二大溝渠,該第一大溝渠和該第二大溝渠的大小相同並且該第一大溝渠在該第一基底上的座標軸位置和該第二大溝渠在該第二基底上的座標軸位置相同,該第二基底和該第一基底大小相同; 進行一第二物理氣相沉積製程,形成一第三材料層填入該第二大溝渠,其中該第三材料層和該第一材料層的厚度和材料相同,該第三材料層在該第二大溝渠的相對兩個側壁上的厚度不同; 形成一光阻層全面覆蓋該第三材料層: 將該偏移量輸入一曝光機台校正一光罩位置後,曝光該光阻層; 將該光阻層顯影後形成一圖案化光阻層;以及 以該圖案化光阻層為遮罩,蝕刻該第三材料層。 The method for measuring the offset of the physical vapor deposition material layer and the method for correcting the offset as described in claim 1, wherein after obtaining the offset, the method further includes: A second base is provided on which a second large ditch is provided, the first large ditch and the second large ditch are of the same size and the coordinate axis position of the first large ditch on the first base and the second large ditch are The coordinate axis positions on the second substrate are the same, and the second substrate and the first substrate are the same size; A second physical vapor deposition process is performed to form a third material layer to fill the second large trench, wherein the third material layer and the first material layer have the same thickness and material, and the third material layer is in the first The thickness of the two opposite side walls of the two major ditches is different; A photoresist layer is formed to fully cover the third material layer: After inputting the offset into an exposure machine to correct the position of a photomask, expose the photoresist layer; Developing the photoresist layer to form a patterned photoresist layer; and Using the patterned photoresist layer as a mask, the third material layer is etched. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,其中該小溝渠的開口寬度與該第一材料層的厚度比值較佳大於2.5。The method for measuring the offset of the physical vapor deposition material layer and the method for correcting the offset as described in claim 1, wherein the ratio of the opening width of the small trench to the thickness of the first material layer is preferably greater than 2.5. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,其中該第一大溝渠和該小溝渠的深度相同。The method for measuring the offset of the physical vapor deposition material layer and the method for correcting the offset as described in claim 1, wherein the depths of the first large trench and the small trench are the same. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,其中該小溝渠的高與寬的比值介於0.333~1.066之間。The method for measuring the offset of the physical vapor deposition material layer and the method for correcting the offset as described in claim 1, wherein the ratio of the height and width of the small trench is between 0.333 and 1.066. 如請求項1所述之物理氣相沉積材料層的偏移量的測量方法以及偏移量的校正方法,其中該第一大溝渠的高與寬的比值介於0.038~0.123之間。The method for measuring the offset of the physical vapor deposited material layer and the method for correcting the offset as described in claim 1, wherein the ratio of the height and width of the first large trench is between 0.038 and 0.123.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5807761A (en) * 1995-07-24 1998-09-15 International Business Machines Corporation Method for real-time in-situ monitoring of a trench formation process
TW538491B (en) * 2001-04-02 2003-06-21 Advanced Micro Devices Inc In-situ thickness measurement for use in semiconductor processing
TW544832B (en) * 2001-02-16 2003-08-01 Boxer Cross Inc Evaluating sidewall coverage in a semiconductor wafer
US7019519B2 (en) * 2000-04-07 2006-03-28 Cuong Duy Le Thickness estimation using conductively related calibration samples
US20150371847A1 (en) * 2014-06-20 2015-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Method for controlling semiconductor deposition operation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5807761A (en) * 1995-07-24 1998-09-15 International Business Machines Corporation Method for real-time in-situ monitoring of a trench formation process
US7019519B2 (en) * 2000-04-07 2006-03-28 Cuong Duy Le Thickness estimation using conductively related calibration samples
TW544832B (en) * 2001-02-16 2003-08-01 Boxer Cross Inc Evaluating sidewall coverage in a semiconductor wafer
TW538491B (en) * 2001-04-02 2003-06-21 Advanced Micro Devices Inc In-situ thickness measurement for use in semiconductor processing
US20150371847A1 (en) * 2014-06-20 2015-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Method for controlling semiconductor deposition operation

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