JP2015026732A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve manufacturing yield of a semiconductor device by detecting a position of a superposition inspection mark with high accuracy in a photolithography process.SOLUTION: A semiconductor device manufacturing method comprises: forming a mark trench MT on a principal surface of a semiconductor substrate SUB in a superposition inspection mark region, and subsequently filling the inside of the mark trench MT with an insulation film; and subsequently, after forming a gate insulation film GI1 on the principal surface of the semiconductor substrate SUB, removing the gate insulation film GI1 in a low-voltage nMIS region, a low-voltage pMIS region and the superposition inspection mark region by wet etching. In the wet etching, a superposition inspection mark MTI of a recess structure, which is composed of the insulation film filled inside the mark trench MT is formed by performing processing in a manner such that a top face of the insulation film filled inside the mark trench MT reaches a depth of about 20 nm from the principal surface of the semiconductor substrate SUB.

Description

  The present invention relates to a semiconductor device manufacturing technique, and can be suitably used for, for example, a photolithography process which is a manufacturing process of a semiconductor device.

  For example, Japanese Patent Laid-Open No. 2006-13359 (Patent Document 1) discloses a first step including a step of forming a plurality of recesses on the surface of a substrate, a step of selectively forming a film inside the recesses, and the recesses and the vicinity thereof. And a step of locally etching the region to form a step, and a method for manufacturing a semiconductor device is disclosed that uses the position where the step is formed as an alignment mark.

JP 2006-13359 A

  For inspection of overlay accuracy between the mating layer and the exposure layer in the photolithography process, for overlay inspection mark of the mating layer with an insulating film embedded in the groove formed in the substrate and overlay inspection mark of the exposure layer A resist pattern is used. However, when the bottom of the groove of the overlay inspection mark of the mating layer is asymmetric, the detection waveform picks up the signal intensity from the bottom of the groove, so the detection waveform is also asymmetric, and the overlay inspection mark of the mating layer is detected. Accuracy is reduced. Moreover, even when the flatness of the upper surface of the insulating film embedded in the groove of the overlay inspection mark of the mating layer is poor, the detection accuracy of the overlay inspection mark of the mating layer is lowered by the scattered light.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In the method of manufacturing a semiconductor device according to one embodiment, first, a groove is formed in the main surface of the semiconductor substrate in the overlay inspection mark region, and an insulating film is embedded in the groove. Next, a first insulating film is formed on the main surface of the semiconductor substrate in the low-voltage element region, the high-voltage element region, and the overlay inspection mark region. Next, the first insulating film in the low-voltage element region and the overlay inspection mark region is removed by wet etching. During this wet etching, the upper surface of the insulating film embedded in the groove is processed to a depth of about 20 nm from the main surface of the semiconductor substrate, thereby forming an overlay inspection mark having a recess structure. Thereafter, a second insulating film is formed on the main surface of the semiconductor substrate in the low-voltage element region.

  According to one embodiment, the manufacturing yield of the semiconductor device can be improved by accurately detecting the position of the overlay inspection mark in the photolithography process.

Memory region, peripheral circuit region (low voltage system nMIS region, low voltage system pMIS region, high voltage system nMIS region, and high voltage system pMIS region) showing the manufacturing process of the semiconductor device according to the first embodiment, and an essential part of overlay inspection mark region It is sectional drawing. FIG. 2 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 1; FIG. 3 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 2; FIG. 4 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 3; FIG. 5 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 4; FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 5; FIG. 7 is an essential part cross-sectional view of the same place as that in FIG. 1 during the manufacturing process of the semiconductor device, following FIG. 6; FIG. 8 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 7; FIG. 9 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 8; FIG. 10 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 9; FIG. 11 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 10; FIG. 12 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 11; (A) And (b) is the principal part top view and principal part sectional drawing which show the overlay inspection mark of the to-be-matched layer by Embodiment 1, and the resist pattern for overlay inspection marks of an exposure layer, respectively (same figure ( It is sectional drawing along the AA line shown to a). FIG. 3 is a cross-sectional view and a detection waveform of a main part of an overlay inspection mark for a layer to be bonded according to the first embodiment, and a cross-sectional view and a detection waveform of a main part of an overlay inspection mark for a layer to be bonded according to a comparative example. FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 12; FIG. 16 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 15; FIG. 17 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 16; FIG. 18 is an essential part cross-sectional view of the same place as that in FIG. 1 during the manufacturing process of the semiconductor device, following FIG. 17; FIG. 19 is an essential part cross-sectional view of the same place as that in FIG. 1 during the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is an essential part cross-sectional view of the same place as that in FIG. 1 during the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 20; Memory area, peripheral circuit area (low voltage system nMIS area, low voltage system pMIS area, high voltage system nMIS area, and high voltage system pMIS area) showing the manufacturing process of the semiconductor device according to the second embodiment, and the main part of the overlay inspection mark area It is sectional drawing. FIG. 23 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 22; FIG. 24 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 23; FIG. 25 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 24; FIG. 26 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 25; FIG. 27 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 26; FIG. 28 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 27; FIG. 29 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 28; FIG. 10 is a cross-sectional view of a main part and a detection waveform of an overlay inspection mark for a layer to be bonded according to a second embodiment. FIG. 30 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 29; FIG. 33 is an essential part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 31; FIG. 33 is an essential part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 32; FIG. 34 is an essential part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 33; FIG. 35 is an essential part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 34; FIG. 36 is a principal part cross-sectional view of the same place as in FIG. 22 in the process of manufacturing the semiconductor device, following FIG. 35;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS. Of course, MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cells described in the following embodiments are also included in the subordinate concept of the MIS.

In the following embodiments, when referring to silicon nitride, silicon nitride, or silicon nitride, not only Si ₃ N ₄ but also silicon nitride is used and includes an insulating film having a similar composition. . In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

(Embodiment 1)
A method of manufacturing a semiconductor device according to the first embodiment will be described in the order of steps with reference to FIGS. In the first embodiment, an overlay inspection mark used in a photolithography process which is a manufacturing process of a semiconductor device having a MONOS type nonvolatile memory cell will be described. Further, as the nonvolatile memory cell, a split-gate memory cell having a two-transistor structure in which a sidewall-shaped memory nMIS memory gate electrode is formed on one side surface of the selection nMIS selection gate electrode is illustrated.

  1 to 12 and FIGS. 15 to 21 illustrate a memory region, a peripheral circuit region (low-voltage nMIS region, low-voltage pMIS region, high-voltage nMIS region, and high-voltage system) during the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view of a main part of a pMIS region) and an overlay inspection mark region. In the memory region and the peripheral circuit region, a sectional view in the gate length direction is shown. The MISFET formed in the peripheral circuit region constitutes a processor such as a CPU, a logic circuit, an input / output circuit, a decoder, and a booster circuit. FIGS. 13A and 13B are a plan view and a cross-sectional view of the relevant part showing the overlay inspection mark for the layer to be bonded and the resist pattern for overlay inspection mark for the exposure layer according to the first embodiment, respectively. It is sectional drawing along the AA line shown to a figure (a). FIG. 14 is a cross-sectional view and a detection waveform of the main part of the overlay inspection mark for the mating layer according to the first embodiment, and a cross-sectional view and a detection waveform of the main part of the overlay inspection mark for the mating layer according to the comparative example.

  First, as shown in FIG. 1, a silicon oxide film SO1 and a silicon nitride film SN1 are sequentially formed on the main surface of a semiconductor substrate (planar substantially circular semiconductor thin plate called a semiconductor wafer in this stage) SUB. The silicon oxide film SO1 is formed by, for example, a thermal oxidation method, and the silicon nitride film SN1 is formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Subsequently, the silicon nitride film SN1 and the silicon oxide film SO1 at predetermined positions where the element isolation portion and the overlay inspection mark are formed are removed by dry etching using the resist pattern as a mask. Further, the isolation groove ST is formed at a predetermined position of the semiconductor substrate SUB where the element isolation portion is formed, and the mark groove MT is formed at a predetermined position of the semiconductor substrate SUB where the overlay inspection mark is formed. Thereafter, the resist pattern is removed.

  The overlay inspection mark area where the overlay inspection mark is formed is arranged, for example, in a scribe area. In plan view, the mark groove MT has a square frame shape (see FIG. 13 described later). The width of the mark groove MT is 2 μm, for example, and the depth of the mark groove MT from the main surface of the semiconductor substrate SUB is 300 to 350 nm, for example.

  Next, as shown in FIG. 2, an insulating film is deposited on the main surface of the semiconductor substrate SUB, and further, the insulating film is left so as to remain only in the isolation trench ST and in the mark trench MT. The film is polished by a CMP (Chemical Mechanical Polishing) method or the like. Thus, an element isolation portion STI made of an insulating film embedded in the isolation trench ST is formed so as to surround the active region. An overlay inspection mark MTI made of an insulating film embedded in the mark groove MT is formed in the overlay inspection mark region.

The insulating film embedded in the isolation trench ST and the mark trench MT is, for example, a silicon oxide film, and uses TEOS (Tetra Ethyl Ortho Silicate; Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as a source gas. Deposited by plasma CVD method.

  Next, as shown in FIG. 3, after removing the silicon nitride film SN1, an n-type buried well NISO is formed by selectively ion-implanting n-type impurities into the semiconductor substrate SUB in the peripheral circuit region. Subsequently, a p-type well WHp is formed by selectively ion-implanting a p-type impurity into the semiconductor substrate SUB in the memory region and the high-voltage nMIS region, and an n-type impurity is selected in the semiconductor substrate SUB in the high-voltage pMIS region. An n-type well WHn is formed by ion implantation. Similarly, a p-type well WLp is formed by selectively ion-implanting p-type impurities into the semiconductor substrate SUB in the low-voltage nMIS region, and n-type impurities are selectively ionized into the semiconductor substrate SUB in the low-voltage pMIS region. By implanting, an n-type well WLn is formed.

  Next, predetermined impurities are ion-implanted into the semiconductor substrate SUB in the memory region. Thereby, a semiconductor region Cc for channel formation of the selection nMIS is formed. Similarly, a predetermined impurity is ion-implanted into each semiconductor substrate SUB in the low-voltage nMIS region, the low-voltage pMIS region, the high-voltage nMIS region, and the high-voltage pMIS region in the peripheral circuit region. Thus, semiconductor regions CLn, CLp, CHn, and CHp for channel formation are formed on the respective semiconductor substrates SUB of the low-voltage nMIS region, the low-voltage pMIS region, the high-voltage nMIS region, and the high-voltage pMIS region in the peripheral circuit region. .

  Next, after removing the silicon oxide film SO1 by wet etching, the semiconductor substrate SUB is subjected to an oxidation process, thereby forming a gate insulating film GI1 made of, for example, silicon oxide on the main surface of the semiconductor substrate SUB. The thickness of the gate insulating film GI1 is, for example, 20 nm.

  Next, as shown in FIG. 4, the gate insulating film GI1 in the memory region, the low-pressure nMIS region, the low-pressure pMIS region, and the overlay inspection mark region is removed by wet etching. At this time, wet etching is performed until the upper surface of the insulating film embedded in the mark groove MT in the overlay inspection mark region reaches a predetermined depth from the main surface of the semiconductor substrate SUB. That is, the overlay inspection mark MTI has a recess structure (concave structure) whose upper surface is recessed. The depth (recess amount) from the main surface of the semiconductor substrate SUB to the upper surface of the insulating film embedded in the mark groove MT is, for example, 15 to 25 nm. Since the overlay inspection mark MTI has a recess structure, the element isolation portion STI in the memory region, the low-voltage nMIS region, and the low-voltage pMIS region also has a recess structure.

  Further, since the upper surface of the insulating film embedded in the mark groove MT is processed by wet etching, the insulating film embedded in the mark groove MT has a smooth upper surface.

  In the above-mentioned Patent Document 1, a method for manufacturing a semiconductor device using a position where a step is formed as an alignment mark is disclosed. However, a plurality of steps for forming the alignment mark are required. On the other hand, in the first embodiment, the overlay inspection mark MTI has a recess structure having a recess by using an etching process when two types of gate insulating films having different thicknesses are formed. Therefore, the recess structure of the overlay inspection mark MTI can be realized without increasing the number of processes.

  Next, as shown in FIG. 5, the semiconductor substrate SUB is oxidized. Thus, the gate insulating film GI2 made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate SUB in the memory region, the low-pressure nMIS region, the low-pressure pMIS region, and the overlay inspection mark region. The thickness of the gate insulating film GI2 is, for example, 1 to 5 nm.

  Next, as shown in FIG. 6, a conductive film SI made of, for example, amorphous silicon is deposited on the main surface of the semiconductor substrate SUB by a CVD method. The thickness of the conductive film SI is, for example, 150 nm. Subsequently, an n-type conductive film SIn1 is formed by introducing an n-type impurity into the conductive film SI in the memory region by an ion implantation method or the like.

  Next, as shown in FIG. 7, the n-type conductive film SIn1 in the memory region is processed by dry etching using the resist pattern as a mask. Thus, the selection gate electrode CG of the selection nMIS made of the n-type conductive film SIn1 is formed in the memory region. The gate length of the selection gate electrode CG in the memory region is, for example, 100 nm. Thereafter, the resist pattern is removed.

  Next, an n-type impurity, for example, arsenic or phosphorus is ion-implanted into the main surface of the semiconductor substrate SUB in the memory region using the selection gate electrode CG of the selection nMIS and the resist pattern as a mask, thereby forming a channel for the memory nMIS. N-type semiconductor region Cm is formed. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 8, on the main surface of the semiconductor substrate SUB, for example, a lower insulating film Ib made of silicon oxide, a charge storage layer CSL having a trap level made of silicon nitride, and an upper layer made of silicon oxide. The insulating films It are sequentially formed. The lower insulating film Ib is formed by, for example, a thermal oxidation method or an ISSG (In-Situ Steam Generation) oxidation method, and the thickness thereof is, for example, 1 to 10 nm. The charge storage layer CSL is formed by, for example, a CVD method and has a thickness of, for example, 5 to 20 nm. The upper insulating film It is formed by, for example, a CVD method or an ISSG oxidation method, and has a thickness of, for example, 4 to 15 nm. The insulating films Ib and It may be a silicon oxide film containing nitrogen, and the charge storage layer CSL has a dielectric higher than that of the silicon nitride film, such as an aluminum oxide (alumina) film, a hafnium oxide film, or a tantalum oxide film. A high dielectric constant film having a constant may be used.

  Next, an n-type conductive film made of, for example, low-resistance polycrystalline silicon is deposited on the main surface of the semiconductor substrate SUB. This conductive film is formed by, for example, the CVD method, and the thickness thereof is, for example, 40 to 100 nm. Subsequently, the conductive film is etched back using anisotropic dry etching.

  As a result, as shown in FIG. 9, in the memory region, the sidewall SW1 is formed on both side surfaces of the stacked film including the selection gate electrode CG of the selection nMIS via the insulating films Ib and It and the charge storage layer CSL. .

  Next, as shown in FIG. 10, using the resist pattern as a mask, the sidewall SW1 exposed therefrom is etched. Thus, the memory gate electrode MG (side wall SW1) of the memory nMIS is formed only on one side surface of the selection gate electrode CG of the selection nMIS in the memory region. The gate length of the memory gate electrode MG is, for example, 65 nm. Thereafter, the resist pattern is removed.

  Next, in the memory region, the insulating films Ib and It and the charge storage layer CSL between the select gate electrode CG and the memory gate electrode MG and between the semiconductor substrate SUB and the memory gate electrode MG are left, and other regions are left. The insulating films Ib and It and the charge storage layer CSL are selectively etched.

  Next, as shown in FIG. 11, an n-type conductive film SIn2 is formed by introducing an n-type impurity into the conductive film SI in the low-voltage nMIS region and the high-voltage nMIS region in the peripheral circuit region by an ion implantation method or the like. To do. Further, a p-type conductive film SIp is formed by introducing a p-type impurity into the conductive film SI in the low-voltage pMIS region and the high-voltage pMIS region in the peripheral circuit region by an ion implantation method or the like.

  Next, as shown in FIG. 12, resist patterns RP used for forming the gate electrodes of the low-voltage nMIS, low-voltage pMIS, high-voltage nMIS, and high-voltage pMIS in the peripheral circuit region are formed by photolithography. Form.

  When this resist pattern RP is formed, a registration inspection mark resist pattern MRP is formed in the registration inspection mark region. The overlay inspection mark resist pattern MRP has a square frame shape larger than the overlay inspection mark MTI in plan view (see FIG. 13 described later). Then, the overlay accuracy is inspected using the overlay inspection mark MTI and the overlay inspection mark resist pattern MRP already formed in the overlay inspection mark area.

  FIGS. 13A and 13B are a main part plan view and a main part showing the overlay inspection mark of the mating layer and the resist pattern for the overlay inspection mark of the exposure layer formed in the overlay inspection mark area, respectively. It is sectional drawing.

  When forming the element isolation portion STI, an overlay inspection mark MTI having a square frame shape is formed on the main surface of the semiconductor substrate SUB, and an overlay inspection having a square frame shape larger than the overlay inspection mark MTI. A mark resist pattern MRP is formed so as to overlap the overlay inspection mark MTI. Then, by measuring the relative positional deviation in the plane direction between the overlay inspection mark MTI and the overlay inspection mark resist pattern MRP, the overlay accuracy between the layer to be aligned and the exposure layer is inspected.

  FIG. 14 shows a cross-sectional view and a detected waveform of the main part of the overlay inspection mark of the layer to be bonded according to the first embodiment. Moreover, the principal part sectional drawing and detection waveform of the overlay inspection mark of the to-be-matched layer by a comparative example are shown. The comparative example is an overlay inspection mark in which the upper surface of the insulating film embedded in the mark groove formed in the semiconductor substrate is at substantially the same position as the main surface of the semiconductor substrate.

  The detected waveform obtained from the overlay inspection mark MTI according to the comparative example is easily influenced by the shape of the mark groove MT. For this reason, when the shape of the mark groove MT, in particular, the shape of the bottom surface of the mark groove MT and the depth of the mark groove MT is asymmetric, the detection waveform is also asymmetric, and the position of the overlay inspection mark MTI cannot be obtained accurately.

  On the other hand, the MTI in the overlay inspection mark according to the first embodiment suppresses scattered light from the bottom surface of the mark groove MT in the side wall portion (A region shown in FIG. 14) where the upper surface is depressed. Even if the depth of the mark groove MT is asymmetric, the asymmetry of the detection waveform is eliminated, and the position of the overlay inspection mark MTI can be detected with high accuracy.

  That is, in order to inspect the overlay accuracy of the overlay inspection mark MTI and the overlay inspection mark resist pattern MRP, it is necessary to detect the position of the overlay inspection mark MTI of the layer to be matched with high accuracy. In the first embodiment, as described with reference to FIG. 4 described above, the overlay inspection mark MTI has a recess structure, and an insulating film having a smooth upper surface is embedded in the mark groove MT. Accordingly, since scattered light from the bottom surface of the mark groove MT and scattered light from the top surface of the insulating film embedded in the mark groove MT are suppressed, the detection waveform obtained from the overlay inspection mark MTI has a center position. The waveform has the highest light intensity and good symmetry. Thereby, the position of the overlay inspection mark MTI on the layer to be bonded can be detected with high accuracy.

  In the first embodiment, the depth of the mark groove MT is set to 300 to 350 nm, for example, and the recess amount of the overlay inspection mark is set to 15 to 25 nm, for example. In this case, when the recess amount is 250 nm or more, the shape of the bottom surface of the mark groove MT directly affects the detection waveform. In addition, when the upper surface of the insulating film embedded in the mark groove is wet-etched, the upper surface of the insulating film embedded in the separation groove ST is also wet-etched. There is also a possibility that the function of the element isolation portion STI in the memory region, the low-voltage nMIS region, and the low-voltage pMIS region may deteriorate. For this reason, the control of the recess amount is important, and it is considered that the recess amount is most preferably in the range of 15 to 25 nm with 20 nm as the center value.

  Next, as shown in FIG. 15, using the resist pattern RP as a mask, the conductive films SIn2 and SIp in the peripheral circuit region are processed by dry etching to form a low-voltage nMIS gate electrode GLn and a high-voltage nMIS made of the conductive film SIn2. The gate electrode GHn of the low voltage system pMIS and the gate electrode GHp of the high voltage system pMIS made of the conductive film SIp are formed. The gate length of the gate electrode GLn of the low-voltage nMIS and the gate electrode GLp of the low-voltage pMIS in the active region is, for example, 100 nm, and the gate length of the gate electrode GHn of the high-voltage nMIS and the gate electrode GHp of the high-voltage pMIS is, for example, 400 nm. It is. Thereafter, the resist patterns RP and MRP are removed.

Next, an n-type impurity such as arsenic is ion-implanted into the main surface of the semiconductor substrate SUB using the resist pattern as a mask on the main surface of the semiconductor substrate SUB in the high-voltage nMIS region of the peripheral circuit region. An n ⁻ type semiconductor region HLn is formed on the main surface of the semiconductor substrate SUB in the system nMIS region in a self-aligned manner with respect to the gate electrode GHn. Thereafter, the resist pattern is removed.

Similarly, by ion-implanting a p-type impurity such as boron fluoride into the main surface of the semiconductor substrate SUB in the main surface of the semiconductor substrate SUB in the high-voltage pMIS region of the peripheral circuit region, using the resist pattern as a mask, A p ⁻ -type semiconductor region HLp is formed in a self-aligned manner with respect to the gate electrode GHp on the main surface of the semiconductor substrate SUB in the high-voltage pMIS region. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 16, after an insulating film made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate SUB by a CVD method, the insulating film is etched back using anisotropic dry etching. . Thereby, in the memory region, the sidewalls SW2 are formed on the side surface of the selection gate electrode CG opposite to the memory gate electrode MG and the side surface of the memory gate electrode MG, respectively. Further, in the peripheral circuit region, sidewalls SW2 are formed on both side surfaces of the low-voltage nMIS gate electrode GLn, the low-voltage pMIS gate electrode GLp, the high-voltage nMIS gate electrode GHn, and the high-voltage pMIS gate electrode GHp, respectively. . The spacer length of the sidewall SW2 is, for example, about 6 nm.

  As a result, the exposed side surface of the gate insulating film GI2 between the selection gate electrode CG of the selection nMIS and the semiconductor substrate SUB, and the insulating film Ib between the memory gate electrode MG of the memory nMIS and the semiconductor substrate SUB. , It and the exposed side surface of the charge storage layer CSL can be covered with the sidewall SW2.

Next, a resist pattern whose end is located on the upper surface of the selection gate electrode CG of the memory region selection nMIS and covers a part of the selection gate electrode CG on the memory gate electrode MG side of the memory nMIS and the memory gate electrode MG Then, n − -type impurity, for example, arsenic is ion-implanted into the main surface of the semiconductor substrate SUB using the selection gate electrode CG, the memory gate electrode MG, and the resist pattern as a mask, thereby forming n ^{− on} the main surface of the semiconductor substrate SUB. A type semiconductor region Dn is formed in a self-aligned manner with respect to the select gate electrode CG. Thereafter, the resist pattern is removed.

Next, a resist pattern is formed, the end of which is located on the upper surface of the selection gate electrode CG of the memory region selection nMIS and covers a part of the selection gate electrode CG opposite to the memory gate electrode MG of the memory nMIS. Thereafter, an n-type semiconductor, such as arsenic, is ion-implanted into the main surface of the semiconductor substrate SUB using the selection gate electrode CG, the memory gate electrode MG, and the resist pattern as a mask, thereby forming an n ⁻ type semiconductor on the main surface of the semiconductor substrate SUB. The region Sn is formed in a self-aligned manner with respect to the memory gate electrode MG. Thereafter, the resist pattern is removed.

Here, the n ⁻ type semiconductor region Dn is formed first and then the n ⁻ type semiconductor region Sn is formed. However, the n ⁻ type semiconductor region Sn is formed first and then the n ⁻ type semiconductor region Dn. May be formed. Further, following the ion implantation of the n-type impurity for forming the n ⁻ -type semiconductor region Dn, a p-type impurity such as boron is ion-implanted into the main surface of the semiconductor substrate SUB, and the lower portion of the n ⁻ -type semiconductor region Dn is formed. A p-type semiconductor region may be formed so as to surround it.

Next, as shown in FIG. 17, n-type impurities such as arsenic are ion-implanted into the main surface of the semiconductor substrate SUB in the main surface of the semiconductor substrate SUB in the low-voltage nMIS region in the peripheral circuit region using the resist pattern as a mask. Thus, the n ⁻ type semiconductor region LLn is formed in a self-aligned manner with respect to the gate electrode GLn on the main surface of the semiconductor substrate SUB in the low-voltage nMIS region in the peripheral circuit region. Thereafter, the resist pattern is removed.

Similarly, by ion-implanting a p-type impurity such as boron fluoride into the main surface of the semiconductor substrate SUB on the main surface of the semiconductor substrate SUB in the low-voltage pMIS region of the peripheral circuit region using the resist pattern as a mask, the peripheral circuit region A p ⁻ type semiconductor region LLp is formed in a self-aligned manner with respect to the gate electrode GLp on the main surface of the semiconductor substrate SUB in the low pressure pMIS region. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 18, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially deposited on the main surface of the semiconductor substrate SUB by a CVD method, and these are etched by anisotropic dry etching. Back. Accordingly, in the memory region, the side surface of the selection gate electrode CG opposite to the memory gate electrode MG and the side surface of the memory gate electrode MG, and in the peripheral circuit region, the gate electrode GLn of the low-voltage system nMIS and the gate electrode GLp of the low-voltage system pMIS. Side walls SW3 are formed on both side surfaces of the high-voltage nMIS gate electrode GHn and the high-voltage pMIS gate electrode GHp, respectively. The thickness of the lower silicon oxide film is, for example, 20 nm, the thickness of the silicon nitride film is, for example, 25 nm, and the thickness of the upper silicon oxide film is, for example, 50 nm.

Next, as shown in FIG. 19, a p-type impurity such as boron or boron fluoride is applied to the main surface of the semiconductor substrate SUB in the low-voltage pMIS region and high-voltage pMIS region in the peripheral circuit region, using a resist pattern as a mask. Ions are implanted into the main surface of the SUB. Then, a p ⁺ type semiconductor region Hp is formed in a self-aligned manner with respect to the gate electrode GLp of the low-voltage pMIS and the gate electrode GHp of the high-voltage pMIS. Thus, p ^- type source and drain regions SD of the high-voltage pMIS comprising the semiconductor region HLp and ^{p +} -type semiconductor region Hp is formed of, p ^- type semiconductor regions LLp and ^{p +} -type semiconductor region Hp A source / drain region SD of the low-pressure pMIS consisting of is formed. Thereafter, the resist pattern is removed.

Next, n-type impurities such as arsenic and phosphorus are applied to the main surface of the semiconductor substrate SUB with the resist pattern as a mask on the main surface of the semiconductor substrate SUB in the low-voltage nMIS region and high-voltage nMIS region in the memory region and the peripheral circuit region. Ion implantation. In the memory region, an n ⁺ type semiconductor region Hm is formed in a self-aligned manner with respect to the selection gate electrode CG of the selection nMIS and the memory gate electrode MG of the memory nMIS, and in the peripheral circuit region, a low-voltage nMIS is formed. An n ⁺ -type semiconductor region Hn is formed in a self-aligned manner with respect to the gate electrode GLn and the gate electrode GHn of the high-voltage nMIS. As a result, in the memory region, a drain region Drm composed of an n ⁻ type semiconductor region Dn and an n ⁺ type semiconductor region Hm is formed, and a source region composed of the n ⁻ type semiconductor region Sn and the n ⁺ type semiconductor region Hm. Srm is formed. In the peripheral circuit region, a source / drain region SD of a high voltage nMIS composed of an n ⁻ type semiconductor region HLn and an n ⁺ type semiconductor region Hn is formed, and the n ⁻ type semiconductor region LLn and the n ⁺ type semiconductor region Hn are formed. A source / drain region SD of the low-voltage nMIS composed of the semiconductor region Hn is formed. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 20, in the memory region, a silicide layer is formed on the upper surface of the memory gate electrode MG of the memory nMIS, the upper surface of the selection gate electrode CG of the selection nMIS, and the upper surface of the n ⁺ type semiconductor region Hm. SIL, for example, nickel silicide or cobalt silicide, is formed by a self-alignment method, for example, a salicide (Salicide: Self Align silicide) process. Similarly, in the peripheral circuit region, the upper surface of the gate electrode GLn of the low voltage system nMIS and the upper surface of the n ⁺ type semiconductor region Hn, the upper surface of the gate electrode GLp of the low voltage system pMIS and the upper surface of the p ⁺ type semiconductor region Hp, the high voltage system Silicide layers SIL are formed on the upper surface of the nMIS gate electrode GHn and the upper surface of the n ⁺ -type semiconductor region Hn, and on the upper surface of the gate electrode GHp of the high-voltage pMIS and the upper surface of the p ⁺ -type semiconductor region Hp.

  Next, as shown in FIG. 21, a silicon nitride film SN2 is deposited as an insulating film on the main surface of the semiconductor substrate SUB by a CVD method. This silicon nitride film SN2 functions as an etching stopper when a contact hole described later is formed. Subsequently, after depositing a silicon oxide film SO2 as an insulating film by a CVD method, the silicon oxide film SO2 is polished by a CMP method, thereby forming an interlayer insulating film ILS composed of the silicon nitride film SN2 and the silicon oxide film SO2.

  Next, in the memory region, a contact hole CNT reaching the silicide layer SIL on the drain region Drm is formed in the interlayer insulating film ILS. At the same time, a contact hole CNT reaching the silicide layer SIL on the source region Srm is also formed. However, in FIG. 21, only the contact hole CNT reaching the silicide layer SIL on the drain region Drm is illustrated for the sake of simplicity. Yes.

  At the same time, in the peripheral circuit region, in the low-voltage system nMIS, the low-voltage system pMIS, the high-voltage system nMIS, and the high-voltage system pMIS, on the silicide layer SIL and the source / drain regions SD on the respective gate electrodes GLn, GLp, GHn, GHp. A contact hole CA reaching the silicide layer SIL is formed. In FIG. 21, only the contact hole CA reaching the silicide layer SIL on the source / drain region SD of the low-voltage nMIS, the low-voltage pMIS, the high-voltage nMIS, and the high-voltage pMIS is illustrated for simplification of description.

  Next, plugs PLG are formed in the contact holes CNT and CA. The plug PLG is, for example, a relatively thin barrier film made of a laminated film of titanium and titanium nitride, and a laminated film made of a relatively thick conductive film made of tungsten, aluminum, or the like formed so as to be surrounded by the barrier film. Consists of a membrane.

  After that, by forming a first layer wiring M1 mainly composed of, for example, copper or aluminum on the interlayer insulating film ILS, a memory cell formed in the memory region and a low-voltage system formed in the peripheral circuit region nMIS, low-pressure pMIS, high-pressure nMIS, and high-pressure pMIS are almost completed. Thereafter, an upper layer wiring and the like are further formed, and a semiconductor device having a nonvolatile memory is manufactured through a normal semiconductor device manufacturing process.

  In the first embodiment, the layer to be matched is the step of forming the element isolation portion STI, and the exposure layer is the gate electrode of each of the low-voltage nMIS, low-voltage pMIS, high-voltage nMIS, and high-voltage pMIS in the peripheral circuit region. Although the overlay accuracy inspection as a process of forming GLn, GLp, GHn, and GHp is illustrated, it is not limited to these processes. For example, the present invention can be applied to an overlay accuracy inspection in which the layer to be bonded is a step of forming contact holes CNT and CA, and the exposure layer is a step of forming a first layer wiring M1.

  In the first embodiment, the split gate structure MONOS type nonvolatile memory cell in which the sidewall-shaped memory gate electrode MG is formed on one side surface of the selection gate electrode CG of the selection nMIS is illustrated. It is not limited to this. For example, the overlay inspection described in the first embodiment also applies to the MONOS type nonvolatile memory cell having the split gate structure in which the memory gate electrode MG of the memory nMIS having the sidewall shape is formed on both side surfaces of the selection gate electrode CG of the selection nMIS. Marks can be applied.

  As described above, according to the first embodiment, the overlay inspection mark MTI of the layer to be bonded has a recess structure in which the insulating film having a smooth upper surface is embedded in the mark groove MT. In the inspection of the overlay accuracy between the exposure layer and the exposure layer, the position of the overlay inspection mark MTI can be detected with high accuracy. Thereby, the manufacturing yield of the semiconductor device can be improved. Furthermore, since the overlay inspection mark MTI of the mating layer can be formed without increasing the number of steps in the manufacturing process of the semiconductor device, an increase in manufacturing cost and manufacturing TAT (Turn around time) of the semiconductor device is avoided. can do.

(Embodiment 2)
A method of manufacturing a semiconductor device according to the second embodiment will be described in the order of steps with reference to FIGS. In the second embodiment, an overlay inspection mark used in a photolithography process which is a manufacturing process of a semiconductor device having a MONOS type nonvolatile memory cell will be described. Further, as the nonvolatile memory cell, a single-structure memory cell having a one-transistor structure is illustrated.

  22 to 29 and FIGS. 31 to 36 illustrate a memory region, a peripheral circuit region (low-voltage nMIS region, low-voltage pMIS region, high-voltage nMIS region, and high-voltage system) during the manufacturing process of the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view of a main part of a pMIS region) and an overlay inspection mark region. In the memory region and the peripheral circuit region, a sectional view in the gate length direction is shown. FIG. 30 is a cross-sectional view and a detection waveform of the main part of the overlay inspection mark of the layer to be bonded according to the second embodiment.

  First, as shown in FIG. 22, in the same manner as in the first embodiment described above, a semiconductor in which an isolation inspection mark is formed by forming an isolation trench ST at a predetermined location of a semiconductor substrate SUB where an element isolation portion is to be formed. A mark groove MT is formed at a predetermined location on the substrate SUB.

  The overlay inspection mark area where the overlay inspection mark is formed is arranged, for example, in a scribe area. In plan view, the mark groove MT has a rectangular frame shape (see FIG. 13 described above). The width of the mark groove MT is 2 μm, for example, and the depth of the mark groove MT from the main surface of the semiconductor substrate SUB is 300 to 350 nm, for example.

  Next, an insulating film is deposited on the main surface of the semiconductor substrate SUB, and further, the insulating film is polished by CMP or the like so that the insulating film remains only in the isolation trench ST and the mark trench MT. To do. Thereby, an element isolation portion STI including the isolation trench ST in which the insulating film is embedded is formed so as to surround the active region. In addition, an overlay inspection mark MTI including a mark groove MT in which an insulating film is embedded is formed in the scribe region. The insulating film embedded in the isolation trench ST and the mark trench MT is, for example, a silicon oxide film, and is deposited by a plasma CVD method using TEOS and ozone as source gases.

  Next, as shown in FIG. 23, an n-type buried well NISO is formed by selectively ion-implanting n-type impurities into the semiconductor substrate SUB in the peripheral circuit region. Subsequently, a p-type well WHp is formed by selectively ion-implanting a p-type impurity into the semiconductor substrate SUB in the memory region and the high-voltage nMIS region, and an n-type impurity is selected in the semiconductor substrate SUB in the high-voltage pMIS region. An n-type well WHn is formed by ion implantation. Similarly, a p-type well WLp is formed by selectively ion-implanting p-type impurities into the semiconductor substrate SUB in the low-voltage nMIS region, and n-type impurities are selectively ionized into the semiconductor substrate SUB in the low-voltage pMIS region. By implanting, an n-type well WLn is formed.

  Next, predetermined impurities are ion-implanted into the semiconductor substrate SUB in the memory region. Thereby, a semiconductor region Cc for channel formation is formed in the semiconductor substrate SUB in the memory region. Similarly, a predetermined impurity is ion-implanted into each semiconductor substrate SUB in the low-voltage nMIS region, the low-voltage pMIS region, the high-voltage nMIS region, and the high-voltage pMIS region in the peripheral circuit region. Thus, semiconductor regions CLn, CLp, CHn, and CHp for channel formation are formed on the respective semiconductor substrates SUB of the low-voltage nMIS region, the low-voltage pMIS region, the high-voltage nMIS region, and the high-voltage pMIS region in the peripheral circuit region. .

  Next, as shown in FIG. 24, the semiconductor substrate SUB is oxidized to form a gate insulating film GI1 made of, for example, silicon oxide on the main surface of the semiconductor substrate SUB. The thickness of the gate insulating film GI1 is, for example, 20 nm.

  Next, the gate insulating film GI1 in the low-pressure nMIS region and the low-pressure pMIS region is removed by wet etching using the resist pattern as a mask. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 25, the semiconductor substrate SUB is oxidized. Thereby, the gate insulating film GI2 made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate SUB in the low-pressure nMIS region and the low-pressure pMIS region. The thickness of the gate insulating film GI2 is, for example, 1 to 5 nm.

  Next, a conductive film PS1 made of, for example, polycrystalline silicon is deposited on the main surface of the semiconductor substrate SUB by a CVD method. The thickness of the conductive film PS1 is, for example, 150 nm.

  Next, as shown in FIG. 26, the conductive film PS1 and the gate insulating film GI1 in the memory region and the overlay inspection mark region are removed by dry etching using the resist pattern RP0 as a mask. Thereafter, the resist pattern RP0 is removed.

  Next, as shown in FIG. 27, a resist pattern RP1 is formed in a region other than the overlay inspection mark region (memory region, low-pressure nMIS region, low-pressure pMIS region, high-pressure nMIS region, and high-pressure pMIS region). . Subsequently, using this resist pattern RP1 as a mask, wet etching is performed until the upper surface of the insulating film embedded in the mark groove MT in the overlay inspection mark region reaches a predetermined depth from the main surface of the semiconductor substrate SUB. . That is, the overlay inspection mark MTI has a recess structure (concave structure) whose upper surface is recessed. The depth (recess amount) from the main surface of the semiconductor substrate SUB to the upper surface of the insulating film embedded in the mark groove MT is, for example, 150 nm. Thereafter, the resist pattern RP1 is removed.

  By the way, similarly in the first embodiment (the wet etching process described with reference to FIG. 4 described above), the upper surface of the insulating film embedded in the mark groove MT is predetermined from the main surface of the semiconductor substrate SUB. Wet etching is performed until the depth becomes the same. However, in the above-described wet etching process in the first embodiment, the upper surface of the insulating film embedded in the isolation trench ST in the memory region, the low-pressure nMIS region, and the low-pressure pMIS region is also etched. In some cases, an optimum recess amount cannot be obtained for the mark MTI.

  However, in the wet etching process according to the second embodiment, only the insulating film embedded in the mark groove MT is processed by wet etching. Therefore, by controlling the etching amount of this insulating film, an optimal recess amount is obtained. It is possible to obtain with high accuracy.

  Next, as shown in FIG. 28, on the main surface of the semiconductor substrate SUB, for example, a lower insulating film Ib made of silicon oxide, a charge storage layer CSL having a trap level made of silicon nitride, and an upper layer made of silicon oxide. The insulating films It are sequentially formed. The lower insulating film Ib is formed by, for example, a thermal oxidation method or an ISSG oxidation method, and the thickness thereof is, for example, 1 to 10 nm. The charge storage layer CSL is formed by, for example, a CVD method and has a thickness of, for example, 5 to 20 nm. The upper insulating film It is formed by, for example, a CVD method or an ISSG oxidation method, and has a thickness of, for example, 4 to 15 nm. The insulating films Ib and It may be a silicon oxide film containing nitrogen, and the charge storage layer CSL has a dielectric higher than that of the silicon nitride film, such as an aluminum oxide (alumina) film, a hafnium oxide film, or a tantalum oxide film. A high dielectric constant film having a constant may be used.

  Here, the insulating films Ib and It and the charge storage layer CSL are also formed in the overlay inspection mark region. That is, the insulating films Ib and It and the charge storage layer CSL are also formed on the bottom surface and the side wall of the recessed portion following the shape of the recessed portion formed in the overlay inspection mark MTI.

  Next, an n-type conductive film PS2 made of, for example, polycrystalline silicon is deposited on the insulating films Ib and It and the charge storage layer CSL by the CVD method. The thickness of the conductive film PS2 is, for example, 200 nm.

  Next, as shown in FIG. 29, a resist pattern RP2 used for forming a selection gate electrode in the memory region is formed by photolithography. When the resist pattern RP2 is formed, an overlay inspection mark resist pattern MRP2 is formed in the overlay inspection mark region. The overlay inspection mark resist pattern MRP2 has a square frame shape larger than the overlay inspection mark MTI in plan view (see FIG. 13 described above). Then, the overlay accuracy is inspected using the overlay inspection mark MTI and the overlay inspection mark resist pattern MRP2 already formed in the overlay inspection mark area.

  In order to inspect the overlay accuracy between the overlay inspection mark MTI and the overlay inspection mark resist pattern MRP2, it is necessary to accurately detect the position of the overlay inspection mark MTI in the layer to be aligned. As described in the first embodiment, since the overlay inspection mark MTI has a recess structure, the detection waveform obtained from the overlay inspection mark MTI has the strongest light intensity at the center position and symmetry. A good waveform. Thereby, the position of the overlay inspection mark MTI on the layer to be bonded can be detected with high accuracy.

  However, if the variation in the recess amount increases, the variation in the detected signal intensity also increases, so that it may not be possible to obtain a detection waveform having the desired light intensity and symmetry. For example, if the recess amount becomes too large, the shape of the bottom surface of the mark groove MT may directly affect the detected waveform.

  FIG. 30 shows a cross-sectional view of a principal part and a detection waveform of an overlay inspection mark for a layer to be bonded according to the second embodiment. The overlay inspection mark A and the overlay inspection mark B have different recess amounts, the overlay inspection mark A has a recess amount of 300 nm, and the overlay inspection mark B has a recess amount of 150 nm.

  The detected waveform detected at the overlay inspection mark B is a waveform having the highest light intensity at the center position and good symmetry. On the other hand, the detection waveform detected in the overlay inspection mark A is asymmetric due to the influence of the shape of the bottom surface and the side wall of the mark groove MT.

  Thus, in order to obtain a detection waveform with good symmetry, it is important to control the recess amount of the overlay inspection mark MTI. In the second embodiment, as described with reference to FIG. 27 described above, only the insulating film embedded in the mark groove MT is processed by wet etching, so that the etching amount of this insulating film can be easily controlled. Can do. Therefore, since the overlay inspection mark MTI having a structure having an optimal recess amount can be formed, a detection waveform having clear light intensity and symmetry can be obtained, and the position of the overlay inspection mark MTI on the layer to be bonded can be determined. It can be detected with high accuracy.

  Next, as shown in FIG. 31, the n-type conductive film PS2 in the memory region is processed by dry etching using the resist pattern RP2 as a mask. Thereby, the selection gate electrode CG made of the n-type conductive film PS2 is formed in the memory region. The gate length of the selection gate electrode CG in the memory region is, for example, 100 nm. Thereafter, the resist patterns RP2 and MRP2 are removed.

  Next, the insulating films Ib and It and the charge storage layer CSL between the conductive film PS2 and the semiconductor substrate SUB are left in the memory region between the select gate electrode CG and the semiconductor substrate SUB and in the overlay inspection mark region. Then, the insulating films Ib and It and the charge storage layer CSL in other regions are selectively etched.

  Next, as shown in FIG. 32, using the resist pattern as a mask, the conductive film PS1 in the peripheral circuit region is processed by dry etching to form a low-voltage nMIS gate electrode GLn, a low-voltage pMIS gate electrode GLp, and a high-voltage nMIS. Gate electrode GHn and high-voltage pMIS gate electrode GHp are formed. The gate length of the gate electrode GLn of the low-voltage nMIS and the gate electrode GLp of the low-voltage pMIS in the active region is, for example, 100 nm, and the gate length of the gate electrode GHn of the high-voltage nMIS and the gate electrode GHp of the high-voltage pMIS is, for example, 400 nm. It is. Thereafter, the resist pattern is removed.

Next, an n-type impurity, for example, arsenic is ion-implanted into the main surface of the semiconductor substrate SUB using the resist pattern as a mask, so that the n ⁻ -type semiconductor region SDn is selected on the main surface of the semiconductor substrate SUB in the memory region. In a self-aligned manner. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 33, an n-type impurity, for example, arsenic, is ion-implanted into the main surface of the semiconductor substrate SUB on the main surface of the semiconductor substrate SUB in the high-voltage nMIS region in the peripheral circuit region using the resist pattern as a mask. Thus, the n ⁻ type semiconductor region HLn is formed in a self-aligned manner with respect to the gate electrode GHn on the main surface of the semiconductor substrate SUB in the high-voltage nMIS region in the peripheral circuit region. Thereafter, the resist pattern is removed.

Similarly, by ion-implanting a p-type impurity such as boron fluoride into the main surface of the semiconductor substrate SUB in the main surface of the semiconductor substrate SUB in the high-voltage pMIS region of the peripheral circuit region, using the resist pattern as a mask, A p ⁻ -type semiconductor region HLp is formed in a self-aligned manner with respect to the gate electrode GHp on the main surface of the semiconductor substrate SUB in the high-voltage pMIS region. Thereafter, the resist pattern is removed.

Next, an n-type impurity, for example, arsenic is ion-implanted into the main surface of the semiconductor substrate SUB using the resist pattern as a mask on the main surface of the semiconductor substrate SUB in the low-voltage nMIS region of the peripheral circuit region. An n ⁻ type semiconductor region LLn is formed on the main surface of the semiconductor substrate SUB in the system nMIS region in a self-aligned manner with respect to the gate electrode GLn. Thereafter, the resist pattern is removed.

Similarly, by ion-implanting a p-type impurity such as boron fluoride into the main surface of the semiconductor substrate SUB on the main surface of the semiconductor substrate SUB in the low-voltage pMIS region of the peripheral circuit region using the resist pattern as a mask, the peripheral circuit region A p ⁻ type semiconductor region LLp is formed in a self-aligned manner with respect to the gate electrode GLp on the main surface of the semiconductor substrate SUB in the low pressure pMIS region. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 34, for example, a silicon oxide film Sb, a silicon nitride film Sc, and a silicon oxide film St are sequentially deposited on the main surface of the semiconductor substrate SUB by a CVD method, and these are anisotropically dried. Etch back by etching. Thus, in the memory region, on both side surfaces of the selection gate electrode CG, in the peripheral circuit region, the low-voltage nMIS gate electrode GLn, the low-voltage pMIS gate electrode GLp, the high-voltage nMIS gate electrode GHn, and the high-voltage pMIS Sidewall-shaped insulating films are formed on both side surfaces of the gate electrode GHp.

Next, a p-type impurity such as boron or boron fluoride is ion-implanted into the main surface of the semiconductor substrate SUB on the main surface of the semiconductor substrate SUB in the low-voltage pMIS region and the high-voltage pMIS region in the peripheral circuit region. To do. Then, a p ⁺ type semiconductor region Hp is formed in a self-aligned manner with respect to the gate electrode GLp of the low-voltage pMIS and the gate electrode GHp of the high-voltage pMIS. Thus, p ^- type source and drain regions SD of the high-voltage pMIS comprising the semiconductor region HLp and ^{p +} -type semiconductor region Hp is formed of, p ^- type semiconductor regions LLp and ^{p +} -type semiconductor region Hp A source / drain region SD of the low-pressure pMIS consisting of is formed. Thereafter, the resist pattern is removed.

Next, n-type impurities such as arsenic and phosphorus are applied to the main surface of the semiconductor substrate SUB with the resist pattern as a mask on the main surface of the semiconductor substrate SUB in the low-voltage nMIS region and high-voltage nMIS region in the memory region and the peripheral circuit region. Ion implantation. In the memory region, the n ⁺ type semiconductor region Hm is formed in a self-aligned manner with respect to the selection gate electrode CG, and in the peripheral circuit region, the n ⁺ type semiconductor region Hn is formed with the gate electrode GLn of the low-voltage nMIS and the high voltage. It is formed in a self-aligned manner with respect to the gate electrode GHn of the system nMIS. As a result, in the memory region, a source / drain region SDrm including the n ⁻ type semiconductor region SDn and the n ⁺ type semiconductor region Hm is formed. In the peripheral circuit region, a source / drain region SD of a high voltage nMIS composed of an n ⁻ type semiconductor region HLn and an n ⁺ type semiconductor region Hn is formed, and the n ⁻ type semiconductor region LLn and the n ⁺ type semiconductor region Hn are formed. A source / drain region SD of the low-voltage nMIS composed of the semiconductor region Hn is formed. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 35, in the memory region, a silicide layer SIL such as nickel silicide or cobalt silicide is applied to the upper surface of the select gate electrode CG and the upper surface of the n ⁺ type semiconductor region Hm by a self-alignment method such as a salicide process. To form. Similarly, in the peripheral circuit region, the upper surface of the gate electrode GLn of the low voltage system nMIS and the upper surface of the n ⁺ type semiconductor region Hn, the upper surface of the gate electrode GLp of the low voltage system pMIS and the upper surface of the p ⁺ type semiconductor region Hp, the high voltage system Silicide layers SIL are formed on the upper surface of the nMIS gate electrode GHn and the upper surface of the n ⁺ -type semiconductor region Hn, and on the upper surface of the gate electrode GHp of the high-voltage pMIS and the upper surface of the p ⁺ -type semiconductor region Hp.

  Next, as shown in FIG. 36, a silicon nitride film SN2 is deposited as an insulating film on the main surface of the semiconductor substrate SUB by a CVD method. This silicon nitride film SN2 functions as an etching stopper when a contact hole described later is formed. Subsequently, after depositing a silicon oxide film SO2 as an insulating film by a CVD method, the silicon oxide film SO2 is polished by a CMP method, thereby forming an interlayer insulating film ILS composed of the silicon nitride film SN2 and the silicon oxide film SO2.

  Next, in the memory region, a contact hole CNT reaching the silicide layer SIL on the source / drain region SDrm is formed in the interlayer insulating film ILS.

  At the same time, in the peripheral circuit region, in the low-voltage system nMIS, the low-voltage system pMIS, the high-voltage system nMIS, and the high-voltage system pMIS, on the silicide layer SIL and the source / drain regions SD on the respective gate electrodes GLn, GLp, GHn, GHp. A contact hole CA reaching the silicide layer SIL is formed. In FIG. 36, for simplification of description, only the contact hole CA reaching the silicide layer SIL on the source / drain region SD of the low-voltage nMIS, the low-voltage pMIS, the high-voltage nMIS, and the high-voltage pMIS is illustrated.

  Next, plugs PLG are formed in the contact holes CNT and CA. The plug PLG is, for example, a relatively thin barrier film made of a laminated film of titanium and titanium nitride, and a laminated film made of a relatively thick conductive film made of tungsten, aluminum, or the like formed so as to be surrounded by the barrier film. Consists of a membrane.

  After that, by forming a first layer wiring M1 mainly composed of, for example, copper or aluminum on the interlayer insulating film ILS, a memory cell formed in the memory region and a low-voltage system formed in the peripheral circuit region An nMIS, a low-pressure pMIS, a high-pressure nMIS, and a high-pressure nMIS are almost completed. Thereafter, an upper layer wiring and the like are further formed, and a semiconductor device having a nonvolatile memory is manufactured through a normal semiconductor device manufacturing process.

  As described above, according to the second embodiment, the overlay inspection mark MTI of the mating layer has a recess structure in which the insulating film having a smooth upper surface is embedded in the mark groove MT, thereby the mating layer. In the inspection of the overlay accuracy between the exposure layer and the exposure layer, the position of the overlay inspection mark MTI can be detected with high accuracy. Further, since the recess amount can be controlled, the overlay inspection mark MTI having the optimum recess amount can be formed. Thereby, the manufacturing yield of the semiconductor device can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

CA Contact hole Cc Semiconductor region CG for channel formation Select gate electrodes CHn, CHp, CLn, CLp Semiconductor region Cm for channel formation Semiconductor region CNT for channel formation CNT Contact hole CSL Charge storage layer Dn n ⁻ type semiconductor region Drm Drain Region GI1, GI2 Gate insulating film GHn, GHp, GLn, GLp Gate electrode HLn n ⁻ type semiconductor region HLp p ⁻ type semiconductor region Hm, Hn n ⁺ type semiconductor region Hp p ⁺ type semiconductor region Ib Lower layer insulation Film ILS Interlayer insulating film It Upper insulating film LLn n ⁻ type semiconductor region LLp p ⁻ type semiconductor region M1 First layer wiring MG Memory gate electrode MRP, MRP2 Overlay inspection mark resist pattern MT Mark trench MTI Overlap Alignment inspection mark NISO n-type embedding E le PLG plug PS1, PS2 n-type conductive film RP, RP0, RP1, RP2 resist pattern Sb oxide silicon film Sc silicon nitride film SDn n ^- -type semiconductor region SD, SDRM source and drain regions SI conductive SIN1, sin @ 2 n Type conductive film SIpp p type conductive film SIL silicide layer Sn n ⁻ type semiconductor region SN1, SN2 silicon nitride film SO1, SO2 silicon oxide film Srm source region St silicon oxide film ST isolation trench STI element isolation portion SUB semiconductor substrate SW1 , SW2, SW3 Side wall WHn n-type well WHp p-type well WLn n-type well WLp p-type well

Claims (12)

A first region in which a first insulating film having a first thickness is formed on a semiconductor substrate, a second region in which a second insulating film having a second thickness different from the first thickness is formed, and a photolithography process. A method of manufacturing a semiconductor device having a third region where an overlay inspection mark is formed,
(A) forming a groove in a main surface of the semiconductor substrate in the third region;
(B) After the step (a), a step of embedding a third insulating film in the trench,
(C) after the step (b), forming the second insulating film on the main surface of the semiconductor substrate in the first region, the second region, and the third region;
(D) a step of removing the second insulating film in the first region and the third region by wet etching after the step (c);
(E) after the step (d), forming the first insulating film on the main surface of the semiconductor substrate in the first region and the third region;
Including
In the step (d), the third insulating film is processed by the wet etching until the upper surface of the third insulating film reaches a first depth from the main surface of the semiconductor substrate, and is embedded in the groove. A method of manufacturing a semiconductor device, wherein the overlay inspection mark made of the third insulating film is formed. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first depth is 15 to 25 nm. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the third region is a scribe region. In the manufacturing method of the semiconductor device according to claim 1,
The first insulating film and the second insulating film are made of silicon oxide formed by oxidizing the semiconductor substrate,
The method of manufacturing a semiconductor device, wherein the third insulating film is made of silicon oxide formed by a plasma CVD method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
(F) After the step (e), a step of forming a conductive film on the main surface of the semiconductor substrate;
(G) After the step (f), a step of forming a resist pattern on the conductive film,
Including
A method for manufacturing a semiconductor device, wherein in the step (g), overlay accuracy is inspected using the resist pattern formed in the third region and the overlay inspection mark. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the step (d), the upper surface of the third insulating film subjected to the wet etching is smooth. A method for manufacturing a semiconductor device, comprising: a first region where a memory cell is formed on a semiconductor substrate; and a second region where an overlay inspection mark used in a photolithography process is formed.
(A) forming a groove in the main surface of the semiconductor substrate in the second region;
(B) After the step (a), a step of embedding a first insulating film in the trench,
(C) After the step (b), the first insulating film is processed by etching until the upper surface of the first insulating film reaches a first depth from the main surface of the semiconductor substrate, and is embedded in the groove. Forming the overlay inspection mark made of the first insulating film,
(D) After the step (c), a second insulating film is formed on the main surface of the semiconductor substrate in the first region and the second region, and a first conductive film is formed on the second insulating film. The process of
(E) After the step (d), a first resist pattern is formed on the first conductive film in the first region, and a second resist pattern is formed on the first conductive film in the second region. Process,
(F) After the step (e), forming the gate electrode of the memory cell in the first region by processing the first conductive film using the first resist pattern as a mask;
Including
In the step (e), the overlay accuracy is inspected using the second resist pattern formed in the second region and the overlay inspection mark. The method of manufacturing a semiconductor device according to claim 7.
The method for manufacturing a semiconductor device, wherein the second region is a scribe region. The method of manufacturing a semiconductor device according to claim 7.
The first insulating film is made of silicon oxide formed by a plasma CVD method,
The second insulating film includes a lower insulating film, a charge storage layer formed on the lower insulating film, and a stacked film of an upper insulating film formed on the charge storage layer. Method. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the charge storage layer is made of silicon nitride. The method of manufacturing a semiconductor device according to claim 7.
The method for manufacturing a semiconductor device, wherein the etching in the step (c) is wet etching. The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein in the step (c), the upper surface of the first insulating film subjected to the etching is smooth.