JPS62128138A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate relative positional difference from an insulating-isolating region for the accomplishment of high precision positioning by a method wherein a second groove is formed, 1.5-4 times wider than the insulating-isolating region but not wider than twice the thickness of the material to fill the grooves, a step is provided on the surface of the material filling the second groove, and said step serves as a position detecting mark. CONSTITUTION:A narrow groove 4 and second groove 8 are formed in a silicon substrate 1 provided on its primary surface with a silicon oxide film 2 and silicon nitride film 3. The grooves 4, 8 are provided with oxide films 5 on their inner surfaces. The grooves 4, 8 are then filled with polycrystalline silicon 6 for the formation of an groove-type insulating-isolating region 7 and a position detecting mark 9. The position detecting mark 9, 1.5-4 times wider than the insulating-isolating region 7, is a step created on a recess 6a provided on the upper surface of the polycrystalline silicon 6 filling the second groove 8. The width of the second groove 8 accommodating the position detecting mark 9 is set at a value not more than twice the thickness of the polycrystalline silicon 6 filling the grooves 4, 8. The position detecting mark 9 serves to realize a high precision positioning in relation to the insulating-isolating region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a trench type isolation region;
In particular, the present invention relates to a semiconductor device having a position detection mark in a part thereof.

[Conventional technology]

In semiconductor devices such as semiconductor integrated circuits, the required elements are formed on the main surface of the semiconductor wafer by sequentially laminating diffusion layers and thin films, etc., which are made up of multiple steps, but it is necessary to set the relative positions of pattern formation in each step. In order to do this, a position detection mark is usually formed on a part of the half-quad wafer, and this position detection mark is detected in each process to set the position of each process pattern.

Conventionally, pattern edges of insulating regions formed to partition device regions on semiconductor wafers have been used as position detection marks, but with the miniaturization of devices in recent years, insulating isolation regions have been configured in the form of grooves. In a semiconductor device in which this type of semiconductor device is used, it becomes difficult to use this insulating isolation region as a position detection mark. In other words, the trench-type insulation isolation region is created by forming a trench in a semiconductor wafer and then burying a material in the trench while maintaining an insulating state. Since the material buried in the groove is formed flat with respect to the surface of the semiconductor wafer, the step required for the position detection mark is not formed, and therefore it becomes impossible to recognize it.

For this reason, in this type of semiconductor device, a position detection mark is formed by partially etching the surface of the semiconductor wafer in a process independent of the trench-type isolation region.

[Problem that the invention seeks to solve]

The conventional semiconductor device described above requires an independent process to form the position detection mark, which increases the number of processes and complicates manufacturing. A relative positional error is likely to occur between the two due to positional deviation in mask alignment when forming each, and there is a risk that alignment accuracy will decrease in alignment with the insulation isolation region using the position detection mark as a reference.

[Means for Solving the Problems] In the semiconductor device of the present invention, the position detection mark is formed in the same process as the groove-type insulation isolation region, thereby preventing an increase in the number of steps and reducing the relative position error with the insulation isolation region. This makes it possible to set the position with high accuracy.

The semiconductor device of the present invention has a trench type isolation region formed by burying a material in a trench while maintaining an insulating state.
．． A second groove is formed with a width that is 5 to 4 times as wide, and preferably less than twice the thickness of the material buried in the groove, and the difference in groove width between these grooves and the second groove is determined. A position detection mark is formed by forming a step on the surface of the material buried in the second groove.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2(a),
(b) is a sectional view showing the manufacturing method in order of steps.

This semiconductor device includes a silicon substrate 1 having a silicon oxide film 2 and a silicon nitride film 3 on its main surface, a narrow groove 4 formed therein, an oxide film 5 formed on the inner surface thereof, and a polycrystalline A trench type insulation isolation region 7 is formed by embedding silicon 6. Similarly, a second groove 8 is formed, an oxide film 5 is formed on its inner surface, and then polycrystalline silicon 6 is buried in the groove 8 to form a position detection mark 9. The groove width of the position detection mark 9 is 1.5 to 4 times larger than the groove width of the insulation isolation region 7,
In this position detection mark 9, the polycrystalline silicon 6
A step consisting of a recess 6a is formed on the upper surface of the mark, and this step can be recognized as a mark. The groove width of the position detection mark 9 is set to be twice or less the thickness when the polycrystalline silicon 6 is buried in the grooves 4 and 8.

Next, a method for manufacturing the semiconductor device will be explained with reference to FIG.

First, as shown in FIG. 1(a), the main surface of a silicon substrate 1 is oxidized to form a silicon oxide film 2 of about 500 layers.
A silicon nitride film 3 of 1,000 yen is formed by vapor phase growth. Then, the silicon nitride film 3. The silicon oxide film 2 and the silicon substrate 1 are sequentially etched to a width of 1 μm.
A narrow groove 4 with a width of m and a second groove 8 with a width of 3 μm, which is larger than this, are formed. In this case, the groove 4 is formed in a pattern corresponding to the insulation isolation region, and the second groove 8 is formed at a position that does not interfere with element formation.

Then, after removing the photoresist 10, as shown in FIG.
The inner surfaces of grooves 4 and 8 are coated with 2,000 yen each by thermal oxidation treatment as shown in FIG.
A silicon oxide film 5 is formed, and polycrystalline silicon 6 is deposited thereon to a thickness of about 2 μm by vapor phase growth. The polycrystalline silicon 6 deposited at this time forms a narrow groove 4.
Although the groove 8 is almost flat on the top, a recess 6A of about 1,000 depths is formed on the groove 8.

Then, when the polycrystalline silicon 6 is anisotropically dry etched until the silicon nitride film 3 is exposed, grooves 4 are formed as shown in FIG.
Then, a substantially flat polycrystalline silicon surface is obtained from the silicon substrate 1 to the silicon nitride film 3, and an insulating isolation region 7 is formed.
In the groove 8, the recess 6A remains as it is, and the position detection mark 9 is formed.

According to this configuration, if the insulation isolation region 7 and the position detection mark 9 are simply formed with different groove widths and are formed in the same process, a flat surface can be obtained in the insulation isolation region 7, and The position detection mark 9 has a recess 6a which can be used as a mark. Therefore, the insulation isolation region 7 and the position detection mark 9 can be formed using the same photolithography mask, and there is no relative positional error between the two, and the position detection mark 9 can be Even when alignment is performed, alignment with respect to the insulation isolation region 7 can be performed with high precision. Further, since both can be formed in the same process, there is no need to employ separate special processes, and the manufacturing process can be easily performed without increasing the number of manufacturing steps.

Here, if the width of the second groove 8 constituting the position detection mark 9 is in the range of 1.5 to 4 times the width of the groove 4 of the insulation isolation region 7, it will be flat on the groove 4 and flat on the groove 8. In this case, it is possible to realize a configuration that satisfies both requirements by forming the recessed portion 6a. Further, in this case, the width of the groove 8 is preferably twice or less the thickness of the deposited polycrystalline silicon 6.

Furthermore, it goes without saying that the material buried in the trench is not limited to the above-mentioned polycrystalline silicon, but may be other insulating materials.

〔Effect of the invention〕

As explained above, the present invention provides a second layer having a width that is 1.5 to 4 times larger than that of the trench type isolation region, and preferably not more than twice the thickness of the material buried in the trench. form a groove,
Since the position detection mark is formed by embedding the material in this second groove, the position detection mark can be formed in the same process as the groove-type insulation isolation region, thereby reducing the number of steps. It is possible to prevent relative position errors between the insulation separation area and the position detection mark, and to improve the accuracy of alignment to the insulation separation area during alignment using the position detection mark. can be done.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the main parts of the semiconductor device of the present invention, and FIG.
a) and (b) are cross-sectional views showing the manufacturing method in order of steps. 1... Silicon substrate, 2... Silicon oxide 1fi,
3... Silicon nitride film, 4... Groove, 5... Silicon oxide film, 6... Polycrystalline silicon, 6A, 6a...
Recessed portion, 7... Insulating isolation region, 8... Second groove, 9...
...Position detection mark, 10...Photoresist.

Claims (1)

[Scope of Claims] 1. A groove-type insulating isolation region formed by burying a material in an insulating state in a groove formed on a semiconductor substrate, and a position detection mark that detects a position using a step on the semiconductor substrate. In the semiconductor device, the position detection mark is formed by embedding the same material as the embedding material in a second groove formed with a width 1.5 to 4 times wider than the groove-type insulation isolation region, and 2
A semiconductor device characterized in that a recess is formed on the upper surface of the buried material in the groove. 2. The semiconductor device according to claim 1, wherein the second groove constituting the position detection mark is set to have a width not more than twice the thickness of the deposited material buried in the groove.