TW202228192A - Semiconductor exposure machine calibration method and semiconductor structure manufacturing method - Google Patents

Abstract

A semiconductor exposure machine calibration method includes the following operations. A first test layer with a first pattern and a second test layer with a second pattern are formed by a first semiconductor exposure machine according to a first mask pattern and a second mask pattern and stacked sequentially. A third test layer with a third pattern is formed by a second semiconductor exposure machine according to a third mask pattern and stacked on the second test layer. An overlap error between the first pattern on the first test layer and the third pattern on the third test layer is measured by an electron microscope. Calibrate the first semiconductor exposure machine and the second semiconductor exposure machine according to the overlap error.

Description

Semiconductor exposure machine calibration method and semiconductor structure manufacturing method

The present disclosure relates to a calibration method for a semiconductor exposure machine and a method for fabricating a semiconductor structure.

For the manufacturing process of semiconductor wafers, due to the limitation of the area, only the main related layers can be designed with measurement marks, so as to confirm the pattern of the upper and lower layers directly overlapped. However, when the number of layers to be formed is four or more, there will be cases where the marking for measurement cannot be designed. Since the two sub-related semiconductor layers are formed using different semiconductor exposure machines, it is difficult to confirm whether the patterns of the two sub-related semiconductor layers are properly overlapped due to the lack of measurement marks, and it is also difficult to confirm the corresponding semiconductor wafer. Is the line on the line as expected.

Therefore, how to improve the above problems is one of the problems to be solved by those skilled in the art.

One aspect of the present disclosure relates to a method for calibrating a semiconductor exposure machine.

According to an embodiment of the present disclosure, a method for calibrating a semiconductor exposure machine includes the following processes. The first semiconductor exposure machine forms the first test layer and the second test layer sequentially stacked respectively through the first mask pattern and the second mask pattern. The first test layer and the second test layer respectively have a first pattern and a second pattern. The second semiconductor exposure machine stacks the third test layer on the second test layer through the third mask pattern. The third test layer has a third pattern. The stacking error between the first pattern on the first test layer and the third pattern on the third test layer is measured by an electron microscope. The first semiconductor exposure machine and the second semiconductor exposure machine are calibrated according to the stacking error.

In one or more embodiments of the present disclosure, the overlay error includes a horizontal offset between the first pattern and the third pattern.

In some embodiments, in the process of calibrating the first semiconductor exposure machine and the second semiconductor exposure machine according to the stacking error, the second semiconductor exposure machine provides the same compensation phase difference to a plurality of reticle patterns according to the stacking error, and the reticle The pattern includes a third pattern reticle pattern forming a third pattern.

In one or more embodiments of the present disclosure, the first pattern and the second pattern are arranged so that the channel passes through the first test layer and the second test layer. The third test layer extends into the channel.

In some embodiments, the aforementioned semiconductor exposure machine calibration method further includes the following procedures. The second semiconductor exposure machine stacks the fourth test layer on the third test layer through the fourth mask pattern. The fourth test layer includes a fourth pattern. The stacking error between the second pattern on the second test layer and the fourth pattern on the fourth test layer is measured by an electron microscope.

In one or more embodiments of the present disclosure, the fourth test layer extends to the second test layer.

In one or more embodiments of the present disclosure, the aforementioned method for calibrating a semiconductor exposure machine further includes the following processes. After the fourth test layer is formed, it is measured whether any two conductive patterns of the plurality of conductive patterns on the second test layer are short-circuited.

In some embodiments, the electron microscope comprises a scanning electron microscope (SEM).

One aspect of the present disclosure relates to a method of fabricating a semiconductor structure.

According to an embodiment of the present disclosure, a method for fabricating a semiconductor structure includes the following processes. A first semiconductor exposure machine and a second semiconductor exposure machine calibrated by the semiconductor exposure machine calibration method as described above are provided. A semiconductor pattern layer and two semiconductor pattern layers are sequentially stacked with a first mask pattern and a second mask pattern by a first semiconductor exposure machine. A third semiconductor pattern layer and a fourth semiconductor pattern layer which are sequentially stacked on the second semiconductor pattern layer are formed by a second semiconductor exposure machine with a third mask pattern and a fourth mask pattern respectively, so as to form a semiconductor structure.

In one or more embodiments of the present disclosure, the aforementioned method for fabricating a semiconductor structure further includes the following processes. The semiconductor structure is diced into a plurality of dies. The yield of these dies is measured.

To sum up, the semiconductor exposure machine calibration method provided by the present disclosure can correct the unintended short circuit problem caused by the sub-correlation pattern being unaligned.

It should be understood that the above general description and the following detailed description are all further descriptions by way of examples, and are intended to provide further explanation of the present disclosure.

The following examples are described in detail in conjunction with the accompanying drawings, but the provided examples are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit the order of its execution. Any recombination of elements The structure and the resulting device with equal efficacy are all within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn on the original scale. For ease of understanding, the same or similar elements in the following description will be described with the same symbols.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have their ordinary meanings as understood by those skilled in the art. Furthermore, the definitions of the above words in commonly used dictionaries should be interpreted as meanings consistent with the relevant fields of the present disclosure in the content of this specification. Unless specifically defined, these terms are not to be construed in an idealized or overly formal sense.

The terms "first", "second", ... etc. used in this document do not specifically refer to the order or order, nor are they used to limit the present disclosure, but are only used to distinguish elements or operations described in the same technical terms. That's it.

Secondly, the terms "comprising", "including", "having", "containing" and the like used in this document are all open-ended terms, which means including but not limited to.

Furthermore, in this text, unless the content of the article is particularly limited, "a" and "the" can generally refer to a single one or a plurality of. It will be further understood that the terms "comprising", "including", "having" and similar words used herein designate the recited features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more of its other features, regions, integers, steps, operations, elements, components, and/or groups thereof, described or additional thereto.

In order to solve the problem that it is difficult to measure the alignment error between the sub-correlated semiconductor stacks, the present disclosure provides a semiconductor exposure machine calibration method, and a semiconductor structure fabrication method based on the results of the semiconductor exposure machine calibration method of the present disclosure.

Please refer to Figure 1 and Figure 2 in order. FIG. 1 is a flowchart illustrating a calibration method 100 of a semiconductor exposure machine according to an embodiment of the present disclosure. FIG. 2 illustrates a flowchart of a method 200 for fabricating a semiconductor structure according to an embodiment of the present disclosure. The semiconductor structure manufacturing method 200 shown in FIG. 2 can be performed based on the calibration result of the semiconductor exposure machine calibration method 100 .

To further describe a semiconductor exposure machine calibration method 100 of the present disclosure, please refer to FIG. 3 and FIG. 4 in sequence. FIGS. 3 to 4 are cross-sectional views illustrating structures of different processes of the calibration method 100 for a semiconductor exposure machine according to an embodiment of the present disclosure. It should be noted that FIG. 3 to FIG. 4 only illustrate part of the overlapping portion by way of example, and should not limit the present disclosure.

In the present embodiment, since the semiconductor exposure machine used includes an exposure machine, the first semiconductor exposure machine and the second semiconductor exposure machine described later are, for example, a first exposure machine and a second exposure machine, respectively. The first exposure machine and the second exposure machine can form a patterned semiconductor layer through a designed mask pattern. However, the present disclosure does not limit the types of semiconductor exposure machines.

In some embodiments, the patterned semiconductor layer is formed on a semiconductor wafer or a semiconductor substrate, and a plurality of stacked patterned semiconductor layers form a semiconductor structure, and the formed semiconductor structure can be cut to form a plurality of dies. For the purpose of simple description, semiconductor wafers or semiconductor substrates are omitted and not shown.

Please refer to Figure 1 and Figure 3 at the same time. In the process 110, a first test layer 310 and a second test layer 330 are sequentially stacked by a first semiconductor exposure machine.

In this embodiment, as described above, the first semiconductor exposure machine forms the patterned first test layer 310 through the first mask pattern, and the first test layer 310 has a first pattern. As shown in FIG. 3 , in this embodiment, the patterned first test layer 310 includes channels 315 .

In FIG. 3, the first semiconductor exposure machine forms a patterned second test layer 330 through the second mask pattern. The second test layer 330 is stacked on the first test layer 310 . The second test layer 330 has a second pattern. In this embodiment, the second test layer 330 also includes channels 335 , and the patterned second test layer 330 further includes spaces 340 . The space 340 has a width W1.

In this embodiment, the second pattern of the second test layer 330 includes two separated conductive patterns 330A and 330B between the channels 335 , and a space 340 exists between the conductive patterns 330A and 330B.

Please go back to Figure 1 and refer to Figure 4 at the same time. In the process 120, a third test layer 350 sequentially stacked on the second test layer 330 is formed by a second semiconductor exposure machine. In this embodiment, as shown in FIG. 4 , a fourth test layer 370 may be further stacked on the third test layer 350 .

As mentioned above, the second semiconductor exposure machine forms the patterned third test layer 350 and the fourth test layer 370 respectively through the third mask pattern and the fourth mask pattern. The third test layer 350 and the fourth test layer 370 have a third pattern and a fourth pattern, respectively.

As shown in FIG. 4 , the third test layer 350 is aligned with the channel 315 of the first test layer 310 and the channel 335 of the second test layer 330 . In other words, the channel 315 and the channel 335 form an assembly channel 345 passing through the first test layer 310 and the second test layer 330 , and the third test layer 350 is arranged and formed to extend on the assembly channel 345 , so that the assembly channel 345 is formed in the assembly channel 345 . The inner adjacent to the first test layer 310 . In Figures 3 and 4, the assembly channel 345 formed by the channel 315 and the channel 335 is shown in phantom. On the assembly channel 345 , the fourth test layer 370 is stacked on the third test layer 350 .

However, as shown in FIG. 4 , once there is an unexpected deviation/difference between the first semiconductor exposure machine and the second semiconductor exposure machine, the patterned third test layer 350 will exist relative to the first test layer 310 Unexpected offset. As shown in FIG. 4, although the patterned third test layer 350 is designed to be aligned with the channel 315 and the channel 335, due to the unexpected deviation/machine difference between the first semiconductor exposure machine and the second semiconductor exposure machine, The third test layer 350 is made to have a horizontal offset d relative to the assembly channel 345 so that a portion of the third test layer 350 overlaps the patterned first test layer 310 and the second test layer 330 .

In addition, as shown in FIG. 4, in this embodiment, the patterned fourth test layer 370 is formed and stacked on the third test layer 350, and the fourth pattern portion 370A of the fourth test layer 370 is designed to be connected to the second test layer One of the conductive patterns 330A and the conductive patterns 330B separated by a space 340 on 330 . However, due to the unexpected deviation/difference between the first semiconductor exposure machine and the second semiconductor exposure machine, the fourth test layer 370 is simultaneously connected to the two electrically separated conductive patterns 330A of the second test layer 330 and the Conductive pattern 330B. As a result, unexpected short circuits may occur.

As shown in FIG. 4, the fourth test layer 370 has a portion connected to the second test layer 330 outside the assembly channel 345, and the portion of the fourth test layer 370 connected to the second test layer 330 has a width W2, and the width W2 is greater than the width W1. Therefore, once the deviation occurs, the fourth test layer 370 may simultaneously connect the two conductive patterns 330A and 330B on the second test layer 330 that should be separated, resulting in an unexpected short circuit.

In some embodiments, whether there is an overlap between the second test layer 330 and the fourth test layer 370 can also be confirmed by testing whether there is a short circuit between the conductive patterns 330A and 330B that should be separated on the second test layer 330 error.

In FIG. 4 , after the third test layer 350 and the fourth test layer 370 are formed, the sequentially stacked first test layer 310 , the second test layer 330 , the third test layer 350 and the fourth test layer 370 can be referred to as a test semiconductor structure. By confirming the overlapping of the first test layer 310 , the second test layer 330 , the third test layer 350 and the fourth test layer 370 , it is possible to obtain the existence of the first semiconductor exposure machine and the second semiconductor exposure machine. Unexpected deviation/machine error.

Please go back to Figure 1. In the process 130 , the alignment error between the first pattern of the first test layer 310 and the third pattern of the third test layer 350 is measured by an electron microscope. In this embodiment, the electron microscope used includes a scanning electron microscope (Scanning Electron Microscope).

FIGS. 5A to 5C illustrate a plurality of top views of stacks of different patterns of test semiconductor structures formed by the first test layer 310 , the second test layer 330 , the third test layer 350 and the fourth test layer 370 .

Refer to Figure 1 and Figure 5A at the same time. FIG. 5A shows a part of the overlapping of the first test layer 310 and the third test layer 350 under the electron microscope. Due to direct observation with an electron microscope, it is possible to confirm a lamination difference between the first semiconductor exposure machine and the second semiconductor exposure machine that cannot be seen on the mask simulation software. In the part shown in FIG. 5A, the first test layer 310 includes a first pattern portion 310A that is quasi-square, and the third test layer 350 includes a third pattern portion 350A, a third pattern portion 350B, and is located on the first pattern portion 310A The elongated third pattern portion 350C and the third pattern portion 350D, the third pattern portion 350E and the third pattern portion 350F. The third pattern portion 350A is disposed on the left side of the square-like first pattern portion 310A in the third pattern portion 350B. The third pattern portion 350E is disposed on the right side of the square-like first pattern portion 310A in the third pattern portion 350F.

In the predetermined design and simulation of the mask software, in the part shown in FIG. 5A, the third test layer 350 should be symmetrically stacked on the first test layer 310, that is, the third pattern parts 350A-350F are relatively square-like The first pattern portion 310A should be symmetrically distributed. Relative to the first pattern portion 310A, the third pattern portions 350A, 350B and the third pattern portions 350E, 350F should be arranged to be symmetrically opposite, and the distance between the elongated third pattern portion 350C and the right edge of the first pattern portion 310A should be designed. Equivalent to the distance of the third pattern portion 350D to the left edge of the first pattern portion 310A. However, due to the unintended stacking error of the first test layer 310 and the third test layer 350 , the third test layer 350 is offset relative to the first test layer 310 . As shown in FIG. 5A , for the third pattern of the third test layer 350 , the third pattern portion 350C and the third pattern portion 350D of the middle two strips are opposite to the square-like first pattern of the first test layer 310 The distances of the portion 310A relative to the two edges are not equal. The long strip third pattern portion 350D on the left side of the third test layer 350 is at a distance d1 from the left edge of the square-like first pattern portion 310A, the long strip third pattern portion 350C on the right side of the third test layer 350 is at a distance d2 from the square-like right edge, and The distance d2 is greater than the distance d1 , indicating that the third test layer 350 is offset to the left relative to the first test layer 310 .

The horizontal offset d in Figure 4 corresponds to one-half of the distance d2 minus one-half of the distance d1.

FIG. 5B shows a part of the overlapping of the third test layer 350 and the fourth test layer 370 obtained by an electron microscope. Since the third test layer 350 and the fourth test layer 370 are both formed by the second semiconductor exposure machine, there is no stacking error between the third test layer 350 and the fourth test layer 370 . As shown in FIG. 5B , the elliptical third pattern portion 350G of the third test layer 350 is disposed at the center of the elliptical hole of the fourth pattern portion 370B of the fourth test layer 370 , which conforms to the expected design. If the third test layer 350 and the fourth test layer 370 are misaligned or offset in the stack, since the third test layer 350 and the fourth test layer 370 are both formed by the second semiconductor exposure machine, the second semiconductor exposure machine The mask simulation software should respond instantly. Generally speaking, there should be no stacking error between the third test layer 350 and the fourth test layer 370 formed by the second semiconductor exposure machine.

FIG. 5C shows a part of the overlapping of the second test layer 330 and the fourth test layer 370 obtained by an electron microscope. The second test layer 330 and the fourth test layer 370 are in a sub-correlated stacking relationship, so there is no measurement mark designed to measure alignment. At this time, it was confirmed by an electron microscope whether or not the stacks were aligned.

As shown in FIG. 5C , the second test layer 330 includes a plurality of strips of conductive patterns 330A and 330B, wherein the two strips are a group of conductive patterns 330A and 330B that should be separated from each other by a gap 340 . However, due to the lamination machine difference between the first semiconductor exposure machine and the second semiconductor exposure machine, the second test layer 330 formed by the first semiconductor exposure machine and the fourth test layer 370 formed by the second semiconductor exposure machine There is a stacking error between the fourth pattern parts 370A, so that the fourth pattern part 370A of the patterned fourth test layer 370 connects the two long strip conductive patterns 330A and 330B of the second test layer 330 that should be separated, resulting in non-conductive Expected short circuit.

It can be seen from FIG. 5A to FIG. 5C that, first, due to the lamination machine difference between the different first semiconductor exposure machines and the second semiconductor exposure machines, the first test layer 310 and the second test layer 330 are relatively tested for the third There is a stacking error between the layer 350 and the fourth test layer 370 . Furthermore, since the first semiconductor exposure machine and the second semiconductor exposure machine are different machines, the respective mask simulation software cannot reflect the stacking machine difference between the first semiconductor exposure machine and the second semiconductor exposure machine. A test layer 310 and the second test layer 330 have a stacking error relative to the third test layer 350 and the fourth test layer 370 . For the stacking of the same semiconductor exposure machine, it is usually possible to meet the expected design. For the third test layer 350 and the fourth test layer 370 shown in FIG. 5B, the elliptical fourth pattern portion 370B of the fourth test layer 370 can be The center of the elliptical hole of the third pattern portion 350G of the third test layer 350 is arranged in accordance with the design.

So, back to Figure 1. In the process 140, after the stacking error obtained in the process 130, the first semiconductor exposure machine and the second semiconductor exposure machine are calibrated according to the stacking error. For example, the second semiconductor exposure machine is calibrated based on the first semiconductor exposure machine. Specifically, the correction of the second semiconductor exposure machine can be achieved by providing a compensation phase difference for correction. That is, in the subsequent manufacturing process, after the mask of the first semiconductor exposure machine and the mask of the second semiconductor exposure machine are designed, when the second semiconductor exposure machine is executed, the second semiconductor exposure machine is formed in the Patterns are added with an additional offset to compensate for the phase difference.

For example, in this embodiment, when the semiconductor layer with the third pattern and the fourth pattern is subsequently formed by the third mask pattern and the fourth mask pattern, both the third mask pattern and the fourth mask pattern are A compensated phase difference is provided, so that a compensated horizontal offset d can be obtained for the positions of the third pattern and the fourth pattern. In this way, taking the third test layer 350 of FIG. 5A as an example, the third pattern of the third test layer 350 and the first pattern of the first test layer 310 can be returned to the symmetrical relationship as designed, that is, the third pattern Align the first pattern, which corresponds to the fourth pattern portion 370A of the fourth test layer 370 in FIG. 5C can also be modified, so that the conductive pattern 330A and the conductive pattern 330B adjacent to the second test layer 330 are no longer electrically connected to each other. catch.

Based on the stacking error between the first test layer 310 and the third test layer 350 , the stacking error between the first semiconductor exposure machine and the second semiconductor exposure machine can be calibrated by compensating for the phase difference offset. In the process of calibrating the second semiconductor exposure machine according to the stacking error, the second semiconductor exposure machine provides the same compensation phase difference to a plurality of mask patterns according to the stacking error, and the mask patterns include a third pattern mask forming a third pattern graphics. In this way, since the first pattern of the first test layer 310 and the third pattern of the third test layer 350 can be overlapped and aligned, the second pattern of the second related second test layer 330 and the second pattern of the fourth test layer 370 can be aligned. Quad patterns will also be able to be aligned.

Please go back to picture 2. In a flow 210 of the semiconductor structure fabrication method 200, a calibrated first semiconductor exposure machine and a second semiconductor exposure machine are provided. The calibration of the process 210 is implemented by the semiconductor exposure machine calibration method 100 according to an embodiment of the present disclosure.

FIGS. 6 to 7 are cross-sectional views illustrating structures of different processes of the method 200 for fabricating a semiconductor structure according to an embodiment of the present disclosure. Please refer to FIG. 2, and to FIG. 6 and FIG. 7 in sequence, to further describe the method 200 for fabricating the semiconductor structure.

In the process 220 , the first semiconductor pattern layer 410 and the second semiconductor pattern layer 430 are sequentially stacked by the first semiconductor substrate. The first semiconductor pattern layer 410 has a first pattern, and thus has a channel 415 close to the first test layer 310 . The second semiconductor pattern layer 430 has a second pattern, and therefore also has a channel 435 and a spacer 440 that separates the conductive patterns 430A and 430B of the second semiconductor pattern layer 430 , as shown in FIG. 6 .

Entering the process 230 , the third semiconductor pattern layer 450 and the fourth semiconductor pattern layer 470 sequentially stacked on the second semiconductor pattern layer 430 are formed by the second semiconductor exposure machine.

As shown in FIG. 7 , the third semiconductor pattern layer 450 and the fourth semiconductor pattern layer 470 also have the third pattern and the fourth pattern, respectively, and thus are similar to the third test layer 350 and the fourth test layer 370 respectively. However, after the correction in the process 210, the third semiconductor pattern layer 450 can be aligned with the channel 445 formed by the channel 415 and the channel 435, and the fourth pattern portion 470A of the fourth semiconductor pattern layer 470 will not cross the The two semiconductor pattern layers 430 are located outside the assembly channel 445 to separate the conductive pattern 430A and the conductive pattern 430B separated by an interval 440 .

In this way, through the process 210 to the process 230 of the semiconductor structure manufacturing method 200 , the semiconductor structure 400 is formed.

FIGS. 8A to 8C illustrate a plurality of top-view schematic diagrams of different pattern stacks of the formed semiconductor structure 400 .

FIG. 8A shows a part of the overlapping of the first semiconductor pattern layer 410 and the third semiconductor pattern layer 450 . As shown in FIG. 8A , the first semiconductor pattern layer 410 includes a first pattern portion 410A, and the third semiconductor pattern layer 450 includes a third pattern portion 450A, a third pattern portion 450B, a long third pattern portion 450C and a third pattern portion 450A. The pattern portion 450D, the third pattern portion 450E, and the third pattern portion 450F. For the third pattern of the third semiconductor pattern layer 450 , the middle two strips of the third pattern portion 450C and the third pattern portion 450D are opposite to the opposite sides of the square-like first pattern portion 410A of the first semiconductor pattern layer 410 distances are equal. The long third pattern portion 450D on the left side of the third semiconductor pattern layer 450 is a distance d3 from the left side of the square-like first pattern portion 410A, and the long third pattern portion 450C on the right side of the third semiconductor pattern layer 450 is opposite to the square-like first pattern portion 410A The right is distance d4, and distance d3 is equal to distance d4. This corresponds to the fact that the third pattern parts 450A, 450B and the third pattern parts 450E and 450F are symmetrically opposite to the first pattern part 410A of the square-like shape, for example, the distance from the third pattern part 450A to the right side of the first pattern part 410A is the same The distance from the third pattern portion 450E to the left side of the first pattern portion 410A indicates that the first semiconductor pattern layer 410 and the third semiconductor pattern layer 450 meet the expected symmetrical overlapping design.

FIG. 8B shows a part of the overlapping of the third semiconductor pattern layer 450 and the fourth semiconductor pattern layer 470 obtained by an electron microscope. Since the third semiconductor pattern layer 450 and the fourth semiconductor pattern layer 470 are both formed by the second semiconductor exposure machine, there is no stacking error between the third semiconductor pattern layer 450 and the fourth semiconductor pattern layer 470 . As shown in FIG. 8B , the elliptical fourth pattern portion 470B of the fourth semiconductor pattern layer 470 is disposed at the center of the elliptical hole of the third pattern portion 450G of the third semiconductor pattern layer 450 , which conforms to the expected design.

FIG. 8C shows a part of the overlapping of the second test layer 330 and the fourth semiconductor pattern layer 470 obtained by an electron microscope. As shown in FIG. 8C , since the second semiconductor exposure machine is calibrated, the fourth pattern portion 470A of the fourth semiconductor pattern layer 470 is not simultaneously connected to the two separate conductive patterns 430A and 430B of the second semiconductor pattern layer 430 .

In some embodiments, after the semiconductor structure 400 is formed, the semiconductor structure 400 can be diced into a plurality of dies. The yield of these dies is measured. In this way, it can also be confirmed whether or not there is still a shift in the semiconductor pattern lamination layer. If so, it can be recorded for reference in subsequent manufacturing processes.

To sum up, the semiconductor exposure machine calibration method provided by the present disclosure can correct the unintended short circuit problem caused by the sub-correlation pattern being unaligned. Based on the above-mentioned correction, the sub-correlated patterns of the fabricated semiconductor structure can be aligned with each other. The disclosed method for calibrating a semiconductor exposure machine and a method for fabricating a semiconductor structure can be applied to a multi-layer stack structure formed by two or more semiconductor exposure machines. The semiconductor exposure machine is, for example, a yellow light exposure machine.

Although the present disclosure has been disclosed above with examples, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection of the present disclosure The scope shall be determined by the scope of the appended patent application.

It will be apparent to those skilled in the art that various modifications and changes can be made in the structures of the embodiments of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, the present disclosure is intended to cover various modifications and variations insofar as they fall within the scope of the appended claims.

100: Semiconductor exposure machine calibration method 110~140: Process 200: Method of fabricating semiconductor structures 210~230: Process 310: First Test Layer 310A: The first pattern part 315: Channel 330: Second Test Layer 330A, 330B: Conductive pattern 335: Channel 340:Interval 345: Assembly channel 350: Third Test Layer 350A, 350B, 350C, 350D, 350E, 350F: The third pattern part 350G: The third pattern part 370: Fourth Test Layer 370A, 370B: The fourth pattern part 400: Semiconductor Structure 410: the first semiconductor pattern layer 410A: The first pattern part 415: Channel 430: the second semiconductor pattern layer 430A, 430B: Conductive pattern 435: Channel 440:Interval 445: Assembly channel 450: the third semiconductor pattern layer 450A, 450B, 450C, 450D, 450E, 450F: The third pattern part 450G: The third pattern part 470: the fourth semiconductor pattern layer 470A, 470B: Fourth pattern part W1,W2: width d: offset d1,d2,d3,d4: distance

The advantages and drawings of the present disclosure should be better understood from the following embodiments and with reference to the drawings. The descriptions of these drawings are merely exemplary embodiments, and therefore should not be construed to limit individual embodiments or to limit the scope of the claimed invention. FIG. 1 shows a flowchart of a calibration method for a semiconductor exposure machine according to an embodiment of the present disclosure; FIG. 2 illustrates a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; FIGS. 3 to 4 are cross-sectional views illustrating structures of different processes of a calibration method for a semiconductor exposure machine according to an embodiment of the present disclosure; 5A to 5C illustrate a plurality of top-view schematic diagrams of different pattern stacks of tested semiconductor structures; FIGS. 6 to 7 are cross-sectional views illustrating structures of different processes of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; and FIGS. 8A to 8C are schematic top views illustrating stacks of different patterns of the formed semiconductor structure.

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100: Semiconductor exposure machine calibration method

110~140: Process

Claims (10)

A method for calibrating a semiconductor exposure machine, comprising: A first semiconductor exposure machine forms a first test layer and a second test layer sequentially stacked through a first mask pattern and a second mask pattern, wherein the first test layer and the second test layer respectively have a first pattern and a second pattern; a second semiconductor exposure machine stacks a third test layer on the second test layer through a third mask pattern, wherein the third test layer has a third pattern; measuring a stacking error between the first pattern on the first test layer and the third pattern on the third test layer by an electron microscope; and The first semiconductor exposure machine and the second semiconductor exposure machine are calibrated according to the stacking error. The method for calibrating a semiconductor exposure machine as claimed in claim 1, wherein the alignment error includes a horizontal offset between the first pattern and the third pattern. The method for calibrating a semiconductor exposure machine according to claim 2, wherein in the process of calibrating the first semiconductor exposure machine and the second semiconductor exposure machine according to the stacking error, the second semiconductor exposure machine is calibrated according to the stacking error The same compensated phase difference is provided to a plurality of reticle patterns, the reticle patterns including the third reticle pattern forming the third pattern. The method for calibrating a semiconductor exposure machine as claimed in claim 1, wherein the first pattern and the second pattern are arranged so that a channel passes through the first test layer and the second test layer, and the third test layer extends to the channel Inside. The method for calibrating a semiconductor exposure machine according to claim 4, further comprising: The second semiconductor exposure machine stacks a fourth test layer on the third test layer through a fourth mask pattern, wherein the fourth test layer includes a fourth pattern; and A stacking error between the second pattern on the second test layer and the fourth pattern on the fourth test layer is measured by an electron microscope. The semiconductor exposure machine calibration method as claimed in claim 5, wherein the fourth test layer extends to the second test layer. The method for calibrating a semiconductor exposure machine according to claim 6, further comprising: After the fourth test layer is formed, it is measured whether any two of the conductive patterns on the second test layer are short-circuited. The method for calibrating a semiconductor exposure machine according to claim 1, wherein the electron microscope comprises a scanning electron microscope. A method of fabricating a semiconductor structure, comprising: Provide the first semiconductor exposure machine and the second semiconductor exposure machine calibrated by the semiconductor exposure machine calibration method as claimed in claim 1; A first semiconductor pattern layer and a second semiconductor pattern layer stacked in sequence are respectively formed with the first mask pattern and the second mask pattern by the first semiconductor exposure machine, wherein the first semiconductor pattern layer and the second pattern layer are respectively formed. The two semiconductor pattern layers respectively have the first pattern and the second pattern; and A third semiconductor pattern layer and a fourth semiconductor pattern layer which are sequentially stacked on the second semiconductor pattern layer are formed by the second semiconductor exposure machine with the third mask pattern and a fourth mask pattern, respectively, to form a The semiconductor structure, wherein the third semiconductor pattern layer and the fourth semiconductor pattern layer respectively have the third pattern and a fourth pattern. The method for manufacturing a semiconductor structure according to claim 9, further comprising: dicing the semiconductor structure into a plurality of dies; and The yield of these dies is measured.

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