TWI809784B - Method for overlay error correction - Google Patents

Abstract

The present disclosure provides a method for overlay error correction. The method includes: obtaining an overlay error based on a lower-layer pattern and an upper-layer pattern of a wafer, wherein the lower-layer pattern is obtained by first fabrication equipment through which the wafer passes, and the upper-layer pattern is obtained by exposure equipment; generating a corrected overlay error based on the overlay error and fabrication processes performed on the wafer after the first fabrication equipment and prior to the exposure equipment; and adjusting the exposure equipment based on the corrected overlay error.

Description

Correction method of overlay error

This application claims priority to US Patent Application Nos. 17/568,033 and 17/568,151 (ie, the priority date is "January 4, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a method for correcting overlay errors.

With the development of the semiconductor industry, it becomes more important to reduce the overlay error of the photoresist pattern and the underlying pattern in the lithography operation. Due to various factors, such as the asymmetric shape of the measurement structure, it is more difficult to correctly measure the overlay error, so a new overlay measurement marker and measurement method is needed to measure the overlay error more accurately.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides an overlay corrected marker. The mark includes a first pattern and a second pattern. The first pattern is arranged on a base and is located at a first level. The first pattern includes a plurality of first patterns and a plurality of second patterns. The first pattern extends along a first direction and is arranged along a second direction different from the first direction. The first Secondary patterns are arranged along the second direction, wherein the contour of each of the plurality of first patterns is different from the contour of each of the plurality of second patterns. The second pattern is disposed at a second level different from the first water level.

Another aspect of the disclosure provides a method for correcting overlay errors. The correction method includes: obtaining an overlay error according to a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing equipment through which the wafer passes, and the upper layer pattern is obtained by an exposure device; generating a corrected overlay error based on the overlay error and a process performed on the wafer after the first fabrication tool and before the exposure tool; and adjusting the exposure tool based on the corrected overlay error.

Another aspect of the disclosure provides a method for correcting overlay errors. The correction method includes: receiving a wafer with a substrate; forming a first pattern on the substrate of the wafer; performing a plurality of processes on the wafer; forming the first pattern on the wafer by an exposure device a second pattern; obtaining an overlay error according to the first pattern and the second pattern of the wafer; generating a corrected overlay error according to the overlay error and the plurality of processes; and adjusting the exposure according to the corrected overlay error equipment.

Embodiments of the disclosure disclose an overlay mark for overlay error measurement. The preceding layer of superimposed marks may comprise different sub-patterns, so that correction data can be generated from each sub-pattern. Selecting correction data from specific sub-patterns can refine the correction overlay error, thus making the correction overlay error more realistic.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which this disclosure pertains will appreciate that the concepts and specific embodiments disclosed below can be readily utilized as modifications Or design other structures or processes to achieve the same purpose as this disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

10:Wafer

20: Overlapping markers

30: Cutting Road

40: Wafer

100: base

110:overlap mark

120: pattern

130: pattern

140: intermediate structure

150: mask

210:overlap mark

210': overlapping marks

210":overlapping mark

220: pattern

220': pattern

222: secondary pattern

224: secondary pattern

226: secondary pattern

226d: Segmentation

230: pattern

232: secondary pattern

300: Semiconductor preparation system

301: Wafer

310: Manufacturing equipment

320-1, ..., 320-N: manufacturing equipment

330: Exposure equipment

340: Stacked measuring equipment

350: Network

360: Controller

370: Overlay (OVL) correction system

400: method

410: Operation

420: Operation

430: Operation

440: Operation

500: Correction method

510: Operation

520: Operation

522: Operation

524: Operation

526: Operation

530: Operation

540: Operation

550: operation

560: Operation

562: Operation

564: Operation

5641: Operation

5642: Operation

5643: Operation

566: Operation

568: Operation

570: Operation

600: Semiconductor Manufacturing System

601: Processor

603: Non-transitory computer-readable storage media

605: busbar

607: Input and output (I/O) interface

609: Network interface

610: user interface

A-A': line (cutting line)

B-B': line (cutting line)

X: direction

Y: Direction

Z: Direction

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components.

FIG. 1 is a top view illustrating a wafer according to some embodiments of the present disclosure.

FIG. 2 is an enlarged view illustrating the dotted region in FIG. 1 of some embodiments of the present disclosure.

FIG. 3 is a top view illustrating overlay marks of some embodiments of the present disclosure.

FIG. 4A is a cross-sectional view along line AA' of FIG. 3 illustrating some embodiments of the present disclosure.

FIG. 4B is a cross-sectional view along line BB' of FIG. 3 illustrating some embodiments of the present disclosure.

FIG. 5 is a top view illustrating overlay marks according to some embodiments of the present disclosure.

FIG. 6 is a top view illustrating overlay marks of some embodiments of the present disclosure.

FIG. 7 is a top view illustrating overlay marks of some embodiments of the present disclosure.

FIG. 8 is a block diagram illustrating a semiconductor manufacturing system according to some embodiments of the present disclosure.

FIG. 9 is a flowchart illustrating a method for generating calibration data by an overlay calibration system according to some embodiments of the present disclosure.

FIG. 10 is a flowchart illustrating a method for correcting overlay errors according to various aspects of the present disclosure.

FIG. 11 is a flowchart illustrating a method for correcting overlay errors according to various aspects of the present disclosure.

FIG. 12 is a flowchart illustrating a method of overlay error correction according to various aspects of the present disclosure.

FIG. 13 is a block diagram illustrating hardware of a semiconductor fabrication system of various aspects of the present disclosure.

The embodiments of the present disclosure illustrated in the drawings will now be described in specific language, or instance. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numbers may be repeated throughout the embodiments, but there is no intention that features of one embodiment apply to another, even if they share the same reference number.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly dictates otherwise. It should be further understood that when the terms "comprising" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

Referring to FIGS. 1 and 2 , FIG. 1 is a top view of a wafer 10 illustrating various aspects of the present disclosure, and FIG. 2 is an enlarged view of the dotted area in FIG. 1 .

As shown in FIGS. 1 and 2 , the wafer 10 is sawed into a plurality of wafers 40 along a dicing street 30 . Each chip 40 may include a semiconductor device, and the semiconductor device may include an active device and/or a passive device. Active components may include a memory chip (e.g., Dynamic Random Access Memory (DRAM chip, static random access memory (SRAM) chip, etc.), a power management chip (e.g., power management integrated circuit (PMIC) chip), a logic chip (e.g., system chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), a radio frequency (RF) chip, a sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (such as a digital signal processing (DSP) chip), a front-end chip (such as an analog front-end (AFE) chip), or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

In some embodiments, overlay marks 20 may be located on dicing lines 30 . Overlay marks 20 may be provided on the corners of the edges of each wafer 40 . In some embodiments, overlay marks may be located on the interior of wafer 40 . The overlay marker 20 can be used to measure whether the current layer, such as the opening of the photoresist layer, is accurately aligned with a pre-layer in the semiconductor manufacturing process.

FIG. 3 is a top view illustrating overlay marks 110 for aligning different layers on a substrate 100 according to various aspects of the present disclosure. As shown in FIG. 3 , a semiconductor device structure, such as a wafer, may include overlay marks 110 on a substrate 100 .

The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Substrate 100 may include an elemental semiconductor, including silicon or germanium in single crystal form, polycrystalline form, or amorphous (amorphous) form; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, phosphide At least one of indium, indium arsenide and indium antimonide. An alloy semiconductor material comprising at least one of SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloyed semiconductor substrate may be a SiGe alloy with a graded Ge feature, where the composition of Si and Ge changes from a ratio at one location of the graded SiGe feature to another. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multilayer structure, or the substrate 100 may include a multilayer compound semiconductor structure.

The overlay mark 110 may include a pattern 120 and a pattern 130 on the substrate 100 . The pattern 120 may be a pattern of a previous layer. The pattern 130 may be a layered pattern. The front floor (or lower floor) may be located at a different level from the current floor (or upper floor). Each pattern 120 (or pattern 130 ) may be located in one of four orthogonal destination areas, two for measuring overlay error in the X direction and two for measuring overlay error in the Y direction.

When using an overlay mark (such as the overlay mark 110 ) to measure an overlay error, the deviation in the X direction is measured along a straight line in the X direction of the overlay mark 110 . The deviation in the Y direction is further measured along a straight line in the Y direction of the overlay mark 110 . A single overlay mark, including patterns 120 and 130, can be used to measure an X-direction and a Y-direction deviation between two layers on the substrate. Therefore, it can be determined whether the current layer and the previous layer are accurately aligned according to the deviation in the X direction and the Y direction. Overlay errors may include deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or a combination of both.

FIG. 4A is a cross-sectional view taken along cutting line AA' of FIG. 3 .

As shown in FIGS. 3 and 4A , a pattern 120 may be disposed on the substrate 100 . The pattern 120 may be disposed in the intermediate structure 140 . In some embodiments, the pattern 120 may include the same material as an isolation structure. In some embodiments, the pattern 120 may be disposed at the same elevation as the isolation structure. Isolation structures may include, for example, shallow trench isolation (STI), field oxidation (FOX), local oxidation of silicon (LOCOS) features, and/or other suitable isolation elements. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorine-doped silicate (FSG), a low-k dielectric material, combinations thereof, and/or other suitable materials.

In some embodiments, the pattern 120 may include the same material as a gate structure. For example, the gate structure may be sacrificial, such as a dymmy gate structure. In some embodiments, the pattern 120 may be disposed at the same elevation as the gate structure. In some embodiments, the pattern 120 may include a dielectric layer whose material is the same as a gate dielectric layer, and a conductive layer whose material is the same as a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. A high-k material may have a dielectric constant (k value) greater than 4. High-k materials may include hafnium oxide (HfO2), zirconia (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also contemplated by the present disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the fabrication technology of the gate electrode layer may be a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The fabrication technology of the work function layer is a metal material, and the metal material may include N-work function metal or P-work function metal. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC ), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also contemplated by the present disclosure. The gate electrode layer can be formed by low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

In some embodiments, pattern 120 may include the same material as a conductive via. material, which can be disposed on a conductive wire, such as the first metal layer (M1 layer). In this embodiment, the pattern 120 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may include metal nitride or other suitable materials. The conductive layer may include metals such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloys or other suitable materials. In this embodiment, the pattern 120 can be formed by a suitable deposition process, such as sputtering and physical vapor deposition (PVD).

The intermediate structure 140 may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. In some embodiments, the intermediate structure 140 may include a conductive layer, such as a metal layer or an alloy layer. In some embodiments, one or more intermediate layers can be formed by a suitable film-forming method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). After the interlayer is formed, a thermal operation, such as rapid thermal annealing, may be performed. In other embodiments, a planarization operation, such as a chemical mechanical polishing (CMP) operation, is performed. In other embodiments, a removal operation, such as an etching process, may be performed. The etching process may include, for example, a dry etching process or a wet etching process. It is understood that additional operations may be provided before, during and after the above process, and for other embodiments of the method, some of the above operations may be replaced or eliminated. The order of operations/processes can be interchanged.

FIG. 4B is a cross-sectional view taken along cutting line BB' of FIG. 3 .

As shown in FIGS. 3 and 4B , the pattern 130 is disposed on the intermediate structure 140 . In some embodiments, pattern 130 may be a plurality of openings defined by mask 150 . A mask 150 may be formed on the intermediate structure 140 and will be removed in a subsequent process. The mask 150 may include a positive or negative photoresist (such as polymer), or a hard mask (such as silicon nitride or silicon oxynitride). The layer including the mask 150 and the pattern 130 can be patterned using a suitable lithography process, for example, forming a photoresist layer on the intermediate structure 140 and exposing the photoresist layer to a pattern through a photomask. pattern, bake and develop the photoresist to form mask 150 and pattern 130. The mask 150 can then be used to define a pattern into the intermediate structure 140 such that the portion of the intermediate structure 140 exposed to the pattern 130 can be removed.

Since a plurality of semiconductor processes are performed after the pattern 120 is formed, the outline of the pattern 120 may be deformed and have an asymmetrical outline. A distorted pattern 120 may result in overlay error estimates with relatively large biases.

FIG. 5 is a top view illustrating an overlay mark 210 according to some embodiments of the present disclosure.

Overlay mark 210 may include various features on substrate 100 such as pattern 220 and pattern 230 . The pattern 220 may be a pattern of a previous layer. The pattern 230 may be a layered pattern. The front floor (or lower floor) may be located at a different level from the current floor (or upper floor). Each pattern 220 (or pattern 230 ) can be located in one of four orthogonal destination areas, two for measuring overlay error in the X direction and two for measuring overlay error in the Y direction.

In some embodiments, pattern 220 may comprise the same material as an isolation feature and may be located at the same elevation as the isolation feature. In some embodiments, pattern 220 may comprise the same material as a gate structure and may be located at the same elevation as the gate structure. In some embodiments, pattern 220 may comprise the same material as a conductive via and may be located at the same elevation as the via.

In some embodiments, each pattern 220 may have a plurality of sub-patterns 222 , 224 , and 226 . In some embodiments, each sub-pattern 222, 224, and 226 may have a different profile in a plan view. In some embodiments, each sub-pattern 222, 224, and 226 may have a different size (eg, surface area in plan view).

Each sub-pattern 222 may extend along a first direction, such as the Y direction. The plurality of sub-patterns 222 can be arranged along a second direction, such as the X direction. In some embodiments, each sub-pattern 222 may have, for example, a rectangular outline.

The plurality of sub-patterns 224 can be arranged along the second direction. Each sub-pattern 224 may extend along a third direction, and the third direction is inclined with respect to the X direction and the Y direction. For example, the sub-pattern 224 may have a first edge and a second edge inclined relative to the first edge. The first edge may extend in a second direction, and the second edge may extend in a third direction. In some embodiments, the sub-pattern 224 may be inclined relative to the sub-pattern 222 . In some embodiments, the size of the sub-pattern 224 may be larger (or exceed) the size of the sub-pattern 222 . In some embodiments, the pitch of the plurality of sub-patterns 224 may be greater than the pitch of the plurality of sub-patterns 222 along the second direction. In some embodiments, the number of sub-patterns 224 may be different from the number of sub-patterns 222 . In some embodiments, the number of sub-patterns 224 may be less than the number of sub-patterns 222 . In some embodiments, each sub-pattern 224 may have, for example, a parallelogram outline.

The plurality of sub-patterns 226 can be arranged along the second direction. Each sub-pattern 226 may have a plurality of segments 226d arranged along the first direction. In some embodiments, the size of each segment 226d may be smaller than the size of each sub-pattern 222 . In some embodiments, the pitch of the plurality of sub-patterns 226 may be the same as the pitch of the plurality of sub-patterns 222 along the second direction. In some embodiments, the segments of the sub-pattern 226 may have, for example, a rectangular outline. Although FIG. 5 illustrates that sub-pattern 224 is disposed between sub-patterns 222 and 226, the relative positions between sub-patterns 222, 224, and 226 may be modified. For example, in other embodiments, sub-pattern 222 may be disposed between sub-patterns 224 and 226 .

The pattern 230 may have a plurality of sub-patterns 232 . Each sub-pattern 232 may extend along the first direction. The plurality of sub-patterns 232 can be arranged along the second direction. In some embodiments, the length of the sub-pattern 232 may be greater than the length of the sub-pattern 222 along the first direction. In some embodiments, the pitch of the plurality of sub-patterns 232 may be the same as the pitch of the plurality of sub-patterns 222 along the second direction. same. In some embodiments, the pitch of the plurality of sub-patterns 232 may be smaller than the pitch of the plurality of sub-patterns 224 along the second direction. In some embodiments, each sub-pattern 232 may have, for example, a rectangular outline. In some embodiments, pattern 220 may consist of sub-patterns with two or more different profiles, while pattern 230 may consist of sub-patterns with a single profile.

Although not shown in FIG. 5, it should be noted that an intermediate structure may be provided to overlay the pattern 220, and the pattern 230 is provided on the intermediate structure.

When using an overlay mark (such as the overlay mark 210 ) to measure an overlay error, the deviation in the X direction is measured along a straight line in the X direction of the overlay mark 210 . The deviation in the Y direction is further measured along a straight line in the Y direction of the overlay mark 210 . A single overlay mark, including patterns 220 and 230, can be used to measure an X-direction and a Y-direction deviation between two layers on the substrate. Whether the current layer and the front layer are accurately aligned can be determined according to the deviation in the X and Y directions. Overlay errors may include deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or a combination of both.

More specifically, images of patterns 220 and 230 obtained from an overlay measurement device can be used to calculate overlay errors. As described above, after the pattern 220 is formed, a plurality of semiconductor manufacturing processes are performed; the outline of the pattern 220 may be deformed and have an asymmetrical outline. In order to obtain an overlay error that is more in line with the actual situation, the overlay error obtained from the overlay measurement device can be further corrected. An overlay calibration system can receive optical image information from the pattern of the previous layer and the pattern of the current layer, and then generate a plurality of calibration data corresponding to each corresponding calibration parameter. Therefore, the overlay correction system can generate a corrected overlay error. A controller (eg, computer) will then send a signal indicating how to adjust the exposure equipment to correct for overlay errors. Thus, the exposure equipment used to define the pattern 230 will be adjusted to correct for overlay errors. In some embodiments, the calibration data can be configured to generate an offset value in the X direction, an offset value in the Y direction, or a combination thereof for compensating for overlay errors.

Since one or more semiconductor processes will be performed on the wafer after the formation of the front layer, the profile of the overlay mark in the front layer may be changed due to different processes, such as a deposition process, an etching process, a chemical mechanical polishing process or Distorted by other processes and has an asymmetrical profile. Therefore, the overlay error of these deformed patterns according to the previous layer may deviate from the actual situation. It was found that each cell of the calibration data may have different degrees of error depending on the pattern with the different contours. That is to say, a set of calibration data may have a small error (or a deviation relative to the actual situation) according to pattern A, but a large error according to pattern B, and its profile is different from that of pattern A. Another set of calibration data may have the opposite result: a larger error according to pattern A and a smaller error according to pattern B.

For example, an overlay correction system may include multiple sets of correction parameters, such as field-to-field spread and field-to-field rotation. If an etching process is performed after the formation of the front layer, the correction data generated by the sub-pattern 224 (generated by the correction parameters related to the field-to-field spread) may have a small error relative to the actual situation. If a chemical mechanical polishing is performed after the formation of the previous layer, the calibration data generated by the sub-pattern 226 (generated by the calibration parameter related to the field-to-field rotation) may have a small error relative to the actual situation. Therefore, the correction data generated by the sub-pattern 222 (generated by the correction parameters that do not belong to the inter-field expansion and inter-field rotation) may have a small error relative to the actual situation. By selecting calibration data with a smaller deviation from the actual situation, a calibration overlay error with a smaller deviation can be estimated.

As mentioned above, calibration data from different patterns (or sub-patterns) may have different degrees of error. In an embodiment of the present disclosure, the front layer may include patterns with different contours, and each pattern may be used to generate a series of respective calibration data. These correction data from different sub-patterns can be selected to obtain corrected overlay errors with less deviation from the actual situation. The exposure equipment will be adjusted according to the correction of the overlay error. In the subsequent semiconductor process, the front layer and When the alignment accuracy between layers will be improved.

FIG. 6 is a top view illustrating an overlay mark 210 ′ according to some embodiments of the present disclosure.

The overlay mark 210' shown in FIG. 6 may be similar to the overlay mark 210 shown in FIG. 5, except for the composition of the pattern 220'. In some embodiments, the CMP process may be omitted after forming the front layer, and the pattern 220 ′ may consist of sub-patterns 222 and 224 . In this embodiment, calibration parameters that do not belong to interfield extension can be selected from the sub-pattern 222 to generate calibration data.

As mentioned above, calibration data from different patterns (or sub-patterns) may have different degrees of error. In this embodiment, the front layer may include patterns with different contours, which may be used to produce corrected overlay errors that deviate less from reality. The exposure equipment will be adjusted according to this correction overlay error, and in the next semiconductor process, the alignment accuracy between the previous layer and the current layer will be improved.

FIG. 7 is a top view illustrating an overlay mark 210 ″ of some embodiments of the present disclosure.

The overlay mark 210" shown in FIG. 7 may be similar to the overlay mark 210 shown in FIG. 5, except for the composition of the pattern 220". In some embodiments, the etching process can be omitted after the formation of the front layer, and the pattern 220" can be composed of sub-patterns 222 and 226. In this embodiment, the correction parameters that do not belong to the inter-field rotation can be selected from the sub-pattern 222, to generate calibration data.

As mentioned above, calibration data from different patterns (or sub-patterns) may have different degrees of error. In this embodiment, the front layer may include patterns with different contours, which may be used to produce corrected overlay errors that deviate less from reality. The exposure equipment will be adjusted according to this correction overlay error, and in the next semiconductor process, the alignment accuracy between the previous layer and the current layer will be improved.

FIG. 8 is a block diagram illustrating a semiconductor fabrication system 300 according to some embodiments of the present disclosure.

The semiconductor fabrication system 300 may include a plurality of fabrication equipment 310 , 320 - 1 , . . . , 320 -N, an exposure equipment 330 , and an overlay measurement equipment 340 . The fabrication equipment 310 , 320 - 1 , .

Fabrication apparatus 310 may be configured to form a pattern, such as pattern 220 shown in FIG. 5 , in a front layer. In some embodiments, fabrication equipment 310 may be configured to form an isolation structure, a gate structure, a conductive via, or other layers. Fabrication equipment 320-1, . . . , and 320-N may be configured to form an intermediate structure, such as intermediate structure 140 shown in FIG. 4A. Each of the fabrication equipment 320-1, . process or other process.

Exposure apparatus 330 may be configured to form a pattern in a layer, such as pattern 230 shown in FIG. 5 .

The overlay measurement device 340 may be configured to obtain optical images of the patterns of the previous layer and the current layer, and generate an overlay error based on the optical images of the patterns of the previous layer and the current layer.

The network 350 can be the Internet or an internal network using an Internet protocol such as Transmission Control Protocol (TCP). Through the network 350, each of the fabrication equipment 310, 320-1-320-N, the exposure equipment 330, and the overlay measurement equipment 340 can download or upload from the controller 360 or the overlay correction system 370 information about the wafer or fabrication equipment. In-Product (WIP) information.

The controller 360 may include a processor, such as a central processing unit (CPU), to generate corrected overlay errors based on the overlay measurement device 340 and the correction data generated from the overlay correction system 370 .

Overlay correction system 370 may include correction parameters associated with information about the optical image. number, so calibration data can be generated from the corresponding calibration parameters. The overlay correction system 370 may include, for example, a computer or a server. In some embodiments, the calibration data can be generated or calculated by program code or programming language. In some embodiments, the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination thereof may be generated by a formula including correction parameters. Although FIG. 8 illustrates overlay calibration system 370 in signal connection with overlay measurement device 340 via network 350, the disclosure is not intended to be limiting. In other embodiments, the overlay correction system 370 may be a program built into the overlay measurement device 340 .

Although FIG. 8 does not show any other fabrication equipment preceding fabrication facility 310, this illustrative embodiment is not intended to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged before the manufacturing equipment 310, and may be used to perform various processes according to design requirements.

In the exemplary embodiment, wafer 301 is transferred to fabrication facility 310 to begin a series of different processes. Wafer 301 may be formed with at least one layer of material through various stages of processing. The exemplary embodiments are not intended to limit the wafer 301 process. In other exemplary embodiments, wafer 301 may include various layers, or any stage between initiation and completion of a product, before wafer 301 is transferred to fabrication facility 310 . In an exemplary embodiment, wafer 301 may be sequentially processed by fabrication equipment 310 , 320 - 1 to 320 -N, exposure equipment 330 , and overlay measurement equipment 340 .

FIG. 9 is a flowchart illustrating a method 400 of generating calibration data by an overlay calibration system according to various aspects of the present disclosure.

Method 400 begins at operation 410 in which an overlay correction system, such as overlay correction system 370, is provided. In some embodiments, the overlay correction system 370 may include a plurality of correction parameters P1, P2, .

Method 400 continues with operation 420, where optical image information is provided. For example, an optical image can be generated from patterns (or sub-patterns) A, B, C, and D, and the information of the optical image can be uploaded to the network. In some embodiments, patterns or sub-patterns A, B, C, and D may correspond to sub-pattern 222 , sub-pattern 224 , sub-pattern 226 , and pattern 230 , respectively.

Method 400 continues with operation 430, where correction data is generated. In some embodiments, pattern (or sub-pattern) A may be used to generate correction data a1 from parameter P1, correction data a2 from parameter P2, and so on. Therefore, the correction data a1, a2, . . . , and aN are generated according to the pattern or sub-pattern A and the correction parameters P1-PN. Similarly, the correction data b1, b2, ..., and bN are generated according to the pattern (or sub-pattern B) and the correction parameters P1-PN, and the correction data c1, c2, ..., and cN are generated according to the pattern (or sub-pattern B) )C and correction parameters P1-PN are generated, and correction data d1, d2, . . . , and dN are generated according to pattern (or sub-pattern) D and correction parameters P1-PN.

Method 400 continues with operation 440 where a correction overlay error is generated. The corrected overlay error can be generated according to the corrected data of the corresponding parameters P1-PN. Correcting the overlay error may be expressed by a formula including an offset value in the X direction, an offset value in the Y direction, or a combination of both and the overlay error resulting from the overlay measurement device.

In some other embodiments, operation 430 may be omitted. In this embodiment, the correction of the overlay error, including the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination thereof, can be generated by the correction parameters. Each of the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination of both can be represented by a formula including the correction parameter as a variable. These variables can be determined upon receipt of the optical image information, thereby producing a deviation in the X direction (ΔX), a deviation in the Y direction (ΔY), or a combination of both.

FIG. 10 , FIG. 11 and FIG. 12 are flowcharts illustrating a calibration method 500 for overlay calibration in various aspects of the present disclosure.

Referring to FIG. 10, calibration method 500 begins at operation 510, where a wafer is received. A wafer may include a semiconductor substrate, such as a silicon substrate. A wafer may include a plurality of wafers separated by dicing streets.

The calibration method 500 continues with operation 520, wherein a first pattern (eg, a front-layer pattern) is formed by a first fabrication tool. Prior to forming the first pattern, a number of processes may be performed on the base of the wafer to form a number of features beneath the first pattern. In some embodiments, the first pattern may include a dielectric material, a conductive material or other suitable materials. In some embodiments, the first pattern may be formed in an operation configured to form, for example, gate structures, isolation features, conductive vias, or other features. In some embodiments, the first pattern may correspond to pattern 220 shown in FIG. 5 .

Referring to FIG. 11, operation 520 may include operations 522, 524, and 526, wherein a plurality of first, second, and third sub-patterns are formed. In some embodiments, the first, second and third patterns can be formed simultaneously. In some embodiments, each of the first, second, and third sub-patterns may correspond to sub-patterns 222, 224, and 226 shown in FIG. 5, respectively.

Returning to FIG. 10 , the calibration method 500 proceeds to operation 530 , wherein after forming the first pattern, a plurality of processes are performed on the substrate of the wafer. These processes can be used to form an intermediate layer covering the first pattern. The intermediate layer can be formed by a variety of manufacturing equipment that can be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

The calibration method 500 continues with operation 540, wherein a second pattern (eg, a layer) is formed by the exposure apparatus. In some embodiments, the second pattern may be an opening pattern of a mask, such as a photoresist. In some embodiments, the second pattern may correspond to pattern 230 shown in FIG. 5 .

Calibration method 500 continues with operation 550 where an overlay error associated with movement in the X and Y directions is generated by the overlay measurement device. In some embodiments, the first pattern, including the first, second and third sub-patterns and a plurality of optical images of the second pattern are generated by an overlay measurement device, and an overlay error can be generated based on these optical images. In some embodiments, the overlay error may include a deviation in the X direction (ΔX), a deviation in the Y direction (ΔY), or a combination of both.

The correction method 500 continues with operation 560 in which a corrected overlay error is generated by correcting the overlay error obtained in operation 550 . In some embodiments, an offset value in the X direction, an offset value in the Y direction, or a combination thereof may be generated to compensate for the overlay error generated in operation 550 . In some embodiments, the correction overlay error may be determined or calculated from operations for forming the above-described intermediate layer below the current layer, such as operation 530 .

Referring to FIG. 12 , operation 560 may include operations 562 , 564 , 566 and 568 . Operation 562 may include sorting the correction parameters into first, second, and third groups. For example, correction parameters may be divided into a first group related to interfield extension, a second group related to interfield rotation, and a third group not belonging to the first and second groups.

Operation 564 may include operations 5641, 5642, and 5643, wherein a first calibration data, a second calibration data, and a third calibration data are generated from the first, second, and third order patterns. Each of the first, second or third patterns can be used to generate first, second and third calibration data. That is to say, nine units of correction data can be generated according to the first, second and third patterns. The first, second and third calibration profiles may correspond to first, second and third sets of calibration parameters, respectively.

Operation 566 may include selecting data for use in generating corrected overlay errors. In some embodiments, the first calibration data is selected from the first pattern respectively, and the second calibration data is selected from the first pattern A secondary pattern is selected, and a third calibration data is selected from a third pattern.

For example, correction parameters P1, P2, ... and P9, and parameters P1, P2 and P3 belong to a first group, parameters P4, P5 and P6 belong to a second group, and parameters P7, P8 and P9 belong to a third group. Calibration data a1, a2, ..., and a9 are produced by the first group of sub-patterns, calibration data b1, b2, ..., and b9 are produced by the second group of sub-patterns, and calibration data c1, c2, ..., and c9 are generated by the third set of subpatterns. In this embodiment, the calibration data a1 , a2 , a3 , b4 , b5 , b6 , c7 , c8 , and c9 are selected to generate an offset value in the X direction, an offset value in the Y direction, or a combination thereof. Accordingly, a corrected overlay error may be generated based on the above-described offset and the overlay error generated in operation 550 .

In other embodiments, the number of sets of calibration parameters may be determined by the process performed on the wafer in operation 530 . In some embodiments, an etching process or a chemical mechanical polishing process can be omitted, and the calibration parameters can be divided into two groups accordingly. In this case, if there are correction parameters P1, P2, ... and P9, the correction data a1-a6 can be selected from the first set of sub-patterns, and the correction data b7-b9 can be selected from the second set of sub-patterns, to produce corrected overlay errors. In other embodiments, according to how to classify the processes, the number of groups of calibration parameters may be greater than 3, so the calibration parameters are classified according to the classified processes.

Operation 568 may include generating a corrected overlay error based on the overlay error and the selected correction data. Operation 568 may be performed by a controller, such as controller 360 shown in FIG. 8 .

Operations 562 , 564 , 566 and/or 568 may be performed by an overlay correction system, such as overlay correction system 370 shown in FIG. 8 .

In other embodiments, operations 564, 566, and 566 may be omitted. In this embodiment, the correction of the overlay error, including the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination thereof, can be generated by the correction parameters. Each deviation in X direction (△X), deviation in Y direction The difference (ΔY), or a combination of both, can be represented by a formula including the correction parameter as a variable. For example, correction parameters P1, P2, ... and P9, and parameters P1, P2 and P3 belong to the first group, parameters P4, P5 and P6 belong to the second group, and parameters P7, P8 and P9 belong to the third group. The variables comprising calibration parameters P1-P3, P4-P6 and P7-P9 can be determined from the optical information of the first set of sub-patterns, the second set of sub-patterns and the third set of sub-patterns, respectively. Therefore, it is possible to correct the overlay error with certainty.

Referring to FIG. 10 , the correction method 500 proceeds to operation 570 , in which the exposure equipment is adjusted according to the correction overlay error. In some embodiments, operation 570 may include adjusting the position of a reticle of the exposure apparatus so that the next exposure process can be performed with less overlay error.

The calibration method 500 includes categorizing calibration parameters into different groups. As mentioned above, calibration data from different patterns (or sub-patterns) may have different degrees of error. In this embodiment, the front layer may include patterns with different contours, which may be used to produce a corrected overlay error that deviates less from the actual situation. The exposure equipment will be adjusted according to this correction overlay error, and in the subsequent semiconductor manufacturing process, the alignment accuracy between the front layer and the current layer will be improved.

The correction method 500 is just an example, and is not intended to limit the content of the present disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, or after each operation of method 500, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the method. In some embodiments, calibration method 500 may also include operations not depicted in FIGS. 10-12 . In some embodiments, calibration method 500 may include one or more of the operations described in FIGS. 10-12 .

The processes illustrated in Figures 10-12 may be implemented in the controller 360, or computing system that organizes the fabrication of wafers by controlling each part or part of the fabrication equipment in the facility. FIG. 13 is a block diagram illustrating the hardware of a semiconductor fabrication system 600 of various aspects of the present disclosure. System 600 includes one or more hardware processors 601 and coded, i.e. stored, program codes (i.e. A non-transitory computer-readable storage medium 603 of a set of executable instructions). The computer readable storage medium 603 may also be encoded with instructions for interfacing with manufacturing equipment for producing semiconductor devices. The processor 601 is electrically coupled to the computer readable storage medium 603 via the bus bar 605 . The processor 601 is also electrically coupled to an input and output (I/O) interface 607 via a bus bar 605 . The network interface 609 is also electrically connected to the processor 601 via the bus bar 605 . The network interface is connected to a network, so the processor 601 and the computer-readable storage medium 603 can be connected to external components via the network 350 . The processor 601 is configured to execute computer program codes encoded in the computer-readable storage medium 605 , so that the system 600 can be used to perform some or all of the operations described in the methods shown in FIGS. 10 to 12 .

In some exemplary embodiments, processor 601 may be, but is not limited to, a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. Various circuits or units are within the scope of this disclosure.

In some exemplary embodiments, computer readable storage medium 603 may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, computer readable storage medium 603 includes a semiconductor or solid state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read only memory (ROM), a hard disk and/or or a CD. In one or more exemplary embodiments utilizing compact discs, computer readable storage medium 603 also includes compact disc-read only memory (CD-ROM), compact disc-read/write (CD-R/W) and/or digital Video Disc (DVD).

In some exemplary embodiments, the storage medium 603 stores computer program codes configured to enable the system 600 to execute the methods shown in FIGS. 8 to 12 . In one or more exemplary embodiments, the storage medium 601 also stores information required for performing the methods shown in FIGS. Execute the operations of the methods shown in FIG. 8 to FIG. 12 . In some exemplary embodiments, a user interface 610 , such as a graphical user interface (GUI), may be provided for users to operate on the system 600 .

In some exemplary embodiments, the storage medium 603 stores instructions for interfacing with external machines. The instructions enable the processor 601 to generate instructions readable by an external machine to effectively implement the methods shown in FIGS. 8-12 during analysis.

System 600 includes input and output (I/O) interface 607 . The I/O interface 607 is connected with external circuits. In some exemplary embodiments, the I/O interface 607 may include, but is not limited to, a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and/or cursor keys for providing information to the processor 601. convey information and orders.

In some exemplary embodiments, the I/O interface 607 may include a display, such as a cathode ray tube (CRT), liquid crystal display (LCD), speaker, and the like. For example, a monitor displays information.

The system 600 may also include a network interface 609 coupled to the processor 601 . Network interface 609 allows system 600 to communicate with network 350 to which one or more other computer systems are connected. For example, system 600 can be connected to fabrication equipment 310 , 320 - 1 , .

One aspect of the present disclosure provides an overlay corrected marker. The mark includes a first pattern and a second pattern. The first pattern is arranged on a base and is located at a first water level. The first pattern includes a plurality of first patterns and a plurality of second patterns. The first pattern extends along a first direction and is arranged along a second direction different from the first direction. The second pattern is arranged along the second direction, wherein the outline of each of the plurality of first patterns and Each of the plurality of second patterns has a different profile. The second pattern is disposed at a second level different from the first water level.

Another aspect of the disclosure provides a method for correcting overlay errors. The correction method includes: obtaining an overlay error according to a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing equipment through which the wafer passes, and the upper layer pattern is obtained by an exposure device; generating a corrected overlay error based on the overlay error and a process performed on the wafer after the first fabrication tool and before the exposure tool; and adjusting the exposure tool based on the corrected overlay error.

Another aspect of the disclosure provides a method for correcting overlay errors. The correction method includes: receiving a wafer with a substrate; forming a first pattern on the substrate of the wafer; performing a plurality of processes on the wafer; forming the first pattern on the wafer by an exposure device a second pattern; obtaining an overlay error according to the first pattern and the second pattern of the wafer; generating a corrected overlay error according to the overlay error and the plurality of processes; and adjusting the exposure according to the corrected overlay error equipment.

Embodiments of the disclosure disclose an overlay mark for overlay error measurement. The preceding layer of superimposed marks may comprise different sub-patterns, so that correction data can be generated from each sub-pattern. Selecting correction data from specific sub-patterns can refine the correction overlay error, thus making the correction overlay error more realistic.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the process described in the specification, Particular embodiments of machines, manufacture, compositions of matter, means, methods and steps. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

100: base 210:overlap mark 220: pattern 222: secondary pattern 224: secondary pattern 226: secondary pattern 226d: Segmentation 230: pattern 232: secondary pattern X: direction Y: Direction Z: Direction

Claims (19)

A method for correcting an overlay error, comprising: obtaining a plurality of overlay errors according to a plurality of sub-patterns of a lower-layer pattern and a plurality of sub-patterns of an upper-layer pattern of a wafer, wherein the plurality of sub-patterns of the lower-layer pattern are obtained by The wafer is obtained through a first manufacturing equipment, and the plurality of sub-patterns of the upper layer pattern are obtained by an exposure equipment, and the plurality of overlay errors are different from each other; according to the plurality of overlay errors and in the first manufacturing A process performed on the wafer after the apparatus and before the exposure apparatus selects an overlay error to generate a corrected overlay error; and adjusts the exposure apparatus based on the corrected overlay error. The correction method as claimed in claim 1, wherein the plurality of sub-patterns of the lower layer pattern include a plurality of first-time patterns and a plurality of second-time patterns, and the contour of each of the plurality of first-time patterns and Each of the plurality of second patterns has a different profile. The correction method as described in claim 2, wherein generating the correction overlay error comprises: dividing the plurality of correction parameters into a first group of correction parameters and a second group of correction parameters; obtaining a first corresponding data of the first set of calibration parameters, and obtaining a second corresponding data of the second set of calibration parameters from the plurality of second sub-patterns; and according to the plurality of overlay errors, the first The corresponding data and the second corresponding data generate the corrected overlay error. The calibration method as described in claim 3, further comprising: obtaining a third corresponding data of the first set of calibration parameters from the plurality of second patterns, and obtaining the second data from the plurality of second patterns a fourth corresponding data of the set of calibration parameters; and selecting the first corresponding data and the second corresponding data to determine the corrected overlay error. The calibration method according to claim 2, wherein the pitch of the plurality of second-time patterns is different from the pitch of the plurality of first-time patterns. The correction method according to claim 2, wherein in a plan view, each of the plurality of second sub-patterns extends along a third direction different from the first direction and the second direction. The calibration method according to claim 2, wherein each of the plurality of second sub-patterns includes a plurality of segments arranged along the first direction. The correction method according to claim 2, wherein in a plan view, the size of each of the plurality of second-time patterns is different from the size of each of the plurality of first-time patterns. The calibration method according to claim 2, wherein the number of the plurality of second-time patterns is different from the number of the plurality of first-time patterns. The calibration method as claimed in claim 1, wherein the process includes at least one of an etching process, a deposition process and a chemical mechanical polishing process. The calibration method according to claim 1, wherein adjusting the exposure device includes adjusting a position of a mask of the exposure device. A method for correcting overlay errors, comprising: receiving a wafer with a substrate; forming a first pattern on the substrate of the wafer, the first pattern including a plurality of sub-patterns; forming an intermediate structure by at least one process to cover the first pattern; by means of an exposure device, forming a second pattern on the intermediate structure; obtaining a plurality of overlay errors according to the plurality of sub-patterns and the second pattern of the first pattern of the wafer , the plurality of overlay errors are different from each other; according to the plurality of overlay errors and the process, a corrected overlay error is generated; and the exposure equipment is adjusted according to the corrected overlay error. The correction method as claimed in claim 12, wherein forming the first pattern includes: forming a plurality of first-time patterns; and forming a plurality of second-time patterns, wherein the outline of each of the plurality of first-time patterns is consistent with Each of the plurality of second patterns has a different profile. The correction method as claimed in claim 13, wherein generating the correction overlay error comprises: Dividing the plurality of calibration parameters into a first group of calibration parameters and a second group of calibration parameters; respectively obtaining a first corresponding data of the first group of calibration parameters from the plurality of first-time patterns, and obtaining from the plurality of first-time patterns Obtaining a second corresponding data of the second set of calibration parameters in the second pattern; and generating the corrected superposition error according to the superposition error, the first corresponding data and the second corresponding data. The calibration method as described in claim 14, further comprising: obtaining a third corresponding data of the first set of calibration parameters from the plurality of second patterns, and obtaining the second set from the plurality of second patterns a fourth corresponding data of calibration parameters; and selecting the first corresponding data and the second corresponding data to determine the corrected overlay error. The correction method according to claim 13, wherein in a plan view, each of the plurality of second sub-patterns extends along a third direction different from the first direction and the second direction, and the plurality of second sub-patterns Each of the patterns includes a plurality of segments arranged along the first direction, and the pitch of the plurality of second patterns is different from the pitch of the plurality of first patterns. The correction method as claimed in claim 13, wherein in a plan view, the size of each of the plurality of second-time patterns is different from the size of each of the plurality of first-time patterns, and the plurality of The number of second-time patterns is different from the number of the plurality of first-time patterns. The calibration method as claimed in claim 12, wherein the at least one process for forming the intermediate structure At least one of an etching process, a deposition process and a chemical mechanical polishing process is included. The calibration method as claimed in claim 12, wherein adjusting the exposure device includes adjusting a position of a mask of the exposure device.