CN116435291A

CN116435291A - Overlay error measurement marking

Info

Publication number: CN116435291A
Application number: CN202211303661.2A
Authority: CN
Inventors: 马士元
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2022-01-04
Filing date: 2022-10-24
Publication date: 2023-07-14
Also published as: TW202328811A; TWI809784B; CN116400573A; TW202328699A; TWI817418B

Abstract

The present disclosure provides a overlay error measurement marker. The measurement mark comprises a first pattern and a second pattern. The first pattern is arranged on a substrate and is positioned on a first horizontal height. The first pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns. The first sub-patterns extend along a first direction and are arranged along a second direction different from the first direction. The second sub-patterns are arranged in a second direction, wherein a contour of each of the plurality of first sub-patterns is different from a contour of each of the plurality of second sub-patterns. The second pattern is disposed at a second water level different from the first water level.

Description

Overlay error measurement marking

Cross reference

The present application claims priority from U.S. patent application Ser. Nos. 17/568,033 and 17/568,151 (i.e., priority date "2022, 1, 4"), the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a overlay measurement marking.

Background

With the development of the semiconductor industry, it has become more important to reduce overlay errors (overlay errors) of photoresist patterns and underlayer patterns in photolithography operations. Due to various factors, such as the asymmetric shape of the measurement structure, making it more difficult to properly measure overlay errors, a new overlay measurement mark and measurement method is needed to more accurately measure overlay errors.

The above description of "prior art" merely provides background, and it is not admitted that the above description of "prior art" reveals the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure.

Disclosure of Invention

One aspect of the present disclosure provides a overlay corrected marker. The mark includes a first pattern and a second pattern. The first pattern is arranged on a substrate and located at a first water level. The first pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns. The first sub-patterns extend along a first direction and are arranged along a second direction different from the first direction. The second sub-patterns are arranged along the second direction, wherein a contour of each of the plurality of first sub-patterns is different from a contour of each of the plurality of second sub-patterns. The second pattern is disposed at a second level different from the first level.

Another aspect of the present disclosure provides a method of correcting overlay error. The correction method comprises the following steps: obtaining a stacking error according to a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing device through which the wafer passes, and the upper layer pattern is obtained by an exposure device; generating a corrected overlay error based on the overlay error and a process performed on the wafer after the first fabrication tool and before the exposure tool; and adjusting the exposure apparatus according to the corrected overlay error.

Another aspect of the present disclosure provides a method of correcting overlay error. The correction method comprises the following steps: receiving a wafer having a substrate; forming a first pattern on a substrate of the wafer; performing a plurality of processes on the wafer; forming a second pattern on the first pattern of the wafer by an exposure apparatus; obtaining a superposition error according to the first pattern and the second pattern of the wafer; generating a corrected overlay error based on the overlay error and the plurality of processes; and adjusting the exposure apparatus according to the corrected overlay error.

Embodiments of the present disclosure disclose a overlay mark for overlay error measurement. The front layer of the overlay mark may include different sub-patterns so that correction data may be generated from each sub-pattern. Selecting correction data from a particular sub-pattern may refine the corrected overlay error, thus making the corrected overlay error more realistic.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure of the present application may be more fully understood when the detailed description and claims are taken in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

Fig. 1 is a top view illustrating a wafer according to some embodiments of the present disclosure.

Fig. 2 is an enlarged view illustrating the dotted areas in fig. 1 of some embodiments of the present disclosure.

Fig. 3 is a top view illustrating overlay marks according to some embodiments of the present disclosure.

Fig. 4A is a cross-sectional view along line A-A' of fig. 3 illustrating some embodiments of the present disclosure.

Fig. 4B is a cross-sectional view along line B-B' of fig. 3 illustrating some embodiments of the present disclosure.

Fig. 5 is a top view illustrating overlay marks according to some embodiments of the present disclosure.

Fig. 6 is a top view illustrating overlay marks according to some embodiments of the present disclosure.

Fig. 7 is a top view illustrating overlay marks according to some embodiments of the present disclosure.

Fig. 8 is a block diagram illustrating a semiconductor fabrication system in accordance with some embodiments of the present disclosure.

FIG. 9 is a flow chart illustrating a method of generating correction data by a overlay correction system in accordance with some embodiments of the present disclosure.

FIG. 10 is a flow chart illustrating a method of correcting overlay errors in accordance with aspects of the present disclosure.

FIG. 11 is a flow chart illustrating a method of correcting overlay errors in accordance with aspects of the present disclosure.

FIG. 12 is a flow chart illustrating a method of correction of overlay error in accordance with aspects of the present disclosure.

Fig. 13 is a block diagram illustrating hardware of a semiconductor fabrication system of various aspects of the present disclosure.

Reference numerals illustrate:

10: wafer with a plurality of wafers

20: overlay mark

30: cutting path

40: chip

100: substrate

110: overlay mark

120: pattern and method for producing the same

130: pattern and method for producing the same

140: intermediate structure

150: mask film

210: overlay mark

210': overlay mark

210": overlay mark

220: pattern and method for producing the same

220': pattern and method for producing the same

222: secondary pattern

224: secondary pattern

226: secondary pattern

226d: segmentation

230: pattern and method for producing the same

232: secondary pattern

300: semiconductor manufacturing system

301: wafer with a plurality of wafers

310: manufacturing apparatus

320-1, …,320-N: manufacturing apparatus

330: exposure apparatus

340: stacked measuring apparatus

350: network system

360: controller for controlling a power supply

370: overlay (OVL) correction system

400: method of

410: operation of

420: operation of

430: operation of

440: operation of

500: correction method

510: operation of

520: operation of

522: operation of

524: operation of

526: operation of

530: operation of

540: operation of

550: operation of

560: operation of

562: operation of

564: operation of

5641: operation of

5642: operation of

5643: operation of

566: operation of

568: operation of

570: operation of

600: semiconductor manufacturing system

601: processor and method for controlling the same

603: non-transitory computer readable storage medium

605: bus line

607: input and output (I/O) interfaces

609: network interface

610: user interface

A-A': line (cutting path)

B-B': line (cutting path)

X: direction of

Y: direction of

Z: direction of

Detailed Description

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described with particular language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any alterations and modifications in the described embodiments, and any further applications of the principles as described herein are contemplated as would normally occur to one skilled in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but it is not intended that features of one embodiment be applicable to another embodiment even if they share the same reference numerals.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections. Various elements, components, regions, layers or sections may be described without limitation by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, region, layer or section discussed below could be termed a second element, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

Referring to fig. 1 and 2, fig. 1 is a top view of a wafer 10 illustrating aspects of the present disclosure, and fig. 2 is an enlarged view of a dotted area in fig. 1.

As shown in fig. 1 and 2, the wafer 10 is sawn along dicing streets 30 into a plurality of dies 40. Each chip 40 may include a semiconductor element that may include an active element and/or a passive element. The active element may include a memory chip (e.g., dynamic Random Access Memory (DRAM) chip, static Random Access Memory (SRAM) chip, etc.), a power management chip (e.g., power Management Integrated Circuit (PMIC) chip), a logic chip (e.g., system on a chip (SoC), central Processing Unit (CPU), graphics Processing Unit (GPU), application Processor (AP), microcontroller, etc.), a Radio Frequency (RF) chip, a sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (e.g., digital Signal Processing (DSP) chip), a front end chip (e.g., analog Front End (AFE) chip), or other active element. The passive element may include a capacitor, a resistor, an inductor, a fuse, or other passive element.

In some embodiments, overlay mark 20 may be located on scribe line 30. The overlay mark 20 may be disposed at a corner of an edge of each chip 40. In some embodiments, the overlay mark may be located inside the chip 40. The overlay mark 20 may be used to measure whether a current layer (current layer), such as an opening in a photoresist layer, is precisely aligned with a previous layer (pre-layer) in a semiconductor process.

Fig. 3 is a top view illustrating overlay marks 110 for aligning different layers on a substrate 100 in accordance with aspects of the present disclosure. As shown in fig. 3, a semiconductor device structure, such as a wafer, may include overlay marks 110 on a substrate 100.

The substrate 100 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 100 may include an elemental semiconductor including silicon or germanium in single crystal form, polycrystalline form, or amorphous (amorphorus) form; a compound semiconductor material comprising at least one of silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and indium antimonide. An alloy semiconductor material comprising at least one of SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a graded Ge characteristic, wherein the composition of Si and Ge changes from the ratio of one location of the graded SiGe characteristic to the ratio of another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multi-layered structure, or the substrate 100 may include a multi-layered compound semiconductor structure.

Overlay mark 110 may include a pattern 120 and a pattern 130 on substrate 100. Pattern 120 may be a front layer pattern. Pattern 130 may be a pattern of a current layer. The front layer (or lower layer) may be located at a different horizontal level than the current layer (or upper layer). Each pattern 120 (or pattern 130) may be located in one of four orthogonal destination areas, two for measuring overlay error in the X-direction and two for measuring overlay error in the Y-direction.

When a overlay error is measured using overlay marks (e.g., overlay mark 110), the deviation in the X-direction is measured along a line in the X-direction of the overlay mark 110. The Y-direction deviation is further measured along a line in the Y-direction of the overlay mark 110. A single overlay mark, including

patterns

120 and 130, may be used to measure the deviation in an X-direction and a Y-direction between two layers on a substrate. Thus, it can be determined whether the current layer and the previous layer are precisely aligned according to the deviation of the X direction and the Y direction. The overlay error may include a deviation in the X direction (Δx), a deviation in the Y direction (Δy), or a combination of both.

Fig. 4A is a sectional view taken along the cutting line A-A' of fig. 3.

As shown in fig. 3 and 4A, the pattern 120 may be disposed on the substrate 100. The pattern 120 may be disposed in the intermediate structure 140. In some embodiments, the pattern 120 may comprise the same material as an isolation structure. In some embodiments, the pattern 120 may be disposed at the same elevation as the isolation structures. The isolation structures may include, for example, shallow Trench Isolation (STI), field Oxide (FOX), local oxidation of silicon (LOCOS) features, and/or other suitable isolation elements. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride (silicon oxide-nitride), fluorine doped silicate (FSG), a low-k dielectric material, combinations thereof, and/or other suitable materials.

In some embodiments, the pattern 120 may include a gate structure of the same material. For example, the gate structure may be sacrificial, such as a dummy (dummy) gate structure. In some embodiments, the pattern 120 may be disposed at the same elevation as the gate structure. In some embodiments, the pattern 120 may include a dielectric layer of the same material as a gate dielectric layer and a conductive layer of the same material as a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may comprise a dielectric material, such as a high-k dielectric material. The high-k material may have a dielectric constant (k value) greater than 4. The high-k material may include hafnium oxide (HfO 2), zirconium oxide (ZrO 2), lanthanum oxide (La 2O 3), yttrium oxide (Y2O 3), aluminum oxide (Al 2O 3), titanium oxide (TiO 2), or other suitable materials. Other suitable materials are also within the contemplation of this disclosure.

In some embodiments, the gate electrode layer may comprise a polysilicon layer. In some embodiments, the gate electrode layer may be formed of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The work function layer is made of a metal material, and the metal material may comprise an N-work function metal or a P-work function metal. The N-work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. The metal of the P-work function comprises titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination thereof. Other suitable materials are also within the contemplation of this disclosure. The gate electrode layer may be formed by Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced CVD (PECVD).

In some embodiments, the pattern 120 may comprise the same material as a conductive via, which may be disposed on a conductive line, such as a first metal layer (M1 layer). In this embodiment, the pattern 120 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may comprise a metal nitride or other suitable material. The conductive layer may comprise a metal, such as W, ta, ti, ni, co, hf, ru, zr, zn, fe, sn, al, cu, ag, mo, cr, an alloy, or other suitable material. In this embodiment, the pattern 120 may be formed by a suitable deposition process, such as sputtering and Physical Vapor Deposition (PVD).

Intermediate structure 140 may include one or more intermediate layers of a fabrication technique that is an insulating material, such as silicon oxide or silicon nitride. In some embodiments, the intermediate structure 140 may include a conductive layer, such as a metal layer or an alloy layer. In some embodiments, one or more of the intermediate layers may be formed by a suitable film forming method, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). After the intermediate layer is formed, a thermal operation, such as rapid thermal annealing, may be performed. In other embodiments, a planarization operation, such as a Chemical Mechanical Polishing (CMP) operation, is performed. In other embodiments, a removal operation, such as an etching process, may be performed. The etching process may include, for example, a dry etching process or a wet etching process. It will be appreciated that additional operations may be provided before, during, and after the above-described processes, and that some of the operations described above may be replaced or eliminated for other embodiments of the present method. The order of operations/processes may be interchanged.

Fig. 4B is a sectional view taken along a cutting line B-B' of fig. 3.

As shown in fig. 3 and 4B, the pattern 130 is disposed on the intermediate structure 140. In some embodiments, pattern 130 may be a plurality of openings defined by mask 150. Mask 150 may be formed over intermediate structure 140 and removed in a subsequent process. Mask 150 may comprise a positive or a negative photoresist (e.g., a polymer), or a hard mask (e.g., silicon nitride or silicon oxynitride). The underlying layers, including mask 150 and pattern 130, may be patterned using a suitable photolithography process, such as forming a photoresist layer over intermediate structure 140, exposing the photoresist layer to a pattern through a mask, baking and developing the photoresist to form mask 150 and pattern 130. Mask 150 may then be used to define a pattern into intermediate structure 140 such that portions of intermediate structure 140 exposed to pattern 130 may be removed.

Since a plurality of semiconductor processes are performed after forming the pattern 120, the profile of the pattern 120 may be deformed and have an asymmetric profile. The deformed pattern 120 may result in a stack-up error estimate with a relatively large deviation.

Fig. 5 is a top view of overlay mark 210 illustrating some embodiments of the present disclosure.

Overlay mark 210 may include various features on substrate 100, such as pattern 220 and pattern 230. Pattern 220 may be a front layer pattern. Pattern 230 may be a pattern of a current layer. The front layer (or lower layer) may be located at a different horizontal level than the current layer (or upper layer). Each pattern 220 (or pattern 230) may be located in one of four orthogonal destination areas, two for measuring overlay error in the X-direction and two for measuring overlay error in the Y-direction.

In some embodiments, the pattern 220 may comprise the same material as an isolation feature and may be located at the same elevation as the isolation feature. In some embodiments, the pattern 220 may include a gate structure of the same material and may be located at the same elevation as the gate structure. In some embodiments, pattern 220 may comprise the same material as a conductive via and may be located at the same elevation as the conductive via.

In some embodiments, each pattern 220 may have a plurality of

sub-patterns

222, 224, and 226. In some embodiments, each of the

sub-patterns

222, 224, and 226 may have a different profile in a plan view. In some embodiments, each of the

secondary patterns

222, 224, and 226 may have a different size (e.g., surface area in plan view).

Each of the sub-patterns 222 may extend in a first direction, such as the Y direction. The plurality of sub-patterns 222 may be arranged along a second direction, such as the X-direction. In some embodiments, each secondary pattern 222 may have, for example, a rectangular outline.

The plurality of sub patterns 224 may be arranged in the second direction. Each of the sub patterns 224 may extend in a third direction inclined with respect to the X-direction and the Y-direction. For example, the secondary pattern 224 may have a first edge and a second edge that is inclined with respect to the first edge. The first edge may extend in a second direction and the second edge may extend in a third direction. In some embodiments, the secondary pattern 224 may be tilted with respect to the secondary pattern 222. In some embodiments, the size of the secondary pattern 224 may be greater than (or exceed) the size of the secondary pattern 222. In some embodiments, the pitch of the plurality of sub patterns 224 may be greater than the pitch of the plurality of sub patterns 222 in the second direction. In some embodiments, the number of secondary patterns 224 may be different from the number of secondary patterns 222. In some embodiments, the number of secondary patterns 224 may be less than the number of secondary patterns 222. In some embodiments, each secondary pattern 224 may have, for example, a parallelogram profile.

The plurality of sub patterns 226 may be arranged in the second direction. Each sub-pattern 226 may have a plurality of segments 226d arranged in the first direction. In some embodiments, the size of each segment 226d may be smaller than the size of each secondary pattern 222. In some embodiments, the pitch of the plurality of sub patterns 226 may be the same as the pitch of the plurality of sub patterns 222 in the second direction. In some embodiments, the segments of the secondary pattern 226 may have, for example, a rectangular outline. Although fig. 5 illustrates that the sub pattern 224 is disposed between the

sub patterns

222 and 226, the relative positions between the

sub patterns

222, 224, and 226 may be modified. For example, in other embodiments, the secondary pattern 222 may be disposed between the

secondary patterns

224 and 226.

The pattern 230 may have a plurality of sub-patterns 232. Each of the sub patterns 232 may extend in the first direction. The plurality of sub patterns 232 may be arranged in the second direction. In some embodiments, the length of the secondary pattern 232 may be greater than the length of the secondary pattern 222 along the first direction. In some embodiments, the pitch of the plurality of sub patterns 232 may be the same as the pitch of the plurality of sub patterns 222 in the second direction. In some embodiments, the pitch of the plurality of sub patterns 232 may be smaller than the pitch of the plurality of sub patterns 224 in the second direction. In some embodiments, each of the sub-patterns 232 may have, for example, a rectangular outline. In some embodiments, pattern 220 may be comprised of a sub-pattern having two or more different contours, while pattern 230 may be comprised of a sub-pattern having a single contour.

Although not shown in fig. 5, it should be noted that an intermediate structure may be provided to overlap the pattern 220, and the pattern 230 is provided on the intermediate structure.

When a overlay error is measured using overlay marks (e.g., overlay mark 210), the deviation in the X-direction is measured along a line in the X-direction of the overlay mark 210. The Y-direction deviation is further measured along a line in the Y-direction of the overlay mark 210. A single overlay mark, including

patterns

220 and 230, may be used to measure the deviation in an X-direction and a Y-direction between two layers on a substrate. Whether the layers are precisely aligned with the front layer may be determined based on the deviations in the X and Y directions. The overlay error may include a deviation in the X direction (Δx), a deviation in the Y direction (Δy), or a combination of both.

More specifically, images of

patterns

220 and 230 obtained from the overlay measurement apparatus may be used to calculate overlay errors. As described above, after the pattern 220 is formed, a plurality of semiconductor manufacturing processes are performed; the profile of the pattern 220 may be deformed and have an asymmetric profile. In order to obtain a more realistic overlay error, further corrections may be made to the overlay error obtained from the overlay measurement apparatus. An overlay correction system may receive optical image information from the pattern of the previous layer and the pattern of the current layer and then generate a plurality of correction data corresponding to each respective correction parameter. Thus, the overlay correction system may generate a corrected overlay error. A controller (e.g., a computer) will then send a signal indicating how to adjust the exposure apparatus based on the corrected overlay error. Accordingly, the exposure apparatus used to define the pattern 230 will be adjusted according to the corrected overlay error. In some embodiments, the correction data may be configured to generate an offset value in the X direction, an offset value in the Y direction, or a combination of both, for compensating for overlay errors.

Since one or more semiconductor processes are to be performed on the wafer after the formation of the front layer, the profile of the overlay mark in the front layer may be deformed and have an asymmetric profile due to different processes, such as a deposition process, an etching process, a chemical mechanical polishing process, or other processes. Therefore, the overlay error of these deformed patterns according to the front layer may deviate from the actual situation. It has been found that each cell of correction data may have a different degree of error, depending on the pattern having a different profile. That is, a set of correction data may have a small error (or deviation from the actual situation) according to pattern a, and a large error according to pattern B, whose profile is different from that of pattern a. Another set of correction data may have the opposite result: there is a larger error according to pattern a and a smaller error according to pattern B.

For example, the overlay correction system may include multiple sets of correction parameters, such as field-to-field expansion and field-to-field rotation. If an etching process is performed after the formation of the front layer, the correction data generated by the sub-pattern 224 (generated by the correction parameters related to the field spread) may have less error with respect to the actual situation. If a chemical mechanical polishing is performed after the formation of the front layer, the correction data generated by the sub-pattern 226 (generated by the correction parameters related to the inter-field rotation) may have less error than the actual case. The correction data generated by the sub-pattern 222 (which is not generated by the correction parameters of the inter-field spread and the inter-field rotation) may have a small error with respect to the actual situation. By selecting correction data having a small deviation from the actual situation, a corrected overlay error having a small deviation can be estimated.

As described above, correction data from different patterns (or sub-patterns) may have varying degrees of error. In embodiments of the present disclosure, the front layer may include patterns having different profiles, each of which may be used to generate a series of respective correction data. These correction data from the different sub-patterns may be selected to obtain a corrected overlay error with a small deviation from the actual situation. The exposure apparatus will be adjusted in accordance with the corrected overlay error, and in subsequent semiconductor processes, the alignment accuracy between the preceding layer and the succeeding layer will be improved.

Fig. 6 is a top view of overlay mark 210' illustrating some embodiments of the present disclosure.

The overlay mark 210 'shown in fig. 6 may be similar to the overlay mark 210 shown in fig. 5, except for the composition of the pattern 220'. In some embodiments, the CMP process may be omitted after forming the front layer, and the pattern 220' may be composed of the

sub patterns

222 and 224. In this embodiment, correction parameters not belonging to the inter-field extension may be selected from the secondary patterns 222 to generate correction data.

As described above, correction data from different patterns (or sub-patterns) may have varying degrees of error. In this embodiment, the front layer may include patterns having different profiles that may be used to create corrected overlay errors that deviate less from the actual situation. The exposure apparatus will be adjusted based on this corrected overlay error, and in the next semiconductor process, the alignment accuracy between the front layer and the intermediate layer will be improved.

Fig. 7 is a top view of overlay mark 210 "illustrating some embodiments of the present disclosure.

The overlay mark 210 "shown in fig. 7 may be similar to the overlay mark 210 shown in fig. 5, except for the composition of the pattern 220". In some embodiments, the etching process may be omitted after forming the front layer, and the pattern 220″ may be composed of the

sub patterns

222 and 226. In this embodiment, correction parameters that do not pertain to inter-field rotation may be selected from the secondary pattern 222 to generate correction data.

Fig. 8 is a block diagram illustrating a semiconductor fabrication system 300 in accordance with some embodiments of the present disclosure.

The semiconductor manufacturing system 300 may include a plurality of manufacturing apparatuses 310, 320-1, 320-N, an exposure apparatus 330, and a overlay measurement apparatus 340. Manufacturing apparatus 310, 320-1, & 320-N, exposure apparatus 330, and overlay measurement apparatus 340 may be coupled with controller 360 and Overlay (OVL) correction system 370 via network 350.

The manufacturing apparatus 310 may be configured to form a pattern in a front layer, such as the pattern 220 shown in fig. 5. In some embodiments, the fabrication apparatus 310 may be configured to form an isolation structure, a gate structure, a conductive via, or other layer. Manufacturing apparatus 320-1, and 320-N may be configured to form an intermediate structure, such as intermediate structure 140 shown in fig. 4A. Each of the fabrication apparatuses 320-1, and 320-N may be configured to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

The exposure apparatus 330 may be configured to form a pattern in the layer, such as the pattern 230 shown in fig. 5.

The overlay measurement apparatus 340 may be configured to obtain optical images of the patterns of the previous and present layers and to generate an overlay error based on the optical images of the patterns of the previous and present layers.

The network 350 may be the Internet or an internal network employing a network communication protocol such as the Transmission Control Protocol (TCP). Each of the manufacturing tools 310, 320-1-320-N, exposure tool 330, and overlay measurement tool 340 may download or upload work-in-process (WIP) information regarding the wafer or manufacturing tool from the controller 360 or overlay correction system 370 via the network 350.

The controller 360 may include a processor, such as a Central Processing Unit (CPU), to generate corrected overlay errors based on the overlay measurement apparatus 340 and the correction data generated from the overlay correction system 370.

Overlay correction system 370 may include correction parameters related to information of the optical image and thus may generate correction data from the corresponding correction parameters. Overlay correction system 370 may comprise, for example, a computer or a server. In some embodiments, the correction data may be generated or calculated by program code or programming language. In some embodiments, the deviation in the X direction (Δx), the deviation in the Y direction (Δy), or a combination of both may be generated from a formula that includes the correction parameters. Although FIG. 8 illustrates overlay correction system 370 as being in signal communication with overlay measurement apparatus 340 via network 350, the disclosure is not intended to be limiting. In other embodiments, overlay correction system 370 may be a program built into overlay measurement apparatus 340.

Although fig. 8 does not show any other manufacturing equipment prior to manufacturing equipment 310, the exemplary embodiment is not intended to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged before the manufacturing equipment 310 and may be used to perform various processes according to design requirements.

In the illustrative embodiment, wafer 301 is transferred to manufacturing apparatus 310 to begin a series of different processes. Wafer 301 may be formed with at least one layer of material by various stages of processing. The exemplary embodiments are not intended to limit the processing of wafer 301. In other exemplary embodiments, the wafer 301 may include various layers, or any stages between the start and finish of the product, before the wafer 301 is transferred to the manufacturing apparatus 310. In an exemplary embodiment, the wafer 301 may be processed sequentially by the fabrication apparatus 310, 320-1 through 320-N, the exposure apparatus 330, and the overlay measurement apparatus 340.

FIG. 9 is a flow chart illustrating a method 400 of generating correction data by a overlay correction system in accordance with aspects of the present disclosure.

The method 400 begins at operation 410, where a stack correction system, such as the stack correction system 370, is provided. In some embodiments, overlay correction system 370 may include a plurality of correction parameters P1, P2, and PN, which may be used to generate a corresponding correction data or a corrected overlay error.

The method 400 continues with operation 420 in which information of the optical image is provided. For example, the optical image may be generated by patterns (or sub-patterns) A, B, C and D, and information of the optical image may be uploaded to the network. In some embodiments, the patterns or sub-patterns A, B, C and D may correspond to the sub-pattern 222, the sub-pattern 224, the sub-pattern 226, and the pattern 230, respectively.

The method 400 continues with operation 430 in which correction data is generated. In some embodiments, pattern (or sub-pattern) a may be used to generate correction data a1 from parameter P1, correction data a2 from parameter P2, and so on. Thus, correction data a1, a2, and aN are generated according to pattern or sub-pattern a and correction parameters P1-PN. Also, correction data B1, B2, and bN are generated according to the pattern (or sub-pattern B) and correction parameters P1-PN, correction data C1, C2, and cN are generated according to the pattern (or sub-pattern) C and correction parameters P1-PN, and correction data D1, D2, and dN are generated according to the pattern (or sub-pattern) D and correction parameters P1-PN.

The method 400 continues with operation 440 in which a corrected overlay error is generated. The corrected overlay error may be generated based on the corrected data for the corresponding parameters P1-PN. The corrected overlay error may be represented by a formula containing an offset value in the X-direction, an offset value in the Y-direction, or a combination of both and an overlay error generated from the overlay measurement apparatus.

In other embodiments, operation 430 may be omitted. In the present embodiment, correction of overlay errors, including deviations in the X direction (Δx), deviations in the Y direction (Δy), or a combination of both, may be generated by the correction parameters. Each X-direction deviation (Δx), Y-direction deviation (Δy), or a combination of both may be expressed by a formula including a correction parameter as a variable. These variables can be determined when information of the optical image is received, thus producing a deviation in the X-direction (Δx), a deviation in the Y-direction (Δy), or a combination of both.

Fig. 10, 11, and 12 are flowcharts illustrating a correction method 500 of overlay correction in accordance with aspects of the present disclosure.

Referring to fig. 10, the calibration method 500 begins with operation 510 in which a wafer is received. The wafer may include a semiconductor substrate, such as a silicon substrate. The wafer may include a plurality of dies separated by streets.

The calibration method 500 continues with operation 520 in which a first pattern (e.g., a front layer pattern) is formed by a first manufacturing apparatus. A number of processes may be performed on the substrate of the wafer prior to forming the first pattern in order to form a number of features underneath the first pattern. In some embodiments, the first pattern may include a dielectric material, a conductive material, or other suitable material. In some embodiments, the first pattern may be formed in an operation configured to form, for example, gate structures, isolation features, conductive vias, or other features. In some embodiments, the first pattern may correspond to pattern 220 shown in fig. 5.

Referring to fig. 11, operation 520 may include

operations

522, 524, and 526, in which a plurality of first, second, and third sub-patterns are formed. In some embodiments, the first, second, and third sub-patterns may be formed simultaneously. In some embodiments, each of the first, second, and third sub-patterns may correspond to sub-patterns 222, 224, and 226, respectively, shown in fig. 5.

Returning to fig. 10, the correction method 500 continues with operation 530 in which a plurality of processes are performed on the substrate of the wafer after the first pattern is formed. These processes may be used to form an intermediate layer covering the first pattern. The intermediate layer may be formed by a plurality of manufacturing apparatuses that may be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

The correction method 500 continues with operation 540 in which a second pattern (e.g., a current layer) is formed by the exposure apparatus. In some embodiments, the second pattern may be an opening pattern of a mask, such as photoresist. In some embodiments, the second pattern may correspond to pattern 230 shown in fig. 5.

The correction method 500 continues with operation 550 in which a overlay error associated with movement in the X-direction and the Y-direction is generated by the overlay measurement apparatus. In some embodiments, a plurality of optical images of the first pattern, including the first, second, third, and second patterns, are generated by a overlay measurement apparatus, and overlay errors may be generated from the optical images. In some embodiments, the overlay error may include a deviation in the X direction (Δx), a deviation in the Y direction (Δy), or a combination of both.

The correction method 500 continues with operation 560 in which a corrected overlay error is generated by correcting the overlay error obtained in operation 550. In some embodiments, an offset value in the X-direction, an offset value in the Y-direction, or a combination of both may be generated to compensate for the overlay error generated in operation 550. In some embodiments, the corrected overlay error may be determined or calculated based on the operations for forming the above-described intermediate layer located below the current layer, such as operation 530.

Referring to fig. 12, operation 560 may include

operations

562, 564, 566, and 568. Operation 562 may include classifying the correction parameters into first, second, and third groups. For example, the correction parameters may be divided into a first group related to the inter-field expansion, a second group related to the inter-field rotation, and a third group not belonging to the first and second groups.

Operation 564 may include

operations

5641, 5642, and 5643, wherein a first correction data, a second correction data, and a third correction data are generated from the first, second, and third sub-patterns. Each of the first, second or third sub-patterns may be used to generate first, second and third correction data. That is, correction data of nine units may be generated according to the first, second, and third sub-patterns. The first, second and third correction data may correspond to first, second and third sets of correction parameters, respectively.

Operation 566 may include selecting data for generating a corrected overlay error. In some embodiments, the first correction data is selected from the first sub-pattern, the second correction data is selected from the second sub-pattern, and the third correction data is selected from the third pattern, respectively.

For example, correction parameters P1, P2,..and P9, and parameters P1, P2 and P3 belong to a first group, parameters P4, P5 and P6 belong to a second group, and parameters P7, P8 and P9 belong to a third group. Correction data a1, a2, & a9 is generated by the first set of sub-patterns, correction data b1, b2, & b9 is generated by the second set of sub-patterns, correction data c1, c2, & c9 is generated by the third set of sub-patterns. In the present embodiment, the correction data a1, a2, a3, b4, b5, b6, c7, c8, and c9 are selected to generate an offset value in the X direction, an offset value in the Y direction, or a combination of both thereof. Accordingly, a corrected overlay error may be generated based on the offset and the overlay error generated in operation 550.

In other embodiments, the number of sets of correction parameters may be determined by the process performed on the wafer in operation 530. In some embodiments, an etching process or a chemical mechanical polishing process may be omitted, and the correction parameters may be divided into two groups accordingly. In this case, if there are correction parameters P1, P2,..and P9, the correction data a1-a6 may be selected from the first set of sub-patterns and the correction data b7-b9 may be selected from the second set of sub-patterns to produce a corrected overlay error. In other embodiments, the number of sets of correction parameters may be greater than 3 depending on how the process is classified, and thus the correction parameters are classified according to the classified process.

Operation 568 may include generating a corrected overlay error based on the overlay error and the selected correction data. Operation 568 may be performed by a controller, such as controller 360 shown in fig. 8.

Operations

562, 564, 566 and/or 568 may be performed by a overlay correction system, such as overlay correction system 370 shown in fig. 8.

In other embodiments,

operations

564, 566, and 566 may be omitted. In the present embodiment, correction of the overlay error, including the deviation in the X direction (Δx), the deviation in the Y direction (Δy), or a combination of both, may be generated by the correction parameter. Each X-direction deviation (Δx), Y-direction deviation (Δy), or a combination of both may be expressed by a formula including a correction parameter as a variable. For example, correction parameters P1, P2,..and P9, and parameters P1, P2 and P3 belong to a first group, parameters P4, P5 and P6 belong to a second group, and parameters P7, P8 and P9 belong to a third group. The variables comprising correction parameters P1-P3, P4-P6 and P7-P9 may be determined from the optical information of the first, second and third sets of sub-patterns, respectively. Thus, correction of the overlay error can be determined.

Referring to fig. 10, the correction method 500 continues with operation 570 in which the exposure apparatus is adjusted according to the corrected overlay error. In some embodiments, operation 570 may include adjusting a position of a mask of the exposure apparatus so that a next exposure process may be performed with less overlay error.

The correction method 500 includes classifying correction parameters into different groups. As described above, correction data from different patterns (or sub-patterns) may have varying degrees of error. In this embodiment, the front layer may include patterns having different profiles, which may be used to create a corrected overlay error with less deviation from the actual situation. The exposure apparatus will be adjusted based on this corrected overlay error, and in subsequent semiconductor processes, the alignment accuracy between the preceding layer and the succeeding layer will be improved.

The correction method 500 is merely an example and is not intended to limit the disclosure beyond the scope of what is explicitly recited in the claims. Additional operations may be provided before, during, or after each operation of method 500, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the methods. In some embodiments, the correction method 500 may also include operations not depicted in fig. 10-12. In some embodiments, correction method 500 may include one or more of the operations described in fig. 10-12.

The processes illustrated in fig. 10-12 may be implemented in the controller 360, or in a computing system that organizes the preparation wafers by controlling each part or portion of the manufacturing equipment in the facility. Fig. 13 is a block diagram illustrating the hardware of a semiconductor fabrication system 600 of various aspects of the present disclosure. The system 600 includes one or more hardware processors 601 and a non-transitory computer-readable storage medium 603 encoded with, i.e., storing, program code (i.e., a set of executable instructions). The computer readable storage medium 603 may also be encoded with instructions for interfacing with a manufacturing apparatus for producing semiconductor devices. The processor 601 is electrically coupled to a computer readable storage medium 603 via a bus 605. The processor 601 is also electrically coupled to an input and output (I/O) interface 607 via bus 605. Network interface 609 is also electrically coupled to processor 601 via bus 605. The network interface is connected to a network, so that the processor 601 and the computer readable storage medium 603 can be connected to external elements via the network 350. The processor 601 is configured to execute computer program code encoded in the computer readable storage medium 605 such that the system 600 is operable to perform some or all of the operations described in the methods of fig. 10-12.

In some demonstrative embodiments, processor 601 may be, but is not limited to, a Central Processing Unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and/or a suitable processing unit. Various circuits or units are within contemplation of the present disclosure.

In some exemplary embodiments, the computer readable storage medium 603 can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 603 may include a semiconductor or solid state memory, a magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a hard disk and/or an optical disk. In one or more exemplary embodiments using optical disks, the computer-readable storage medium 603 also includes a compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W), and/or Digital Video Disk (DVD).

In some exemplary embodiments, the storage medium 603 stores computer program code configured to cause the system 600 to perform the methods shown in fig. 8-12. In one or more exemplary embodiments, the storage medium 601 also stores information required to perform the methods shown in fig. 8-12, as well as information and/or a set of executable instructions generated during performance of the methods to perform the operations of the methods shown in fig. 8-12. In some exemplary embodiments, a user interface 610, such as a Graphical User Interface (GUI), may be provided for a user to operate on the system 600.

In some demonstrative embodiments, storage medium 603 stores instructions for interfacing with an external machine. The instructions enable the processor 601 to generate instructions readable by an external machine to effectively implement the methods shown in fig. 8-12 during the analysis process.

The system 600 includes an input and output (I/O) interface 607. The I/O interface 607 is connected to external circuitry. In some demonstrative embodiments, I/O interface 607 may include, but is not limited to, a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and/or cursor direction keys for communicating information and commands to processor 601.

In some illustrative embodiments, I/O interface 607 may comprise a display, such as a Cathode Ray Tube (CRT), liquid Crystal Display (LCD), speaker, etc. For example, a display displays information.

The system 600 may also include a network interface 609 coupled to the processor 601. Network interface 609 allows system 600 to communicate with network 350, wherein one or more other computer systems are connected to network 350. For example, system 600 may be connected to manufacturing equipment 310, 320-1, and 320-N, exposure equipment, overlay measurement equipment 340, and overlay correction system 370 through network interface 609 connected to network 350.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure of the present disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or future developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of the present disclosure.

Claims

1. A overlay error measurement marker comprising:

a first pattern disposed on a substrate at a first level, wherein the first pattern comprises:

a plurality of first sub-patterns extending along a first direction and arranged along a second direction different from the first direction; and

a plurality of second sub-patterns arranged along the second direction, wherein a profile of each of the plurality of first sub-patterns is different from a profile of each of the plurality of second sub-patterns; and

a second pattern disposed at a second level different from the first level.

2. The measurement mark of claim 1, wherein a pitch of the plurality of second sub-patterns is different from a pitch of the plurality of first sub-patterns.

3. The measurement tag of claim 1 wherein each of the plurality of second sub-patterns extends in a third direction different from the first direction and the second direction in a plan view.

4. The measurement tag of claim 3 wherein the third direction is oblique to the first direction.

5. The measurement tag of claim 4 wherein each of the plurality of second sub-patterns has a first edge and a second edge that is relatively oblique to the first edge.

6. The measurement tag of claim 1 wherein each of the plurality of second sub-patterns comprises a plurality of segments aligned along the first direction.

7. The measurement tag of claim 1 wherein each of the plurality of second sub-patterns has a different size than each of the plurality of first sub-patterns in a plan view.

8. The measurement indicia of claim 1, wherein the number of the plurality of second sub-patterns is different than the number of the plurality of first sub-patterns.

9. The measurement tag of claim 1 wherein the second pattern comprises a plurality of third sub-patterns extending in the first direction and aligned in the second direction.

10. The measurement tag of claim 9 wherein each of the plurality of third sub-patterns has a length in the first direction that is different from each of the plurality of first sub-patterns.

11. The measurement mark of claim 9, wherein the pitch of the plurality of second sub-patterns is different from the pitch of the plurality of third sub-patterns.

12. The measurement mark of claim 9, wherein the pitch of the plurality of first sub-patterns is the same as the pitch of the plurality of third sub-patterns.