TW202341401A - Semiconductor device structure with overlay mark - Google Patents

Abstract

A semiconductor device structure with overlay marks is provided. The semiconductor device structure includes a substrate, a first light-emitting feature, a first pattern and a second pattern. The first light-emitting feature is disposed on the substrate. The first pattern is disposed on the first light-emitting feature. The second pattern is disposed on the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance to the light of the first wavelength. The second pattern has a second transmittance to the light of the first wavelength. The first transmittance is different from the second transmittance.

Description

Semiconductor element structure with overlapping marks

This application claims priority to U.S. Patent Application Nos. 17/716,112 and 17/716,374 (that is, the priority date is "April 8, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device structure. In particular, it relates to a semiconductor device structure having a stack of pairs of mark structures.

With the development of the semiconductor industry, it has become increasingly important to reduce the overlay errors of multiple photoresist patterns and their multiple underlying patterns in the lithography process. Due to various factors such as unclear optical images between a current layer and a preset layer of the overlay mark structure, it becomes more difficult to correctly measure the overlay error. Therefore, a method to more accurately measure the overlay was developed. One of the new semiconductor device structures and methods for error.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first light emitting feature, a first pattern and a second pattern. The first light emitting feature is disposed on the substrate. The first pattern is disposed on the first light emitting feature. The second pattern is disposed on the first pattern. The first light emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance for the light of the first wavelength. The second pattern has a second transmittance for the light of the first wavelength. The first transmittance is different from the second transmittance.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first light-emitting feature and a stack of mark structures. The first luminescent feature is disposed on the substrate. The first luminescent feature includes a plurality of metal ions for emitting a fluorescent light having a first wavelength. The overlapping mark structure is disposed on the first light emitting feature. The overlapping mark structure is configured to absorb or reflect the fluorescent light emitted from the first luminescent feature.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The preparation method includes providing a substrate; forming a first luminescent feature on the substrate; forming a first pattern on the first luminescent feature; and forming a second pattern on the first pattern; wherein the first luminescent feature The features are configured to emit a light of a first wavelength, the first pattern has a first transmittance for the light of the first wavelength, and the second pattern has a second transmittance for the light of the first wavelength. penetration rate, and the first penetration rate is different from the second penetration rate.

The embodiments of the present disclosure provide a semiconductor device structure with a light emitting characteristic. The luminescent features can be configured to emit fluorescent light. The fluorescence can improve the contrast between a current layer and a preset layer of a stacked marking structure in an optical image. Therefore, the overlay error can be calculated more accurately based on the above-mentioned optical image.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element number.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

Please refer to FIGS. 1 and 2 . FIG. 1 is a top view schematic diagram illustrating the wafer 10 in some embodiments of the present disclosure, and FIG. 2 is an enlarged schematic diagram illustrating a dotted line area shown in FIG. 1 in some embodiments of the present disclosure.

As shown in FIGS. 1 and 2 , the wafer 10 is cut along a plurality of cutting lines 30 into a plurality of die 40 . Each die 40 may include a semiconductor component, and the semiconductor wafer may include active components and/or passive components. Active devices may include a memory device (such as a dynamic random access memory (SRAM) device, a static random access memory (SRAM) device, etc.), a power management device (such as a power management integrated circuit (PMIC) component), a logic component (such as a system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microprocessor, etc.), a radio frequency (RF) component, A sensor component, a microelectromechanical system (MEMS) component, a signal processing component (such as a digital signal processing (DSP) component), a front-end component (such as an analog front-end (AFE) component), or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

As shown in FIG. 2 , the overlapping mark structures 21 and 22 may be disposed on the wafer 10 . In some embodiments, the overlapping mark structures 21 or 22 may be disposed on the cutting lines 30 . The overlapping mark structure 21 or 22 may be disposed at a corner of a side circle of each die 40 . In some embodiments, overlapping mark structures 21 or 22 may be disposed on the inside of die 40 . In some embodiments, the overlay mark structure 21 can be used to measure whether the current layer, such as an opening in a photoresist layer, is accurately aligned with a preset layer in the semiconductor manufacturing process. In some embodiments, the overlay mark structure 21 or 22 can be used to generate an overlay error between a current layer (or an upper layer) and a preset layer (or a lower layer).

FIG. 3 is a schematic top view illustrating a semiconductor device structure 50a according to some embodiments of the present disclosure.

As shown in FIG. 3 , a semiconductor device structure 50 a of, for example, a wafer may include an overlapping mark structure 110 a on a substrate 100 . In some embodiments, the overlapping mark structure 21 shown in FIG. 2 may include a pattern or a structure similar to or identical to the overlapping mark structure 110a shown in FIG. 3 . In some embodiments, the overlapping mark structure 22 shown in FIG. 2 may include a pattern or a structure similar to or identical to the overlapping mark structure 110a shown in FIG. 2 .

The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 100 may include an elemental semiconductor, including silicon or germanium in a single crystalline form, a polycrystalline form, or an amorphous form; a compound semiconductor material, including at least one of the following: silicon carbide, gallium arsenide, and gallium phosphide. , indium phosphide, indium arsenide and indium antimonide; an alloy semiconductor material, including at least one of the following: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the composition of Si to Ge changes from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature . In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multi-layer structure, or the substrate 100 may include a multi-layer compound semiconductor structure.

In some embodiments, overlay mark structure 110a may be used to align different layers on substrate 100 in accordance with different aspects of the present disclosure. The overlapping mark structure 110a may include patterns 111 and 112 on the substrate 100. The pattern 111 may be a pattern of a preset layer. Pattern 112 may be a pattern of a current layer. The preset layer (or a lower layer) may be disposed at a horizontal plane different from the current layer (or an upper layer). The preset layer (or a lower layer) can be set at a lower horizontal plane than the current layer (or an upper layer). In some embodiments, pattern 111 may at least partially overlap the pattern along the Z direction.

When measuring a stack error using a stack of mark structures such as double stack mark structure 110a, an X-direction deviation is measured along a straight line in the X direction of stack mark structure 110a. A Y-direction deviation is further measured along a straight line in the Y-direction of the overlapping mark structure 110a. A single overlay mark structure, including patterns 111 and 112, can be used to measure an X-direction and a Y-direction deviation between two layers on a substrate. Therefore, whether the current layer and the preset layer are accurately aligned can be determined based on the deviation in the X and Y directions. The overlay error may include X-direction deviation (ΔX), Y-direction deviation (ΔY), or a combination of both.

FIG. 4 is a schematic cross-sectional view illustrating a cross-section along line A-A’ of FIG. 3 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device structure 50a may further include a light emitting feature 120, an intermediate structure 130 and a mask 140.

As shown in FIG. 4 , the substrate 100 may have a surface 100s1 and a surface 100s2 , and the surface 100s2 is disposed opposite to the surface 100s1 . The surface 100s2 of the substrate 100 may be an active surface on which the input/output terminals are disposed. The surface 100s1 of the substrate 100 may be a rear surface.

In some embodiments, light emitting features 120 may be disposed on surface 100s2 of substrate 100. In some embodiments, the light emitting feature 120 may be used to emit a first waveband of light. In some embodiments, the luminescent feature 120 may be used to emit a phosphor having a first waveband. In some embodiments, light emitting feature 120 may include a dielectric layer and a plurality of light emitting materials therein. For example, after a light of a specific wavelength is incident on the luminescent feature 120, the luminescent materials may absorb the light and be excited. The excited luminescent materials can emit a light having the first wave band. It should be understood that the light (or fluorescence) emitted by the light emitting feature may be a light of a specific wavelength in other embodiments.

The wavelength of the light that induces a fluorescent light may depend on the luminescent materials of the luminescent feature 120 . In some embodiments, the first waveband (or wavelength) may range from about 100 nm to about 1000 nm, such as 100 nm, 200 nm, 300 nm, 400, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm. For example, the wavelength of light emitted from light emitting features 120 may include a band ranging between approximately 300 nm and approximately 500 nm. In another example, the wavelength of light emitted from light emitting feature 120 may be 617 nm.

The dielectric layer of light emitting features 120 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), or other suitable materials.

In some embodiments, the luminescent materials of luminescent features 120 may include metal ions of transition metals, such as europium (Eu), talcium (Tm), phosphorus (Pr), neodymium (Nd), samarium (Sm), phosphorus ( Tb), dysprosium (Dy), 鈥(Ho), erbium (Er), ytterbium (Yb), cerium (Ce), titanium (Pm), 铓(Gd), 镐(Lu), thorium (Th), 铩( Pa), uranium (U), nithenium (Np), plutonium (Pu), gallium (Am), gallium (Cm), gallium (Bk), gallium (Cf), gallium (Es), fermium (Fm), gallium ( Md), 鍩(No), 鍩(Lr), combinations thereof or other suitable metals.

In some embodiments, the luminescent materials of luminescent features 120 may include organic materials, such as a compound or polymer containing aromatic groups. For example, the luminescent materials of luminescent features 120 may include a functional group selected from the group consisting of: benzene, naphthalene, pyridine, pyrimidine, triazine, thiophene, isothiazole, triazole, pyridazine, pyrrole, pyrazole, Imidazole, triazole, thiadiazole, pyridine, furan, isozoline, oxazole, oxadiazole, quinoline, isoquinoline, quinoline, quinazoline, oxadiazole, thiadiazole, benzo Triazine, phthalazine, tetrazole, indole, benzofuran, benzothiophene, benzoxazole, benzothiazole, indazole, benzimidazole, benzotriazole, benzisothiazole, benzothiodi Azole, dibenzofuran, dibenzothiophene, dibenzoselenol, carbazole, or other suitable functional groups.

In some embodiments, the luminescent materials of luminescent features 120 may include semiconductor materials. In some embodiments, the luminescent materials of luminescent features 120 may include homojunctions, heterojunctions, single quantum wells (SQWs), multiple quantum wells (MQWs), or any other applicable structure. In some embodiments, the luminescent materials may include In _x Ga _(1-x) N, Al _x In _y Ga _(1-xy) N, or other suitable materials.

In some embodiments, pattern 111 may be disposed on light emitting features 120 . In some embodiments, pattern 111 may vertically overlap light emitting features 120. In some embodiments, pattern 111 may overlap light emitting features 120 along the Z direction. The pattern 111 can be disposed within or below an intermediate structure 130 . In some embodiments, pattern 111 may include a material that is the same as the material of an insulating structure. In some embodiments, pattern 111 may be disposed at the same height as the insulating structure. In some embodiments, for example, the insulating structure may include a shallow trench isolation (STI), a field oxide (FOX), a local oxidation of silicon (LOCOS) feature, and/or other suitable insulating elements. The insulating structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate (FSG), a low dielectric constant dielectric material, combinations thereof, and/or other suitable materials. .

In some embodiments, the pattern 111 may include a material that is the same as a gate structure. The gate structure may be sacrificial, such as a dummy gate structure. In some embodiments, pattern 111 may be disposed at the same height as the gate structure. In some embodiments, the pattern 111 may include a dielectric layer, the same material as a gate dielectric layer and a conductive layer, and the same material as a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. High-k dielectric materials may have a dielectric constant (k value) greater than 4. The high dielectric constant dielectric material may include HfO ₂ , ZrO ₂ , La ₂ O ₃ , Y ₂ O ₃ , Al ₂ O ₃ , TiO ₂ or other applicable materials. Other suitable materials are within the contemplated scope of this disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may include conductive materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the gate electrode layer may include a work function layer. The work function layer includes metal materials, and the metal materials may include N-type work function metal or P-type work function metal. N-type work function metals include W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Zr or combinations thereof. P-type work function metals include TiN, WN, TaN, Ru or combinations thereof. Other suitable materials are within the contemplated scope of this disclosure. The manufacturing technology of the gate electrode layer may include low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

In some embodiments, the pattern 111 may include a material that is the same as a conductive via, and the conductive via may be disposed on a conductive trace, such as the zeroth metal layer (M0), the first metal layer (M0), M1), the second metal layer (M2), and so on. In this embodiment, the pattern 111 may include a barrier layer and a conductive layer, and the conductive layer is surrounded by the barrier layer. The barrier layer may include metal nitride or other suitable materials. The conductive layer may include metals such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloys, or other suitable materials. In this embodiment, the fabrication technology of the pattern 111 may include a suitable deposition process, for example, sputtering and physical vapor deposition (PVD).

Intermediate structure 130 may include one or more intermediate layers including an isolation material, such as silicon oxide or silicon nitride. In some embodiments, intermediate structure 130 may include multiple conductive layers, such as multiple metal or alloy layers.

Pattern 112 is provided on intermediate structure 130 . The pattern 112 may be disposed on or above the surface 100s2 of the substrate 100. In some embodiments, pattern 112 may at least vertically overlap pattern 111 . In some embodiments, pattern 112 may overlap at least pattern 111 along the Z direction. In some embodiments, pattern 112 may at least vertically overlap light emitting features 120. In some embodiments, pattern 112 may overlap at least light emitting features 120 along the Z direction. In some embodiments, the pattern 112 may be a plurality of openings 140r defined by a mask 140.

Mask 140 may be formed on intermediate structure 130 and will be removed in subsequent processes. The mask 140 may include a positive or negative photoresist, such as a polymer, or a hard mask, such as silicon nitride or silicon oxynitride. The current layer including the mask 140 and the pattern 112 can be patterned using a suitable lithography process, for example, forming a photoresist layer on the intermediate structure 130 and passing the photoresist layer through a photomask. The photoresist is exposed to a pattern, baked, and developed to form mask 140 and pattern 112. Mask 140 can then be used to define a pattern into intermediate structures 130 so that the exposed portions of intermediate structures 130 from the photoresist layer can be removed.

In some embodiments, overlapping mark structure 110a may be configured to absorb and/or reflect a light (or fluorescent light) emitted from reflective feature 120. In some embodiments, pattern 111 may be configured to absorb and/or reflect a light (or fluorescent light) emitted from reflective feature 120 . Pattern 111 may have a first transmittance for a first band (or wavelength) of light (or fluorescence) emitted from reflective feature 120 . Pattern 112 may have a second transmittance for a first band (or wavelength) of light (or fluorescence) emitted from reflective feature 120 . In some embodiments, the first transmission rate is different from the second transmission rate. In some embodiments, the first penetration rate is less than the second penetration rate. In some embodiments, the first penetration rate may be less than 30%, such as 30%, 20%, 15%, 10%, 7%, 5%, 3%, 1%, or even less. A larger transmittance difference between patterns 111 and 112 may facilitate identification of patterns 111 and 112 in an optical image by an overlay measurement device. In this embodiment, the light (or fluorescence) emitted by the light-emitting features 120 can improve the contrast between the patterns 111 and 112 of an optical image. For example, the outlines of patterns 111 and 112 in an optical image can be clearly identified by a sensor of the overlay measurement device. Therefore, the overlay error can be calculated more accurately.

FIG. 4A is a cross-sectional schematic diagram illustrating the light emitting mechanism of the light emitting feature 120 .

In some embodiments, light emitting feature 120 may include a plurality of metal ions LE1 therein. In some embodiments, when the metal ions LE1 receive the light L1, the light emitting feature 120 may emit a light (or fluorescent light) F1. In some embodiments, the first transmittance of the pattern 111 to the light (or fluorescent light) F1 is different from the second transmittance of the pattern 112 to the light (or fluorescent light) F1.

FIG. 5 is a top view schematic diagram illustrating a semiconductor device structure 50b according to some embodiments of the present disclosure. The semiconductor device structure 50b shown in FIG. 5 may be similar to the semiconductor device structure 50a shown in FIG. 3 , except that the semiconductor device structure 50b may include a stacked mark structure 110b instead of the stacked mark structure 110a.

As shown in FIG. 5 , the overlapping mark structure 110b may include a plurality of patterns 111 and 112 . Each pattern 111 or 112 may be located in one of four orthogonal target areas, two of which are configured to measure the overlay error in the X direction, and two of which are configured to measure the overlay error in the Y direction.

FIG. 6A is an optical image diagram illustrating an optical image 200a of a semiconductor device structure according to some embodiments of the present disclosure.

In some embodiments, optical image 200a may include contours 211 and 230. The outline 211 may correspond to an image of the pattern 111 . The outline 230 may correspond to an image of the intermediate structure 130 . In some embodiments, the intermediate structure 130 may have a third transmittance for the first band (or wavelength) of a light (or phosphor) emitted by the light emitting feature 120 . In some embodiments, the first penetration rate is different from the third penetration rate. In some embodiments, the first penetration rate is less than the third penetration rate. As shown in FIG. 6A , the brightness of the outline 230 may exceed the brightness of the outline 211 in the optical image 200a.

FIG. 6B is an optical image diagram illustrating an optical image 200b of a semiconductor device structure according to some embodiments of the present disclosure.

In some embodiments, optical image 200b may include contours 211' and 230'. The outline 211′ may correspond to an image of the pattern 111. The outline 230' may correspond to an image of the intermediate structure 130. In some embodiments, the first penetration rate exceeds the third penetration rate. As shown in FIG. 6B, the brightness of the outline 211' may exceed the brightness of the outline 230' in the optical image 200b.

In some embodiments, the contrast between the pattern 111 and the intermediate structure 130 in an optical image (eg, 200a or 200b) can be improved to help identify the outline of the pattern 111. Therefore, the overlay error can be calculated more accurately.

Similarly, the contrast between pattern 112 and intermediate structure 130 may be controlled or improved. In some embodiments, the second penetration rate may be less than the third penetration rate. In some embodiments, the second penetration rate may exceed the third penetration rate. In some embodiments, the third transmittance may be in a range between the first transmittance and the second transmittance. By adjusting the relationship between the first transmittance, the second transmittance, and the third transmittance, the overlay error can be calculated more accurately.

FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device structure 50c of different aspects of the present disclosure. The semiconductor device structure 50c shown in FIG. 7 may be similar to the semiconductor device structure 50a shown in FIG. 4 , except that the semiconductor device structure 50c may further include a light emitting feature 150 .

In some embodiments, light emitting features 150 may be disposed under pattern 112 . In some embodiments, light emitting features 150 may be disposed between patterns 111 and 112 . In some embodiments, light emitting features 150 may be disposed between intermediate structure 130 and pattern 112 . In some embodiments, light emitting features 150 may be embedded in intermediate structure 130 . In some embodiments, pattern 112 may vertically overlap light emitting features 150. In some embodiments, pattern 112 may overlap light emitting features 150 along the Z direction. In some embodiments, the light emitting feature 150 can be used to emit a light having a second wave band (or wavelength) that is different from the first wave band (or wavelength). In some embodiments, luminescent feature 150 may be used to emit a phosphor having the second band (or wavelength). In some embodiments, light emitting feature 150 may include a dielectric layer with a plurality of light emitting materials doped therein. For example, after a light of a specific wavelength is incident into the luminescent feature 150, the luminescent materials may absorb the light and be excited. The excited luminescent materials can emit light with the second wave band (or wavelength).

The wavelength of the light that induces a fluorescent light may depend on the luminescent materials of the luminescent feature 150 . In some embodiments, the second waveband (or wavelength) may range from about 100 nm to about 1000 nm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm.

The dielectric layer of light emitting features 150 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

In some embodiments, the luminescent materials of luminescent features 150 may include metal ions of transition metals, such as Eu, Tm, Pr, Nd, Sm, Tb, Dy, Ho, Er, Yb, Ce, Pm, Gd, Lu , Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, No, Lr or other suitable metals. In some embodiments, the luminescent materials of luminescent features 150 may include organic materials, such as a compound or polymer that includes aromatic groups. For example, the luminescent materials of luminescent features 150 may include homojunctions, heterojunctions, single quantum wells (SQWs), multiple quantum wells (MQWs), or any other applicable structure.

In some embodiments, overlapping mark structure 110a may be configured to absorb and/or reflect a light (or fluorescent light) emitted from light emitting feature 150. In some embodiments, pattern 112 may be configured to absorb and/or reflect a light (or fluorescent light) emitted from light emitting feature 150 . The pattern 112 may have a fourth transmittance for the second band (or wavelength) of a light (or fluorescent light) emitted from the light emitting feature 150 . In some embodiments, the fourth penetration rate is different from the first penetration rate. In some embodiments, the fourth penetration rate is different from the second penetration rate. In some embodiments, the fourth penetration rate is less than the second penetration rate. In some embodiments, the fourth penetration rate is different from the third penetration rate. In some embodiments, the fourth penetration rate is less than the third penetration rate. In some embodiments, the fourth penetration rate may be less than 30%, such as 30%, 20%, 15%, 10%, 7%, 5%, 3%, 1%, or even less. The light (or fluorescence) emitted by the light emitting features 150 may improve the contrast of the patterns 111 , 112 and/or the intermediate structure 130 . Therefore, the overlay error can be calculated more accurately.

FIG. 7A is a cross-sectional schematic diagram illustrating the light-emitting mechanism of the light-emitting feature 150.

In some embodiments, light emitting feature 150 may include a plurality of metal ions LE2 therein. In some embodiments, when the metal ions LE2 receive the light L2, the light emitting feature 150 may emit a light (or fluorescent light) F2. In some embodiments, the third transmittance of the pattern 112 to the light (or fluorescent light) F2 is different from the second transmittance of the pattern 112 to the light (or fluorescent light) F1 (as shown in FIG. 4A ). of. In some embodiments, the wavelength of light L1 may be different from the wavelength of light L2. In some embodiments, the wavelength of light (or fluorescent light) F1 may be different from the wavelength of light (or fluorescent light) F2. In some embodiments, the metal ions LE2 may be different from the metal ions LE2.

FIG. 8 is an optical image diagram illustrating an optical image 200c of a semiconductor device structure according to some embodiments of the present disclosure.

In this embodiment, the overlay error between patterns 111 and 112 is not equal to zero. That is, the patterns 111 and 112 have an offset along the X direction, the Y direction, or a combination thereof. In some embodiments, optical image 200c may include contours 221, 222, 213, and 224. The outline 221 may correspond to an image of an area without the patterns 111 and 112 disposed on the intermediate structure 130 . The outline 222 may correspond to an image of an area where the pattern 112 does not vertically overlap the pattern 111 . The outline 223 may correspond to an image of an area where the pattern 111 vertically overlaps the pattern 112 . The outline 224 may correspond to an image of a region where the pattern 111 does not vertically overlap the pattern 112 .

In some embodiments, outline 221 may exhibit a color that includes the first band (or wavelength) and the second band (or wavelength). In some embodiments, outline 222 may exhibit a color that includes the first band (or wavelength). In some embodiments, outline 223 may appear a color with lower brightness than outline 221, 222, or 224. In some embodiments, outline 224 may exhibit a color that includes the second band (or wavelength).

Since the contrast between pattern 111, pattern 112, and an overlay area between patterns 111 and 112 in the optical image 200c can be improved, the overlay error can be calculated more accurately.

FIG. 9 is an optical image diagram illustrating an optical image 200d of a semiconductor device structure according to some embodiments of the present disclosure.

In this embodiment, the overlay error between patterns 111 and 112 is equal to zero. That is, the pattern 111 is aligned with the pattern 112 along the X direction and the Y direction. In some embodiments, the optical image 200d may include contours 221 and 223.

By calculating the area of contour 223, the extent of the overlay error can be determined. Since the contour 223 can be identified directly in this embodiment, the overlay error can be calculated more accurately.

FIG. 10 is a block diagram illustrating a semiconductor manufacturing system 300 according to some embodiments of the present disclosure.

Semiconductor manufacturing system 300 may include manufacturing equipment 320-1, . . . , 320-N, 330, 340-1, . . . , 340-N, exposure equipment 350, and overlay measurement equipment 360. An overlay correction system 370 may include or be built into the overlay measurement device 360 . The manufacturing equipment 320-1,..., 320-N, 330, 340-1,..., 340-N, the exposure equipment 350, and the overlay measurement equipment 360 may be signally coupled to a controller 390 via a network 380. . In some embodiments, the overlay correction system 370 may be a stand-alone system that provides signals to the overlay measurement device 360 via the network 380 .

Fabrication equipment 320-1, ..., 320-N may be used to form elements or features between the preset layer (eg, pattern 111) and the substrate, such as light emitting features 120 as shown in FIG. 4. Each piece of manufacturing equipment 320-1, ..., 320-N may be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

Manufacturing equipment 330 may be used to form patterns in a preset layer, such as pattern 111 as shown in FIG. 4 . In some embodiments, fabrication equipment 330 may be used to form an insulating structure, a gate structure, a conductive via, or other layers. The pattern of the preset layer may include dielectric material, semiconductor material or conductive material.

Fabrication equipment 340-1, ..., 340-N may be used to form an intermediate structure, such as intermediate structure 130 as shown in Figure 4. Each piece of manufacturing equipment 340-1, ..., 340-N may be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

Exposure equipment 350 may be used to form a pattern of a current layer, such as pattern 112 as shown in FIG. 4 .

In some embodiments, the overlay measurement device 360 can be used to obtain optical images of each pattern of the preset layer and the current layer, and based on the aforementioned optical images (such as patterns) of each pattern of the preset layer and the current layer 200a, 200b, 200c or 200d).

The overlay correction system 370 may include a plurality of correction parameters for generating corrected first and second overlay errors. For example, the overlay correction system 370 may include a calculator or a server. In some embodiments, corrected alignment errors may be generated or calculated by multiple codes or programming languages. For example, the corrected overlay error may be determined by the overlay error obtained from the overlay measurement device 360 and the correction parameters of the overlay correction system 370 . In some embodiments, an X-direction deviation (ΔX), a Y-direction deviation (ΔY), or a combination of the two can be generated from the correction parameters. Each of the X-direction deviation (ΔX), the Y-direction deviation (ΔY), or a combination of the two may be represented by an equation including the correction parameters as a plurality of variables. In some embodiments, the overlay correction system 370 can receive information from the pattern of the preset layer and the pattern of the current layer, and then generate an X-direction deviation (ΔX), a Y-direction deviation (ΔY), or a combination of the two, to compensate for the overlay error obtained from the overlay measurement device 360.

Network 380 may be the Internet or an intranet that implements a network protocol such as Transmission Control Protocol (TCP). Via network 380, each piece of fabrication equipment 320-1, ..., 320-N, 330, 340-1, ..., 340-N, exposure equipment 3502, and overlay measurement equipment 360 can download information about the wafer from controller 390 Or the work-in-process (WIP) information of the manufacturing equipment or the work-in-process (WIP) information about the wafer or the manufacturing equipment is uploaded to the controller 390 .

Controller 390 may include a processor, such as a central processing unit (CPU). In some embodiments, the controller 390 may be configured to generate an instruction of whether to adjust the exposure device 350 based on the first overlay error and the second overlay error.

Although FIG. 10 does not show any other manufacturing equipment before manufacturing equipment 320, the illustrated embodiment is not meant to be limiting. In other example embodiments, various manufacturing equipment may be arranged before manufacturing equipment 320 and may be used to perform various processes according to design requirements.

In some illustrative embodiments, a wafer 310 may be transferred to fabrication equipment 320 to begin a series of different processes. Wafer 310 may be processed through different stages of forming at least one layer of material. The illustrated embodiments are not meant to limit the performance of wafer 310 . In some other example embodiments, the wafer 310 may include different layers before the wafer 310 is transferred to the fabrication equipment 320, or at any stage between the beginning and completion of a product. In some exemplary embodiments, wafer 310 may be sequentially processed by fabrication equipment 320-1, ..., 320-N, 330, 340-1, ..., 340-N, exposure equipment 350, and overlay measurement equipment 360 handle.

FIG. 11 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to different aspects of the present disclosure.

The preparation method 400 begins with step 410 of providing a substrate. The base has a first surface and a second surface, and the second surface is disposed relative to the first surface. The first surface may also be represented as a rear surface. The second surface may also be represented as an active surface on which active features are formed, such as gate structures and traces connected to input/output terminals.

The preparation method 400 continues with step 410, which is forming a first light emitting feature on the substrate. In some embodiments, the first light-emitting feature may include a plurality of light-emitting materials in a dielectric layer. In some embodiments, for example, the luminescent materials may include a plurality of metal ions, such as Eu, Tm, Pr, Nd, Sm, Tb, Dy, Ho, Er, Yb, Ce, Pm, Gd, Lu, Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, No, Lr or other suitable metals. In some embodiments, the aforementioned metal ions can be formed in a liquid dielectric material. The liquid dielectric material containing the metal ions can be formed on the substrate by, for example, spin coating. An annealing process and/or a baking process may be performed to solidify the liquid dielectric material, thereby forming the first light emitting feature. In some other embodiments, the first light-emitting feature may include organic materials and/or semiconductor materials, and its fabrication technology may include multiple suitable processes. The first luminescent feature may be produced by devices 320-1, ..., 320-N as shown in Figure 10.

The preparation method 400 continues with step 430, which is forming a first pattern on the second surface of the substrate. The first pattern may include a material that is the same as the insulation structure, the gate structure, or the conductive via. Fabrication techniques for the first pattern may include processes for forming insulating features, gate structures, or conductive vias. The first pattern may be produced by apparatus 330 as shown in FIG. 10 .

The preparation method 400 continues with step 440, which is to form an intermediate structure covering the first pattern. The intermediate structure may include one or more intermediate layers including an isolation material such as silicon oxide or silicon nitride. The intermediate structure may include a plurality of conductive features formed in a plurality of dielectric layers. In some embodiments, the manufacturing technology of the intermediate structure may include CVD, PVD, ALD, dry etching, wet etching, CMP or photolithography processes. The luminescent features may be produced by devices 340-1, ..., 340-N as shown in Figure 10.

The preparation method 400 continues with step 450, which is forming a second light emitting feature on the substrate. In some embodiments, the second light emitting feature may include a plurality of light emitting materials in the dielectric layer. In some embodiments, the luminescent materials may include multiple metal ions, such as Eu, Tm, Pr, Nd, Sm, Tb, Dy, Ho, Er, Yb, Ce, Pm, Gd, Lu, Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, No, Lr or other suitable metals. In some embodiments, the aforementioned metal ions can be formed in a liquid dielectric material. The liquid dielectric material including the metal ions can be formed on the intermediate structure by, for example, spin coating. An annealing process and/or a baking process may be performed to solidify the liquid dielectric material, thereby forming the second light emitting feature. In other embodiments, the first light-emitting feature may include organic materials and/or semiconductor materials, and its fabrication technology may include multiple suitable processes. In some embodiments, step 450 is optional. In some embodiments, step 450 may be omitted.

The manufacturing method 400 continues with step 460, which is forming a second pattern on the intermediate structure. In some embodiments, the second pattern may be a plurality of openings in a mask, such as a photoresist layer. In some embodiments, for example, step 460 may include forming a photoresist layer on the intermediate structure or on the second light-emitting feature, exposing the photoresist layer into a pattern through a photomask, and baking the photoresist layer. The photoresist is baked and developed to form the second pattern. The second pattern may be produced by at least exposure apparatus 350 as shown in FIG. 10 .

The method 400 continues with step 470, which generates a stack alignment error. The overlay error may be generated based on the first pattern and the second pattern. In some embodiments, an optical image may be obtained by overlaying the measurement devices. In some embodiments, the overlay measurement device may include an optical source, an optical sensor, and an optical filter. In some embodiments, an optical source may be used to emit a light to excite the luminescent materials of the first luminescent characteristic to induce fluorescence. In some embodiments, an optical sensor may be used to receive the fluorescent light emitted by the first luminescent feature and/or the second luminescent feature, thereby generating an optical image. In some embodiments, a filter may be used to select a specific wavelength of light received by the optical sensor, thereby improving the contrast of the optical image. The overlay error can be determined from the optical image. In this embodiment, the contrast of each pattern of the first pattern, the second pattern and the intermediate structure may be improved by emitting fluorescent light from the first luminescent feature and/or the second luminescent feature. Therefore, the overlay error can be calculated more accurately. The overlay error can be generated by the exposure device 350 as shown in FIG. 10 .

The processes shown in Figure 11 may be implemented in a controller 390 or a computing system that organizes the fabrication of a wafer by controlling all or a portion of the fabrication equipment in the facility. FIG. 12 is a schematic block diagram illustrating the hardware of a semiconductor manufacturing system 500 in different aspects of the present disclosure. System 500 includes one or more hardware processors 501 and a non-transitory computer-readable storage medium 503 encoded with stored program code (i.e., a set of executable instructions) . Computer readable storage medium 503 may also be encoded with instructions for interfacing with the manufacturing equipment used to produce the semiconductor components. The processor 501 is electrically coupled to the computer-readable storage medium 503 via a bus 505 . The processor 501 is also electrically coupled to an input/output interface 507 via the bus 505 . A network interface 509 is also electrically connected to the processor 501 via 505 . The network interface is connected to the Internet so that the processor 501 and the computer-readable storage medium 503 can be connected to multiple external components via the network 503 . The processor 501 is configured to execute computer program code encoded in the computer-readable storage medium 503 so that the system 500 can be used to perform some or all of the steps described in the preparation method as shown in FIG. 11 .

In some exemplary embodiments, the processor 501 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit circuit, ASIC) and/or a suitable processing unit, but is not limited to this. Various circuits or units are within the intended scope of this disclosure.

In some exemplary embodiments, the computer-readable storage medium 503 is an electronic, magnetic, optical, electromagnetic, infrared and/or a semiconductor system (or equipment or device), but is not limited thereto. For example, the computer-readable storage medium 503 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), and a read-only memory. ROM, a rigid magnetic disk and/or an optical disk. In one or more exemplary embodiments using optical discs, the computer-readable storage medium 503 also includes a compact disc read-only memory (CD-ROM), a compact disc read/write (CD-R/W), and/or or a digital video disc (DVD).

In some exemplary embodiments, the storage medium 503 stores computer code configured to cause the system 500 to perform the preparation method shown in FIG. 11 . In one or more illustrative embodiments, the storage medium 503 also stores information required to perform the preparation method shown in FIG. 11 and during execution of these preparation methods and/or a set of executable instructions to perform the preparation shown in FIG. 11 Information generated during the steps of a method. In some exemplary embodiments, a user interface 510, such as a graphical user interface (GUI), may be provided for a user to operate on the system 500.

In some illustrated embodiments, storage medium 503 stores multiple instructions for interfacing with multiple external machines. These instructions enable the processor 501 to effectively implement the method shown in FIG. 11 during an analysis by using a plurality of readable instructions generated by the external machine.

System 500 includes input/output (I/O) interface 507 . Input/output interface 507 is coupled to external circuitry. In some exemplary embodiments, the input/output interface 507 may include a keyboard, a keypad, a mouse, a trackball, and a trackpad for transmitting information and commands to the processor 501 ), touch screen and/or cursor keys. , but not limited to this.

In some exemplary embodiments, input/output interface 507 may include a display, such as a cathode ray tube (CRT), liquid crystal display (LCD), a speaker, or the like. For example, the display displays information.

System 500 may also include a network interface 509 coupled to processor 501. Network interface 509 allows system 500 to communicate with network 380 to which one or more other computer systems are connected. For example, system 500 may connect manufacturing equipment 320-1, ..., 320-N, 330, 340-1, ..., 340-N, exposure equipment 350, and overlay measurement equipment 350 to Network 380.

An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first light emitting feature, a first pattern and a second pattern. The first light emitting feature is disposed on the substrate. The first pattern is disposed on the first light emitting feature. The second pattern is disposed on the first pattern. The first light emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance for the light of the first wavelength. The second pattern has a second transmittance for the light of the first wavelength. The first transmittance is different from the second transmittance.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first light-emitting feature and a stack of mark structures. The first luminescent feature is disposed on the substrate. The first luminescent feature includes a plurality of metal ions for emitting a fluorescent light having a first wavelength. The overlapping mark structure is disposed on the first light emitting feature. The overlapping mark structure is configured to absorb or reflect the fluorescent light emitted from the first luminescent feature.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The preparation method includes providing a substrate; forming a first luminescent feature on the substrate; forming a first pattern on the first luminescent feature; and forming a second pattern on the first pattern; wherein the first luminescent feature The features are configured to emit a light of a first wavelength, the first pattern has a first transmittance for the light of the first wavelength, and the second pattern has a second transmittance for the light of the first wavelength. penetration rate, and the first penetration rate is different from the second penetration rate.

The embodiments of the present disclosure provide a semiconductor device structure with a light emitting characteristic. The luminescent features can be configured to emit fluorescent light. The fluorescence can improve the contrast between a current layer and a preset layer of a stacked marking structure in an optical image. Therefore, the overlay error can be calculated more accurately based on the above-mentioned optical image.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

10:wafer 30: Cutting line 40:Grain 50a: Semiconductor component structure 50b: Semiconductor component structure 50c: Semiconductor component structure 100:Base 100s1: Surface 100s2: Surface 110a: Overlay mark structure 110b: Overlay mark structure 111: Pattern 112: Pattern 120: Luminous characteristics 130: Intermediate structure 140:Mask 140r:Open your mouth 150: Luminous features 200a: Optical imaging 200b: Optical imaging 200c: Optical imaging 200d: Optical imaging 211:Contour 211’:Contour 221:Contour 222:Contour 223:Contour 224:Contour 230:Contour 230’:Contour 300:Semiconductor Manufacturing Systems 310:wafer 320-1~320-N: Manufacturing equipment 330: Manufacturing equipment 340-1~340-N: Manufacturing equipment 350: Exposure equipment 360: Overlay measurement equipment 370: Overlay correction system 380:Internet 390:Controller 400:Preparation method 410: Steps 420: Steps 430: Steps 440: Steps 450: steps 460: steps 470: Steps 500: Semiconductor Manufacturing Systems 501: Hardware processor 503: Non-transitory computer-readable storage media 505:Bus 507:Input/output interface 509:Network interface 510:User interface F1:Light F2:Light L1:Light L2:Light LE1: metal ion LE2: Metal ions X: direction Y: direction Z: direction

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claimed claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description. Figure 1 is a top view schematic diagram illustrating a wafer according to some embodiments of the present disclosure. FIG. 2 is an enlarged schematic diagram illustrating some embodiments of the present disclosure, such as a dotted area shown in FIG. 1 . FIG. 3 is a top view schematic diagram illustrating the structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating a cross-section along line A-A’ of FIG. 3 according to some embodiments of the present disclosure. FIG. 4A is a schematic cross-sectional view illustrating the light-emitting mechanism of the light-emitting feature. FIG. 5 is a schematic top view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 6A is an optical image diagram illustrating optical images of semiconductor device structures according to some embodiments of the present disclosure. FIG. 6B is an optical image diagram illustrating optical images of semiconductor device structures according to some embodiments of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure. 7A is a schematic cross-sectional view illustrating the light-emitting mechanism of the light-emitting feature. FIG. 8 is an optical image diagram illustrating optical images of semiconductor device structures according to some embodiments of the present disclosure. FIG. 9 is an optical image diagram illustrating optical images of semiconductor device structures according to some embodiments of the present disclosure. FIG. 10 is a block diagram illustrating a semiconductor manufacturing system according to some embodiments of the present disclosure. FIG. 11 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. 12 is a schematic block diagram illustrating the hardware of a semiconductor manufacturing system according to different aspects of the present disclosure.

50a: Semiconductor component structure

100:Base

100s1: Surface

100s2: Surface

110a: Overlay mark structure

111: Pattern

112: Pattern

120: Luminous characteristics

130: Intermediate structure

140:Mask

140r:Open your mouth

X: direction

Y: direction

Z: direction

Claims (20)

A semiconductor element structure including: a base; a first luminescent feature disposed on the substrate; a first pattern disposed on the first luminescent feature; and a second pattern arranged on the first pattern; The first luminescent feature is configured to emit a light of a first wavelength, the first pattern has a first transmittance for the light of the first wavelength, and the second pattern has a first transmittance for the light of the first wavelength. The light has a second transmittance, and the first transmittance is different from the second transmittance. The semiconductor device structure of claim 1, wherein the first pattern and the second pattern are used together as a stack of marks. The semiconductor device structure of claim 1, wherein the first transmittance is less than 30%. The semiconductor device structure of claim 1, wherein the first transmittance is smaller than the second transmittance. The semiconductor device structure of claim 1, wherein the first light-emitting feature includes a plurality of metal ions. The semiconductor device structure as claimed in the claim, wherein the first pattern at least vertically overlaps the second pattern. The semiconductor device structure of claim 1, wherein the first pattern is encapsulated by an intermediate structure, the intermediate structure has a third transmittance for the light of the first wavelength, and the third transmittance Different from the first penetration rate and the second penetration rate. The semiconductor device structure of claim 7, wherein the third transmittance is in a range between the first transmittance and the second transmittance. The semiconductor device structure of claim 1, further comprising a second light emitting feature disposed between the first pattern and the second pattern, wherein the second light emitting feature is configured to emit a light of a second wavelength. , the second wavelength is different from the first wavelength. The semiconductor device structure of claim 9, wherein the second pattern has a fourth transmittance for the light of the second wavelength, and the fourth transmittance is smaller than the second transmittance. The semiconductor device structure of claim 9, wherein the second light emitting feature includes a plurality of metal ions. The semiconductor device structure of claim 1, wherein a material of the first pattern includes metal, and the second pattern includes a plurality of openings defined by a photosensitive material. A semiconductor element structure including: a base; a first luminescent feature disposed on the substrate, wherein the first luminescent feature is configured to emit a fluorescent light having a first wavelength; and A stack of marking structures is disposed on the first luminescent feature, wherein the stack of marking structures is configured to absorb or reflect the fluorescent light emitted from the first luminescent feature. The semiconductor device structure of claim 13, wherein the first luminescent feature includes a plurality of metal ions. The semiconductor device structure of claim 13, wherein the overlapping mark structure includes a first pattern and a second pattern, the second pattern is on the first pattern, and the first pattern has a wavelength corresponding to the first wavelength. The fluorescent light has a first transmittance, the second pattern has a second transmittance of the fluorescent light of the first wavelength, and the first transmittance is different from the first transmittance. The semiconductor device structure of claim 15, wherein the first pattern at least vertically overlaps the second pattern. The semiconductor device structure of claim 15, further comprising an intermediate structure disposed on the first luminescent feature, wherein the intermediate structure has a third transmittance for the phosphor of the first wavelength, and the third The third penetration rate is different from the first penetration rate and the second penetration rate. The semiconductor device structure of claim 18, wherein the third transmittance is in a range between the first transmittance and the second transmittance. The semiconductor device structure of claim 15, further comprising a second luminescent feature disposed between the first pattern and the second pattern, wherein the second luminescent feature includes a plurality of metal ions for emitting a A fluorescent light of a second wavelength, and the second wavelength is different from the first wavelength. The semiconductor device structure of claim 19, wherein the second pattern has a fourth transmittance for the phosphor of the second wavelength, and the fourth transmittance is less than the second transmittance.