TWI833185B - Method for overlay error correction and method for manufacturing a semiconductor device structure with overlay marks - Google Patents

Abstract

A method for overlay error correction includes generating a first overlay error based on a first overlay mark, wherein the first overlay error is indicative of a misalignment between a lower pattern and an upper pattern of the first overlay mark. The method also includes generating a second overlay error based on a second overlay mark, in response to an abnormal of the first overlay error is detected. The method further includes determining whether the abnormal of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern depending on the second overlay error.

Description

Correction method of stacking error and preparation method of semiconductor element

This application claims priority to U.S. Patent Application Nos. 17/568,041 and 17/568,118 (that is, the priority date is "January 4, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a stacking error correction method and a semiconductor device manufacturing method.

With the development of the semiconductor industry, it has become more important to reduce the overlay error of photoresist patterns and underlying patterns during lithography operations. Since various factors, such as the asymmetric shape of the measurement structure, make it more difficult to correctly measure stack-up error, a new stack-up marker and method are needed to more accurately measure stack-up error.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides an overlay-corrected mark. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate, and the second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern together define a first overlay error.

Another aspect of the present disclosure provides an overlay corrected mark. The mark includes a first overlay mark and a second overlay mark. The first overlay mark includes a first pattern and a second pattern disposed on a first surface of a substrate. The first overlay mark is used to generate a first overlay error. The second overlay mark includes a third pattern disposed on a second surface of the substrate and a fourth pattern disposed on the first surface of the substrate. The first surface of the substrate is opposite to the second surface of the substrate. The second overlay mark is used to generate a second overlay error, and the second overlay mark is used to correct the first overlay error.

Another aspect of the present disclosure provides a correction method for overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark, and, in response to Detect the abnormality of the first overlay error, generate a second overlay error based on a second overlay mark, and determine whether the abnormality in the first overlay error is caused by the lower pattern and the second overlay error according to the second overlay error. This misalignment of the upper pattern is caused.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate with a first surface and an opposite second surface, forming a first pattern on the first surface of the substrate, and forming a second pattern on the second surface of the substrate. pattern, forming an intermediate structure covering the second pattern, forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern jointly define a first overlay error, and in the A fourth pattern is formed on the second surface of the substrate, wherein the first pattern and the fourth pattern jointly define a second overlay error.

Embodiments of the present disclosure provide overlay marks for overlay error measurement. Two stacking marks can be shared to determine whether stacking error anomalies are caused by misalignment between the current layer and the previous layer, or by wafer warpage. Using two measuring steps with two overlapping marks prevents inaccurate adjustments of the exposure equipment. Therefore, the usable time of the exposure equipment can be increased.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that no limitation on the scope of the present disclosure is intended. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numerals may be repeated throughout the embodiments, but it is not intended that features of one embodiment apply to another embodiment even if they share the same reference numerals.

It will be understood that the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections. May be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprising" and "comprising", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or elements, but do not exclude the presence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

FIG. 1 is a top view illustrating various aspects of the present disclosure of a wafer 10 , and FIG. 2 is an enlarged view of the dotted area in FIG. 1 .

As shown in FIGS. 1 and 2 , the wafer 10 is sawn into a plurality of wafers 40 along the dicing lane 30 . Each wafer 40 may include semiconductor components, which may include active components and/or passive components. Active components may include a memory chip (eg, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (eg, a power management integrated circuit (PMIC) chip), a logic chip (e.g., system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), a radio frequency (RF) chip, a A sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (such as a digital signal processing (DSP) chip), a front-end chip (such as an analog front-end (AFE) chip), or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

As shown in FIG. 2 , overlay marks 21 and 22 may be provided on the wafer 10 . In some embodiments, overlay marks 21 or 22 may be located on cutting lanes 30 . Overlay marks 21 or 22 may be provided at the corners of the edges of each wafer 40 . In some embodiments, overlay marks 21 or 22 may be located inside wafer 40 . In some embodiments, overlay mark 21 can be used to measure whether a current layer, such as an opening of a photoresist layer, is accurately aligned with a previous layer in a semiconductor process. In some embodiments, the overlay mark 21 can be used to generate a first overlay error between the current layer (or upper layer) and the previous layer (or lower layer). In some embodiments, overlay marks 22 may be utilized to create a second overlay between two patterns (eg, a current pattern and a reference pattern) on opposite sides of wafer 10 . In some embodiments, overlay mark 22 may be utilized to correct the first overlay error resulting from overlay mark 21 . In some embodiments, the overlay mark 22 may be used to determine whether the anomaly (or anomaly) in the first overlay error generated from the overlay mark 21 is caused by misalignment of the current layer and the previous layer. In some embodiments, overlay marks 22 may be utilized to determine whether the anomaly in the first overlay error is caused by warpage of the wafer. In some embodiments, overlay marks 21 and 22 may be shared to determine the degree of warpage of wafer 10 . In some embodiments, overlay marks 21 and 22 may be shared to determine whether the anomaly in the first overlay error generated from overlay mark 21 is caused by warpage of wafer 10 .

3 is a top view illustrating stacked marks 110 for aligning different layers on a substrate 100 in accordance with various aspects of the present disclosure. As shown in FIG. 3 , a semiconductor device structure, such as a wafer, may include stacked marks 110 on a substrate 100 . In some embodiments, overlay mark 21 shown in FIG. 2 may include similar or identical patterns or structures as overlay mark 110 in FIG. 3 .

The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The substrate 100 may include an elemental semiconductor, including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, or phosphide. At least one of indium, indium arsenide and indium antimonide. An alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, where the composition of Si and Ge changes from a ratio at one location to a ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multi-layer structure, or the substrate 100 may include a multi-layer compound semiconductor structure.

Overlay mark 110 may include pattern 111 and pattern 112 on substrate 100 . Pattern 111 may be a pattern of a previous layer. Pattern 112 may be a layer of pattern. The front floor (or lower floor) may be on a different horizontal plane than the current floor (or upper floor). Each pattern 111 (or pattern 112) may be located in one of four orthogonal destination areas, two for measuring overlay error in the X direction and two for measuring overlay error in the Y direction.

When measuring an overlay error using an overlay mark (such as overlay mark 110), the deviation in the X direction is measured along a straight line in the X direction of the overlay mark 110. The deviation in the Y direction is further measured along a straight line in the Y direction of the overlay mark 110 . A single stacked mark, including patterns 111 and 112, can be used to measure the X- and Y-direction deviation between two layers on a substrate. Therefore, it can be determined whether the current layer and the previous layer are accurately aligned based on the deviation in the X direction and the Y direction. Overlay errors may include deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or a combination of both.

FIG. 3A is a cross-sectional view taken along line AA′ of FIG. 3 .

As shown in Figures 3 and 3A, the substrate 100 may have a surface 100s1 and a surface 100s2 opposite the surface 100s1. The surface 100s2 of the substrate 100 may be an active surface on which an input and output terminal is disposed. The surface 100s1 of the substrate 100 may be a back surface. The pattern 111 may be provided on the surface 100s1 of the substrate 100. The pattern 111 may be disposed within or underneath the intermediate structure 130 . In some embodiments, pattern 111 may include the same material as an isolation structure. In some embodiments, pattern 111 may be disposed at the same elevation as the isolation structure. Isolation structures may include, for example, shallow trench isolation (STI), field oxide (FOX), local oxidation of silicon (LOCOS) features, and/or other suitable isolation elements. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorosilicate (FSG), a low-k dielectric material, combinations thereof, and/or Other suitable materials.

In some embodiments, pattern 111 may include the same material as a gate structure. The gate structure may be sacrificial, for example, a dummy gate structure. In some embodiments, pattern 111 may be disposed at the same elevation as the gate structure. In some embodiments, pattern 111 may include a dielectric layer of the same material as a gate dielectric layer and a conductive layer of the same material as a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. High-k materials can have a dielectric constant (k value) greater than 4. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also contemplated by this disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may be made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The manufacturing technology of the work function layer is a metal material, and the metal material may include an N-work function metal or a P-work function metal. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC ), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also contemplated by this disclosure. The gate electrode layer can be formed by low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

In some embodiments, the pattern 111 may include the same material as a conductive via, and the material may be disposed on a conductive wire, such as the first metal layer (M1 layer). In this embodiment, the pattern 111 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may include metal nitride or other suitable materials. The conductive layer may include metals such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloys, or other suitable materials. In this embodiment, the pattern 111 can be formed by a suitable deposition process, such as sputtering or physical vapor deposition (PVD).

The intermediate structure 130 may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. In some embodiments, the intermediate structure 130 may include a conductive layer, such as a metal layer or alloy layer. In some embodiments, one or more intermediate layers may be formed by a suitable film formation method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). After the intermediate layer is formed, a thermal operation such as rapid thermal annealing can be performed. In other embodiments, a planarization operation is performed, such as a chemical mechanical polishing (CMP) operation. In other embodiments, a removal operation, such as an etching process, may be performed. The etching process may include, for example, a dry etching process or a wet etching process. It will be appreciated that additional operations may be provided before, during, and after the above-described processes, and that some of the above-described operations may be replaced or eliminated for other embodiments of the method. The order of operations/processes is interchangeable.

FIG. 3B is a cross-sectional view taken along line BB′ of FIG. 3 .

As shown in FIGS. 3 and 3B , pattern 112 is provided on intermediate structure 130 . Pattern 112 may be provided on or over surface 100s2 of substrate 100. In some embodiments, pattern 112 may be a plurality of openings defined by mask 140 . Mask 140 may be formed on intermediate structure 130 and will be removed in subsequent processes. Mask 140 may include a positive or negative photoresist (such as polymer), or a hard mask (such as silicon nitride or silicon oxynitride). Layers including mask 140 and pattern 112 may be patterned using a suitable lithography method, for example, forming a photoresist layer on intermediate structure 130 and exposing the photoresist layer into a pattern through a photomask, or The photoresist is baked and developed to form mask 140 and pattern 112. Mask 140 can then be used to define patterns into intermediate structure 130 so that portions of intermediate structure 130 exposed by the photoresist layer can be removed.

Figure 4 is a top view illustrating a stacked mark 120a according to some embodiments of the present disclosure. As shown in FIG. 4 , a semiconductor device structure, such as a wafer, may include stacked marks 120 a on a substrate 100 . In some embodiments, overlay mark 22 shown in FIG. 2 may include similar or identical patterns or structures as overlay mark 120a shown in FIG. 4 .

Overlay mark 120a may include patterns 121a and 122. In some embodiments, patterns 121a and 122 may be disposed on two opposing surfaces of substrate 100. In some embodiments, the outline of pattern 121a and the outline of pattern 122 are equiform in plan view. In some embodiments, the outline of pattern 121a and the outline of pattern 122 are symmetrical with respect to the XY plane. In some embodiments, the shape of pattern 121a and the shape of pattern 122 are substantially the same. In some embodiments, the size of pattern 121a and the size of pattern 122 are substantially the same. In some embodiments, pattern 121a overlaps at least a portion of pattern 122 along the Z direction. In some embodiments, each of patterns 121a and 122 may consist of a single continuous pattern. In some embodiments, the single continuous pattern described above may have any contour or shape. In this embodiment, the pattern 121a can also be called a reference pattern. In this disclosure, the term "isoform" may refer to two patterns that are the same size and/or shape.

When measuring a stacking error using a stacking mark, such as stacking mark 120a, the deviation in the X direction is measured along a straight line in the X direction of the stacking mark 120a. The deviation in the Y direction is further measured along a straight line in the Y direction of the stacked mark 120a. Therefore, whether the patterns 121a and 122 are accurately aligned can be determined based on the deviation in the X direction and the Y direction. Overlay errors may include deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or a combination of both.

4A is a cross-sectional view along line CC' of FIG. 4 illustrating some embodiments of the present disclosure.

In some embodiments, the pattern 121a may be disposed on the surface 100s1 of the substrate 100. In some embodiments, the pattern 121a may include a layer protruding from the surface 100s1 of the substrate 100, such as a dummy layer. In some embodiments, the material of pattern 121a may include a polycrystalline silicon layer. In some embodiments, the pattern 121a may be made of a metal, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. The pattern 121a can be formed by LPCVD, PECVD, sputtering or other suitable processes. In some embodiments, pattern 121a may include a material that is distinguishable from the material of substrate 100 by an optical image. In some embodiments, pattern 121a may include a material distinguishable from silicon oxide by optical imaging.

In some embodiments, pattern 122 may be disposed on or over surface 100s2 of substrate 100. In some embodiments, pattern 122 may be disposed on intermediate structure 130 . In some embodiments, pattern 122 may be openings or grooves defined by mask 140 . The pattern 122 may be patterned using a suitable photolithography method, for example, forming a photoresist layer over the intermediate structure 130, exposing the photoresist layer through a photomask, or baking and developing the photoresist. Mask pattern 122 is formed. In some embodiments, patterns 112 and 122 may be located on the same horizontal plane. In some embodiments, patterns 112 and 122 may be formed simultaneously. That is, the patterns 112 and 122 may be formed by the same process and formed by the same semiconductor manufacturing equipment. In some embodiments, the outline of pattern 122 may be different than the outline of pattern 112 .

In some embodiments, overlay mark 110 may be used to generate a first overlay error by measuring the position of patterns 121a and 122 to measure the misalignment of the current layer and the previous layer. In some embodiments, the first stacking error may be an anomaly caused by misalignment of the current layer and the previous layer. In some embodiments, the first stacking error is an anomaly due to reasons other than misalignment of the current layer and the previous layer. For example, wafer warpage can cause anomalies in the first overlay error. In this case, the abnormality in the first overlay error is not caused by the misalignment of the current layer and the previous layer. If the exposure equipment is adjusted only based on the first overlay error, the adjusted exposure equipment will be due to inaccuracy or inappropriateness. The adjustment will cause the next wafer to be misaligned.

The overlay mark 120a may be used to generate a second overlay error. In some embodiments, the overlay mark 120a may be utilized to correct the first overlay error based on the second overlay error. In some embodiments, overlay mark 120a may be utilized to determine whether an anomaly in the first overlay is caused by wafer warpage rather than misalignment of the current layer and the previous layer. If warping had not occurred, the optical image of pattern 121a would be superimposed on the image of pattern 122. When wafer warpage occurs, there will be a displacement between patterns 121a and 122. In some embodiments, the second overlay error may increase as the degree of warpage increases. Therefore, the second overlay error can be regarded as an indicator for estimating wafer warpage. In some embodiments, when the second overlay error exceeds a predetermined value, it may be determined that the abnormality in the first overlay error is caused by a warping problem rather than misalignment. Therefore, the exposure apparatus can avoid inaccurate adjustment of the first overlay error and the second overlay error. Furthermore, both the first overlay error and the second overlay error can be obtained by the overlay measurement device. In this embodiment, there is no need to transfer wafers with abnormal first stacking errors to warpage measurement equipment, such as patterned wafer geometry (PWG) metrology, thus improving the fabrication cycle time of semiconductor device structures.

FIG. 5 is a cross-sectional view illustrating a stacked mark 120b according to some embodiments of the present disclosure. The overlay mark 120b shown in FIG. 5 may be similar to the overlay mark 120a shown in FIG. 4A, except that the overlay mark 120b may include a pattern 121b.

In some embodiments, pattern 121b may be defined by a groove in surface 100s1 of substrate 100 . In some embodiments, etching may be performed on surface 100s1 of substrate 100 to form pattern 121b. In some embodiments, the grooves of the substrate 100 may be filled with other materials, such as dielectric materials or conductive materials.

In this embodiment, overlay mark 120b may be utilized to determine whether the anomaly in the first overlay is caused by wafer warpage rather than misalignment of the current layer and the previous layer. Therefore, the exposure apparatus may be free from inaccurate or inappropriate adjustment due to the first overlay error and the second overlay error.

Figure 6 is a cross-sectional view illustrating a stacked mark 120c according to some embodiments of the present disclosure. Overlay mark 120c shown in Figure 6 may be similar to overlay mark 120a shown in Figure 4A, except that overlay mark 120c may include pattern 121c.

In some embodiments, a dummy layer 150 may be formed on the surface 100s1 of the substrate 100. In some embodiments, pattern 121c may be defined by a groove in dummy layer 150. In some embodiments, etching may be performed on dummy layer 150 to form pattern 121c. In some embodiments, the grooves in dummy layer 150 may be filled with other materials. In some embodiments, dummy layer 150 may include a polysilicon layer. In some embodiments, the dummy layer 150 may be a metal, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, a portion of surface 100s1 of substrate 100 may be exposed by dummy layer 150 . In some embodiments, the groove in the dummy layer 150 may be a blind hole.

In this embodiment, overlay mark 120c may be utilized to determine whether the anomaly in the first overlay is caused by wafer warpage rather than misalignment of the current layer and the previous layer. Therefore, the exposure apparatus may be free from inaccurate or inappropriate adjustment due to the first overlay error and the second overlay error.

Figure 7 is a cross-sectional view illustrating a stacked mark 160a according to some embodiments of the present disclosure. The semiconductor element structure shown in FIG. 7 is similar to the semiconductor element structure shown in FIG. 4A. The difference is that the semiconductor element structure of FIG. 7 may further include a stack mark 160a.

Overlay mark 160a may be used to generate a third overlay error. Overlay mark 160a may be used to determine whether an anomaly in an overlay error produced by another pair of current and previous layers is caused by warpage on the wafer. Although not shown, it should be noted that another pair of current and front layers may be located on and within the intermediate structure 170, respectively. The overlay mark 160a can be used to determine whether the abnormality in the overlay error is caused by the misalignment of the current layer and the previous layer.

Overlay mark 160a may include pattern 161a and pattern 162, both of which may be used to create a third overlay error. In some embodiments, the pattern 161a may be disposed on the surface 100s1 of the substrate 100. In some embodiments, pattern 161a and pattern 121a may be located on the same horizontal level. In some embodiments, the pattern 161a may be made of the same material as the pattern 121a and made by the same process. In some embodiments, the outline of pattern 161a may be the same as the outline of pattern 121a. In some embodiments, the outline of pattern 161a may be different from the outline of pattern 121a. In some embodiments, pattern 161a may not overlap pattern 121a in the Z direction.

In some embodiments, pattern 162 may be disposed on or over surface 100s2 of substrate 100. In some embodiments, pattern 162 may be located at a different location than the horizontal plane of feature 122'. Pattern 162 may be provided on intermediate structure 170 . Intermediate structure 170 may include one or more dielectric layers and conductive features disposed within the dielectric layers. Intermediate structure 170 may cover feature 122'. Features 122' may be formed by filling the openings defined by pattern 122 with a conductive or dielectric material. Features 122' may have the same pattern as pattern 122. In some embodiments, pattern 162 may be an opening or a groove defined by mask 180 . Mask 180 may be formed on intermediate structure 170 and will be removed in subsequent processes. Mask 180 may include a positive or negative photoresist. Mask 180 may be used to define a pattern in intermediate structure 170 such that portions of intermediate structure 170 exposed by the photoresist layer may be removed.

In some embodiments, the outline of pattern 162 is conformal to the outline of pattern 161a in plan view. In some embodiments, the outline of pattern 161a and the outline of pattern 162 are symmetrical with respect to the XY plane. In some embodiments, the shape of pattern 161a and the shape of pattern 162 are substantially the same. In some embodiments, the dimensions of pattern 161a and the dimensions of pattern 162 are substantially the same. In some embodiments, pattern 161a overlaps at least a portion of pattern 162 along the Z-axis.

In this embodiment, the overlay mark 160a may be used to estimate wafer warpage at a different stage than the overlay mark 120a used to estimate warpage as shown in FIG. 4A. In this embodiment, overlay mark 160a may be utilized to determine whether anomalies in overlay are caused by wafer warpage rather than misalignment between the current layer and the previous layer. Therefore, the exposure equipment is immune to inaccurate adjustments due to third layer stacking errors.

Figure 8 is a cross-sectional view illustrating stacked marks according to some embodiments of the present disclosure. The semiconductor element structure shown in FIG. 8 may be similar to the semiconductor element structure shown in FIG. 7 , except that the semiconductor element structure may further include stacking marks 160b.

Overlay mark 160b may be used to generate a third overlay error. Overlay mark 160b may be utilized to determine whether an anomaly in overlay error resulting from another pair of current and previous layers is caused by warpage on the wafer. Overlay marks 160b may be used to estimate wafer warpage at another stage than the stage in which warpage is estimated using overlay marks 120a as shown in FIG. 4A.

Overlay mark 160b may include pattern 161b and pattern 162, both of which may be used to create a third overlay error. In some embodiments, the pattern 161b may be disposed on the surface 100s1 of the substrate 100. In some embodiments, pattern 161b and pattern 121c may be located on different horizontal levels. In some embodiments, pattern 121c may be defined by a groove in dummy layer 150. In some embodiments, the grooves in the dummy layer 150 may be filled with other materials, such as dielectric materials or conductive materials. In some embodiments, the pattern 161b may be another dummy layer or a groove of another dummy layer disposed on the dummy layer 150 . For example, the material of the pattern 161b may include a polycrystalline silicon layer, a metal layer or an alloy layer, and may be formed by LPCVD, PECVD, sputtering or other suitable processes.

Although FIG. 8 illustrates that the horizontal plane of pattern 161b is lower than the horizontal plane of pattern 121c, the disclosure is not intended to be limiting. In some other embodiments, the horizontal level of the pattern 161b may be higher than the horizontal level of the pattern 121c. In some embodiments, pattern 161b may not overlap pattern 121c in the Z direction.

In this embodiment, the overlay mark 160b may be used to determine whether the overlay anomaly is caused by wafer warpage rather than misalignment of the current layer and the previous layer. Therefore, the exposure equipment is immune to inaccurate or inappropriate adjustments due to third layer stacking errors.

FIG. 9 is a block diagram illustrating a semiconductor manufacturing system 300 according to some embodiments of the present disclosure.

Semiconductor preparation system 300 may include fabrication equipment 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and overlay measurement equipment 360. Overlay correction system 370 may be included in or built into overlay measurement device 360 . The manufacturing equipment 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, the exposure equipment 350, and the overlay measurement equipment 360 can be controlled via the network 380 390 performs signal coupling. In some embodiments, the overlay correction system 370 may be an independent system that is signal-coupled with the overlay measurement device 360 through the network 380 .

Manufacturing equipment 310 may be used to form reference patterns, such as patterns 121a, 121b, 121c, 160a, or 160b as shown in Figure 4A, Figure 5, Figure 6, Figure 7, or Figure 8, respectively. Fabrication equipment 310 may be used to form patterns on the back surface of the wafer as part of overlay marks.

Fabrication equipment 320-1, ..., and 320-N may be used to form elements or features between a preceding layer, such as pattern 111 shown in Figure 3A, and a substrate. Each of the manufacturing devices 320-1,..., and 320-N may be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other process.

Fabrication equipment 330 may be used to form patterns in a previous layer, such as pattern 111 shown in FIG. 5 . In some embodiments, fabrication equipment 330 may be used to form an isolation structure, a gate structure, a conductive via, or other layers. The pattern of the front layer may include dielectric material, semiconductor material or conductive material.

Fabrication equipment 340-1, ..., and 340-N may be used to form an intermediate structure, such as intermediate structure 130 shown in Figure 4A. Each of the manufacturing devices 340-1,..., and 340-N may be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process or other processes.

Exposure equipment 350 may be used to form a layer of patterns, such as patterns 112 and 122 shown in Figures 3B and 4A, respectively.

In some embodiments, the overlay measurement device 360 may be used to obtain optical images of the patterns of the previous and current layers, and generate an optical image based on the optical images of the patterns of the previous and current layers (eg, patterns 111 and 112). First overlay error. In some embodiments, overlay measurement device 360 may be used to generate a second overlay error based on the reference pattern and the patterns in the current layer (eg, patterns 121 and 122).

Overlay correction system 370 may include correction parameters for generating corrected first and second overlay errors. Overlay correction system 370 may include, for example, a computer or server. In some embodiments, each of the corrected first and second overlay errors may be generated or calculated by programming code or a programming language. For example, the corrected first overlay error may be determined from the first overlay error obtained from overlay measurement device 360 and the correction parameters of overlay correction system 370 . In some embodiments, the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination thereof, may be generated from the correction parameters. The deviation in each X direction (ΔX), the deviation in the Y direction (ΔY), or a combination of both, can be expressed by a formula that includes correction parameters as variables. In some embodiments, the overlay correction system 370 can receive optical image information from the pattern of the previous layer (or reference pattern) and the pattern of the current layer, and then generate an X-direction deviation (ΔX) and a Y-direction deviation (ΔY), or a combination of both, to compensate for the first and second overlay errors obtained from overlay measurement device 360 .

Network 380 may be the Internet or an internal network using a network protocol such as Transmission Control Protocol (TCP). Through the network 380, each of the manufacturing devices 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, the exposure device 350, and the overlay measurement device 360 can access The controller 390 downloads or uploads work-in-progress (WIP) information about wafers or manufacturing equipment.

Controller 390 may include a processor, such as a central processing unit (CPU). In some embodiments, controller 390 may be utilized to generate instructions as to whether to adjust exposure device 350 based on the first overlay error and the second overlay error.

Although FIG. 9 does not show any other manufacturing equipment prior to manufacturing equipment 310, this exemplary embodiment is not intended to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged before the manufacturing equipment 310 and may be used to perform various processes according to design requirements.

In the exemplary embodiment, wafer 301 is transferred to fabrication equipment 310 to begin a series of different processes. Wafer 301 may be formed with at least one layer of material through various stages of processes. The exemplary embodiments are not intended to limit the manufacturing process of wafer 301 . In other exemplary embodiments, the wafer 301 may include various layers before the wafer 301 is transferred to the fabrication equipment 310, or at any stage between the start and completion of the product. In an exemplary embodiment, wafer 301 may be measured by fabrication equipment 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and overlay measurement Device 360 performs processing in sequence.

FIG. 10 is a flowchart illustrating a method 400 for preparing stacked marks according to various aspects of the present disclosure.

The preparation method 400 begins with operation 410, where a substrate is provided. The substrate may have a first surface and a second surface opposite to the first surface. The first surface may also be referred to as the back surface. The second surface, which may also be referred to as an active surface, has active features formed thereon, such as a gate structure or a wire connected to the input and output terminals.

The manufacturing method 400 continues with operation 420, where a first pattern is formed on the first surface of the substrate. In some embodiments, the first pattern may be a polysilicon layer on the first surface of the substrate. In some embodiments, the first pattern may be a groove on the first surface of the substrate. In some embodiments, the first pattern may be a groove formed in a polysilicon layer on the first surface of the substrate. In some embodiments, the preparation method 400 may include forming a polycrystalline silicon layer on the first surface of the substrate, and then patterning the polycrystalline silicon layer to form a first pattern. In some embodiments, the remainder of the polysilicon layer may be used to define the first pattern. In some embodiments, a groove or an opening in the polysilicon layer may be used to define the first pattern. In some embodiments, the preparation method 400 may include removing a portion of the substrate from the first surface of the substrate to form a groove as a first pattern. The first pattern may be formed by, for example, manufacturing equipment 310 shown in FIG. 9 .

The preparation method 400 continues with operation 430, where a second pattern is formed on the second surface of the substrate. The second pattern may include the same material as the isolation features, gate structures, or conductive vias. The second pattern may be formed by a process used to form isolation features, gate structures, or conductive vias. For example, the second pattern may be formed by manufacturing equipment 330 shown in FIG. 9 .

The manufacturing method 400 continues with operation 440, in which an intermediate structure is formed to cover the second pattern. The intermediate structure may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. The intermediate structure may include conductive features formed in the dielectric layer. In some embodiments, the intermediate structure can be formed by CVD, PVG, ALD, dry etching, wet etching, CMP, and lithography processes. The intermediate structure may be formed by, for example, manufacturing equipment 340-1, ..., and 340-N shown in Figure 9.

The manufacturing method 400 continues with operation 450, in which a third pattern is formed to be vertically aligned with the second pattern, and a fourth pattern is formed to be vertically aligned with the first pattern. In some embodiments, the third pattern and the fourth pattern may be openings of a mask, such as a photoresist layer. In some embodiments, operation 450 may include, for example, forming a photoresist layer on the intermediate structure, exposing the photoresist layer into a pattern through a photomask, baking and developing the photoresist to form a masked third pattern, and The fourth pattern. The third pattern and the fourth pattern may be formed by at least the exposure device 350 shown in FIG. 9 .

The second pattern and the third pattern may be used together to create a first overlay error that measures offset between previous and current layers. The first pattern and the fourth pattern may be used cooperatively to generate a second overlay error to determine whether the anomaly in the first overlay error is caused by misalignment between the previous layer and the current layer. The first pattern, the second pattern, the third pattern and the fourth pattern may be used together to measure the degree of wafer warpage.

FIG. 11 is a flowchart illustrating a method 500 for overlay correction in various aspects of the present disclosure.

The method begins at operation 510, where a first overlay mark and a second overlay mark are provided. The first overlay mark may include overlay mark 110 as shown in FIG. 3 , which may include a first pattern of a previous layer (eg, pattern 111 ) and a second pattern of a current layer (eg, pattern 112 ). The second overlay mark may include overlay mark 120 shown in FIG. 4 . The second overlay mark may include a third pattern (eg, pattern 121) and a fourth pattern (eg, pattern 122) of the layer. In some embodiments, the second pattern and the fourth pattern may be formed by an exposure device (eg, exposure device 350).

The method continues with operation 520, where a first overlay error is generated based on the first overlay mark and a second overlay error is generated based on the second overlay mark. In some embodiments, optical images may be obtained from an overlay measurement device (eg, overlay measurement device 360). Overlay errors can occur based on optical images. A first overlay error may be calculated based on the first pattern and the second pattern. The second overlay error may be calculated based on the third pattern and the fourth pattern. In some embodiments, operation 520 may further include correcting the first overlay error and the second overlay error by an overlay correction system (eg, overlay system 370).

The method continues with operation 530 in which a first determination is performed to determine whether the first overlay error is abnormal. In some embodiments, the overlay measurement device may send a signal of the first overlay error to a controller (e.g., controller 390) via a network (e.g., network 380), and the controller may compare the first overlay error to a controller (e.g., controller 390). position error and a target first overlay error. In some embodiments, the target first stacking error may be predetermined based on semiconductor process requirements. In some embodiments, the controller may include a determination module (not shown) to perform operation 530. In some embodiments, when the first overlay error exceeds the target first overlay error, it may be determined that the first overlay error is abnormal.

Next, based on the first determination of operation 530, operation 540 or operation 550 is performed. In some embodiments, when the first overlay error is not abnormal, the exposure device can be used to perform the next exposure process without adjusting the exposure device, as shown in operation 540 .

In some embodiments, when the first overlay error is abnormal, a second determination is performed to determine whether the second overlay error is abnormal, as shown in operation 550 . In some embodiments, the overlay measurement device can send a signal of the second overlay error to the controller, and the controller can then compare the second overlay error to a target second overlay error. In some embodiments, the target second stacking error may be predetermined based on requirements of the semiconductor process. In some embodiments, a certain module of the controller may perform operation 550. In some embodiments, when the second overlay error exceeds the target second overlay error, it may be determined that the second overlay error is abnormal.

Next, based on the determination of operation 550, operation 560 or operation 570 is performed. In some embodiments, when the second overlay error has no abnormality, it may be determined that the wafer warpage causes no abnormality in the first overlay error. In this case, the exposure equipment can be adjusted, which can then be used to perform the next exposure process, as shown in operation 560.

In some embodiments, when the second overlay error is abnormal, it may be determined that the wafer warpage causes the abnormality in the first overlay error. The exposure equipment may be utilized to perform the next exposure process without adjusting the exposure equipment, as shown in operation 570 .

In some embodiments, the abnormality in the first stacking error is not caused by misalignment between the previous layer and the current layer, but is caused by wafer warpage. If the exposure equipment is adjusted based only on the first overlay error, the next wafer will suffer misalignment of the current layer and the previous layer due to inaccurate adjustment of the exposure equipment. To avoid this situation, the second stacking error can be used to determine whether the anomaly in the first stacking error is caused by wafer warpage rather than misalignment between the previous layer and the current layer. By measuring two overlapping marks in two steps, inaccurate adjustments of the exposure equipment can be prevented. Therefore, the available time of the exposure equipment can be improved.

The processes illustrated in Figures 10 and 11 may be implemented in a controller 390, or computing system that organizes the preparation of wafers by controlling each or a portion of the fabrication equipment in the facility. 12 is a diagram illustrating the hardware of a semiconductor fabrication system 600 in various aspects of the present disclosure. System 600 includes one or more hardware processors 601 and a non-transitory computer-readable storage medium 603 encoded with, ie stored with, program code (ie, a set of executable instructions). Computer-readable storage medium 603 may also be encoded with instructions for interfacing with manufacturing equipment that produces semiconductor equipment. The processor 601 is electrically connected to the computer-readable storage medium 603 through the bus 605 . Processor 601 is also electrically coupled to input and output (I/O) interface 607 via bus 605 . The network interface 609 is also electrically connected to the processor 601 via the bus 605 . The network interface is connected to a network so that processor 601 and computer-readable storage medium 603 can connect to external components via network 380. Processor 601 is configured to execute computer code encoded in computer-readable storage medium 605 such that system 600 may be used to perform some or all of the operations described in the methods shown in FIGS. 10 and 11 .

In some exemplary embodiments, processor 601 is, but is not limited to, a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. Various circuits or units are within the scope of this disclosure.

In some exemplary embodiments, computer-readable storage medium 603 is, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the computer readable storage medium 603 includes a semiconductor or solid state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read only memory (ROM), a hard disk and/or Or a CD. In one or more exemplary embodiments using optical discs, computer-readable storage media 603 also includes compact disc-read-only memory (CD-ROM), compact disc-read/write (CD-R/W), and/or digital Video disc (DVD).

In some exemplary embodiments, storage medium 603 stores computer code configured to cause system 600 to perform the methods illustrated in FIGS. 10 and 11 . In one or more exemplary embodiments, storage medium 601 also stores information required to perform the methods illustrated in Figures 10 and 11 as well as information generated during the performance of these methods and/or to perform the methods illustrated in Figures 10 and 11 A set of executable instructions for the operation of a method. In some exemplary embodiments, a user interface 610, such as a graphical user interface (GUI), may be provided for the user to operate on the system 600.

In some exemplary embodiments, storage medium 603 stores instructions for interfacing with external machines. This instruction enables the processor 601 to generate instructions readable by an external machine to effectively implement the methods illustrated in Figures 10 and 11 during analysis.

System 600 includes input and output (I/O) interfaces 607. The I/O interface 607 is connected to external circuits. In some exemplary embodiments, I/O interface 607 may include, but is not limited to, a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating to processor 601 Information and orders.

In some exemplary embodiments, I/O interface 607 may include a display, such as a cathode ray tube (CRT), liquid crystal display (LCD), speakers, etc. For example, a monitor displays information.

System 600 may also include a network interface 609 coupled to processor 601. Network interface 609 allows system 600 to communicate with network 380 to which one or more other computer systems are connected. For example, system 600 may be connected to manufacturing equipment 310, 320-1, ..., 320-N, 330, 340-1, ..., and 340-N through network interface 609 connected to network 380, exposure device 350 and overlay measurement device 360.

One aspect of the present disclosure provides an overlay-corrected mark. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate, and the second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern together define a first overlay error.

Another aspect of the present disclosure provides an overlay corrected mark. The mark includes a first overlay mark and a second overlay mark. The first overlay mark includes a first pattern and a second pattern disposed on a first surface of a substrate. The first overlay mark is used to generate a first overlay error. The second overlay mark includes a third pattern disposed on a second surface of the substrate and a fourth pattern disposed on the first surface of the substrate. The first surface of the substrate is opposite to the second surface of the substrate. The second overlay mark is used to generate a second overlay error, and the second overlay mark is used to correct the first overlay error.

Another aspect of the present disclosure provides a correction method for overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark, and, in response to Detect the abnormality of the first overlay error, generate a second overlay error based on a second overlay mark, and determine whether the abnormality in the first overlay error is caused by the lower pattern and the second overlay error based on the second overlay error. This misalignment of the upper pattern is caused.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate with a first surface and an opposite second surface, forming a first pattern on the first surface of the substrate, and forming a second pattern on the second surface of the substrate. pattern, forming an intermediate structure covering the second pattern, forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern jointly define a first overlay error, and in the A fourth pattern is formed on the second surface of the substrate, wherein the first pattern and the fourth pattern jointly define a second overlay error.

Embodiments of the present disclosure provide overlay marks for overlay error measurement. Two stacking marks can be shared to determine whether stacking error anomalies are caused by misalignment between the current layer and the previous layer, or by wafer warpage. Using two measuring steps with two overlapping marks prevents inaccurate adjustments of the exposure equipment. Therefore, the usable time of the exposure equipment can be increased.

Although the disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the patent scope. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein in accordance with the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of the present disclosure.

10:wafer 21: Overlapping markers 22: Overlapping markers 30: Cutting lane 40:wafer 100:Base 100s1: Surface 100s2: Surface 110: Overlapping markers 111: Pattern 112: Pattern 120a: Stacked Marks 120b: overlapping markers 120c: Stacked Marks 121a:Pattern 121b: Pattern 121c:Pattern 122: Pattern 122':Features 130: Intermediate structure 140:Mask 150: virtual layer 160a: Overlapping markers 160b: overlapping markers 161a:Pattern 161b: Pattern 162:Pattern 170: Intermediate structure 180:mask 300:Semiconductor Preparation Systems 310: Manufacturing equipment 320-1, …, 320-N: Manufacturing equipment 330: Manufacturing equipment 340-1, …, 340-N: Manufacturing equipment 350: Exposure equipment 360: Overlay Measurement Equipment 370: Overlay (OVL) correction system 380:Internet 390:Controller 400:Preparation method 410: Operation 420: Operation 430: Operation 440: Operation 450:Operation 500:Method 510: Operation 520: Operation 530:Operation 540: Operation 550:Operation 560:Operation 570:Operation 600:Semiconductor Preparation Systems 601: Processor 603: Computer readable storage media 605:Bus 607: Input and output (I/O) interface 609:Network interface 610:User interface A-A':line B-B':line C-C':line X: direction Y: direction Z: direction

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a top view illustrating a wafer according to some embodiments of the present disclosure. FIG. 2 is an enlarged view illustrating the dotted areas in FIG. 1 according to some embodiments of the present disclosure. Figure 3 is a top view illustrating stacked marks according to some embodiments of the present disclosure. 3A is a cross-sectional view along line AA' of FIG. 3 illustrating some embodiments of the present disclosure. 3B is a cross-sectional view along line BB' of FIG. 3 illustrating some embodiments of the present disclosure. Figure 4 is a top view illustrating stacked marks according to some embodiments of the present disclosure. 4A is a cross-sectional view along line CC' of FIG. 4 illustrating some embodiments of the present disclosure. Figure 5 is a cross-sectional view illustrating stacked marks according to some embodiments of the present disclosure. Figure 6 is a cross-sectional view illustrating stacked marks according to some embodiments of the present disclosure. Figure 7 is a cross-sectional view illustrating stacked marks according to some embodiments of the present disclosure. Figure 8 is a cross-sectional view illustrating stacked marks according to some embodiments of the present disclosure. 9 is a block diagram illustrating a semiconductor manufacturing system according to some embodiments of the present disclosure. Figure 10 is a flowchart illustrating a method for preparing overlay marks in various aspects of the present disclosure. 11 is a flowchart illustrating a method for correcting overlay errors in various aspects of the present disclosure. 12 is a diagram illustrating hardware of a semiconductor fabrication system of various aspects of the present disclosure.

100:Base

100s1: Surface

100s2: Surface

120a: Stacked Marks

121a:Pattern

122:Pattern

130: Intermediate structure

140:Mask

X: direction

Z: direction

Claims (13)

A method for correcting overlay errors, including: generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a gap between a lower pattern and an upper pattern of the first overlay mark. Misalignment; and in response to detecting an anomaly of the first overlay error: generating a second overlay error based on a second overlay mark; and determining the anomaly of the first overlay error based on the second overlay error. Is it caused by the misalignment between the lower pattern and the upper pattern. The method for correcting overlay errors according to claim 1, wherein the second overlay mark includes a first pattern provided on a first surface of a substrate and a second pattern provided on a second surface of the substrate. pattern, and wherein the first surface of the substrate is opposite the second surface of the substrate. The overlay error correction method as claimed in claim 2, wherein the second pattern and the upper pattern are located on the same horizontal level. The overlay error correction method as claimed in claim 2, wherein the second pattern at least overlaps with the first pattern. The overlay error correction method as claimed in claim 2, wherein an outline of the first pattern and an outline of the second pattern are equiform in a plan view. The overlay error correction method as claimed in claim 2, wherein the lower pattern and the upper pattern do not overlap. The overlay error correction method of claim 1 further includes: determining whether the second overlay error is abnormal, and determining whether the lower pattern and the upper pattern are misaligned. The overlay error correction method of claim 1, wherein the first overlay error and the second overlay error are shared to determine whether the abnormality of the first overlay error is caused by warpage of the wafer. cause. A method for preparing a semiconductor element, including: providing a substrate with a first surface and an opposite second surface; forming a first pattern on the first surface of the substrate; and forming a first pattern on the second surface of the substrate. forming a second pattern on the substrate; forming an intermediate structure to cover the second pattern; forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern jointly define a first overlay error; and forming a fourth pattern on the second surface of the substrate, wherein the first pattern and the fourth pattern jointly define a second overlay error. The method of manufacturing a semiconductor device as claimed in claim 9, wherein an outline of the first pattern and an outline of the fourth pattern are equiform. The method of manufacturing a semiconductor device according to claim 9, wherein forming the first pattern includes: forming a layer on the first surface of the substrate; and patterning the layer to form a first pattern. The method for manufacturing a semiconductor element according to claim 9, wherein forming the first pattern includes: removing a portion of the substrate to form a groove recessed from the first surface of the substrate, wherein the groove serves as the first pattern. The method of manufacturing a semiconductor device according to claim 9, wherein forming the first pattern includes: forming a layer on the first surface of the substrate; and removing a portion of the layer to form a groove, wherein the groove as the first pattern.