TWI825729B - Semiconductor device structure including overlay mark structure - Google Patents

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first conductive feature, a first light-emitting feature, a first pattern and a second pattern. The first light-emitting feature is disposed on the substrate. The first pattern is disposed on the first light-emitting feature. The second pattern is disposed on the first pattern. The first conductive feature is disposed on the substrate and at least laterally overlaps the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance to the light of the first wavelength. The second pattern has a second transmittance to the light of the first wavelength. The first transmittance is different from the second transmittance.

Description

Semiconductor element structure with stacked mark structure

This application claims priority to U.S. Patent Application Nos. 17/683,474 and 17/683,845 (that is, the priority date is "March 1, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device structure. In particular, it relates to a semiconductor device structure having a stacked mark structure.

With the development of the semiconductor industry, it has become more important to reduce the stacking errors of photoresist patterns and underlying patterns during lithography operations. Due to various factors, such as unclear optical images between a current layer and a pre-layer of the stacked mark structure, it is increasingly difficult to accurately measure the stacking error. Therefore, a new semiconductor element structure and the preparation of the semiconductor element structure are developed. method to more accurately measure overlay errors.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor element The device structure includes a substrate, a first conductive feature, a first light emitting feature, a first pattern, and a second pattern. The first luminescent feature is disposed on the substrate. The first pattern is disposed on the first luminescent feature. The second pattern is disposed on the first pattern. The first conductive feature at least laterally overlaps the first pattern. The first light emitting feature is configured to emit a light including a first wavelength. The first pattern has a first transmittance for the light of the first wavelength. The second pattern has a second transmittance for the light of the first wavelength. The first transmittance is different from the second transmittance.

Another aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first light-emitting feature, a stacked mark structure, and a first conductive feature. The first luminescent feature is disposed on the substrate. The first luminescent feature includes metal ions for emitting a fluorescent light including a first wavelength. The stacked mark structure is disposed on the first light emitting feature. The stacked mark structure is configured to absorb and/or reflect the fluorescent light emitted from the first luminescent feature. The first conductive feature at least laterally overlaps the stacked mark structure.

Another aspect of the present disclosure provides a method of fabricating a semiconductor device structure. The preparation method includes: providing a substrate; forming a first luminescent feature on the substrate; forming a first pattern on the first luminescent feature; forming a first conductive feature laterally overlapping the first pattern; and A second pattern is formed on the first pattern, wherein the first luminescent feature is configured to emit a light including a first wavelength, and the first pattern has a first transmittance for the light including the first wavelength. , the second pattern has a second transmittance for the light including the first wavelength, and the first transmittance is different from the second transmittance.

Embodiments of the present disclosure provide a semiconductor device structure including light emitting features. The luminescent features can be configured to emit fluorescent light. Fluorescence can improve the contrast between the current layer and the pre-layer of the superimposed mark structure in the optical image. Therefore, it can be more accurately determined based on the above optical images Calculate the overlay error.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

10:wafer

21: Overlapping markup structure

22: Overlapping markup structure

30: Cutting lane

40:wafer

50a: Semiconductor component structure

50b: Semiconductor component structure

50c: Semiconductor component structure

100:Base

100s1: Surface

100s2: Surface

110a: Stacked markup structure

110b: Stacked markup structure

111: Pattern

112:Pattern

120: Luminous characteristics

130: Intermediate structure

140:Mask

150: Luminous features

200a: Optical images

200b: Optical image

200c: Optical image

200d: Optical image

211:Contour

211':Contour

221:Contour

222:Contour

223:Contour

224:Contour

230:Contour

230':Contour

300:Semiconductor Preparation Systems

320-1,..., and 320-N: Manufacturing Equipment

330: Manufacturing equipment

340-1,..., and 340-N: Manufacturing Equipment

350: Exposure equipment

360: Overlay Measurement Equipment

370: Overlay correction system

380:Internet

390:Controller

400:Preparation method

410: Operation

420: Operation

430: Operation

440: Operation

450:Operation

460:Operation

470: Operation

480:Operation

500a: Semiconductor component structure

500b: Semiconductor component structure

500c: Semiconductor component structure

500d: Semiconductor component structure

502: Base

504:Metalization layer

506: Bottom layer

508: Photosensitive layer

510: Luminous materials

510a: Luminous Characteristics

510b: Luminous characteristics

510c: Luminous Characteristics

512: Dielectric layer

514: Dielectric layer

516:Mask

518: Conductive characteristics

520: Pattern

522: Bottom layer

524: Photosensitive layer

526a: Luminous characteristics

526b: Luminous characteristics

528: Dielectric layer

530:Mask

532:Pattern

534: Conductive characteristics

540: mark structure

600:Semiconductor Preparation Systems

601: Processor

603:Storage media

605:Bus

607: Input and output (I/O) interface

609:Network interface

610:User interface

A1: Projection area

A2: Projection area

A-A': line

F1: light (or fluorescent)

F2: light (or fluorescent)

L1:Light

L2:Light

LE1: metal ion

LE2: Metal ions

O1: Open your mouth

O2:Open your mouth

X: direction

Y: direction

Z: direction

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements.

FIG. 1 is a top view illustrating a wafer according to some embodiments of the present disclosure.

FIG. 2 is an enlarged top view of the dotted line area in FIG. 1 , illustrating some embodiments of the present disclosure.

FIG. 3 is a top view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

Figure 4A is a cross-sectional view along line AA' of Figure 3 illustrating some embodiments of the present disclosure.

Figure 4B is a light emitting mechanism illustrating a luminescence feature.

FIG. 5 is a top view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 6A is an optical image illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 6B is an optical image illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 7A is a cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 7B is a light emitting mechanism illustrating a light emitting characteristic.

FIG. 8 is an optical image illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 9 is an optical image illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 10 is a block diagram illustrating a semiconductor manufacturing system according to some embodiments of the present disclosure.

FIG. 11 is a flowchart illustrating a method of fabricating a semiconductor device structure according to various aspects of the present disclosure.

12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12I, 12J, 12K, 12L, 12M, 12N, 12O, and 12P are examples One or more stages of a method of fabricating a semiconductor device structure according to some embodiments of the present disclosure.

FIG. 13 is a cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 14 is a cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

FIG. 15 is a cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

16 is a diagram illustrating hardware of a semiconductor fabrication system of various aspects of the present disclosure.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, as well as any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layers or portions without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly dictates otherwise. It should be further understood that the terms "include" and "include", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other Characteristic, integer, step, operation, element, component, or group thereof.

Referring to FIGS. 1 and 2 , FIG. 1 is a top view illustrating various aspects of the wafer 10 of the present disclosure. FIG. 2 is an enlarged top view of the dotted area in FIG. 1 .

As shown in FIGS. 1 and 2 , the wafer 10 is cut into a plurality of wafers 40 along the dicing lane 30 . Each wafer 40 may include semiconductor components, which may include active components and/or passive components. Active components may include a memory chip (for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.); a power management chip (for example, a power management integrated circuit (PMIC) chip); a logic chip (e.g., system chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.); a radio frequency (RF) chip; a A sensor chip; a microelectromechanical system (MEMS) chip; a signal processing chip (such as a digital signal processing (DSP) chip); a front-end chip (such as an analog front-end (AFE) chip) or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

As shown in FIG. 2 , stacked mark structures 21 and 22 may be disposed on the wafer 10 . In some embodiments, overlay marking structures 21 or 22 may be located on the cutting lane 30 . Overlay mark structures 21 or 22 may be provided at the corners of the edge of each wafer 40 . In some embodiments, stacked mark structures 21 or 22 may be located inside wafer 40 . In some embodiments, one can utilize Marking structures 21 are stacked to measure whether an opening of a current layer, such as a photoresist layer, is accurately aligned with a pre-layer in the semiconductor process. In some embodiments, overlay mark structures 21 or 22 may be utilized to generate a stacking error between a current layer (or upper layer) and a pre-layer (or lower layer).

3 is a top view illustrating a semiconductor device structure 50a of various aspects of the present disclosure.

As shown in FIG. 3 , a semiconductor device structure 50a, such as a wafer, may include a stacked mark structure 110a on a substrate 100. In some embodiments, the stacked mark structure 21 shown in FIG. 2 may include similar or identical patterns or structures to the stacked mark structure 110a shown in FIG. 3 . In some embodiments, the stacked mark structure 22 shown in FIG. 2 may include similar or identical patterns or structures as the stacked mark structure 110a shown in FIG. 3 .

The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. The substrate 100 may include an elemental semiconductor, including a single crystal form, a polycrystalline form, or an amorphous form of silicon or germanium; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, or phosphide. At least one of indium, indium arsenide and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, where the composition of Si and Ge changes from a ratio at one location to a ratio at another location of the gradient SiGe feature. In another embodiment, a SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multi-layer structure, or the substrate 100 may include a multi-layer compound semiconductor structure.

In some embodiments, in accordance with various aspects of the present disclosure, stacked Marking structure 110a aligns different layers on substrate 100. The stacked mark structure 110a may include patterns 111 and 112 on the substrate 100. Pattern 111 may be a pre-layered pattern. Pattern 112 may be a pattern of a current layer. The pre-layer (or lower layer) can be on a different horizontal plane than the current layer (or upper layer). The pre-layer (or lower layer) can be located at a lower horizontal layer than the current layer (or upper layer). In some embodiments, pattern 111 may at least partially overlap pattern 112 along the Z direction.

When measuring a stacking error using a stacked mark structure, such as the stacked mark structure 110a, the X-direction deviation is measured along a straight line in the X-direction of the stacked mark structure 110a. The Y-direction deviation is further measured along a straight line in the Y-direction of the stacked mark structure 110a. A single stacked mark structure, including patterns 111 and 112, can be used to measure X- and Y-direction deviations between two layers on a substrate. Therefore, it can be determined whether the current layer and the pre-layer are accurately aligned based on the deviations in the X- and Y-directions. Overlay errors may include deviations in the X-direction (ΔX), deviations in the Y-direction (ΔY), or a combination of both.

Figure 4A is a cross-sectional view along line AA' of Figure 3 illustrating some embodiments of the present disclosure. In some embodiments, semiconductor element structure 50a may also include light emitting features 120, intermediate structures 130, and masks 140.

As shown in FIG. 4A, the substrate 100 may have a surface 100s1 and a surface 100s2 opposite the surface 100s1. The surface 100s2 of the substrate 100 may be an active surface on which the input/output terminals are disposed. The surface 100s1 of the substrate 100 may be a back surface.

In some embodiments, light emitting features 120 may be disposed on surface 100s2 of substrate 100. In some embodiments, the light emitting feature 120 may be used to emit light having a first wavelength band. In some embodiments, the luminescent feature 120 may be used to emit fluorescent light having a first wavelength band. In some embodiments, light emitting feature 120 may include a dielectric layer and a light emitting material therein. For example, after a light of a specific wavelength is incident on the luminescent feature 120, the luminescent material Can absorb light and be excited. The excited luminescent material can emit light with the first wavelength band. It should be noted that in other embodiments, the light (or fluorescence) emitted by the luminescent feature may be light of a specific wavelength.

The wavelength of the light that induces fluorescence may depend on the luminescent material of luminescent feature 120 . In some embodiments, the first band (or wavelength) may range from about 100 nanometers to about 1000 nanometers, such as 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers nanometer, 700 nanometer, 800 nanometer, 900 nanometer or 1000 nanometer. For example, the wavelength of light emitted from light emitting features 120 may include a range from approximately 300 nanometers to approximately 500 nanometers. In another illustration, the wavelength of light emitted from light emitting features 120 may be 617 nanometers.

The dielectric layer of light emitting feature 120 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or other suitable materials.

In some embodiments, the luminescent material of luminescent features 120 may include metal ions of transition metals, such as europium (Eu), talonium (Tm), phosphorus (Pr), neodymium (Nd), samarium (Sm), phosphorus (Tb) , dysprosium (Dy), 鈥(Ho), erbium (Er), ytterbium (Yb), cerium (Ce), cadmium (Pm), 铓(Gd), 鑥(Lu), thorium (Th), 铩(Pa) , uranium (U), nithenium (Np), plutonium (Pu), gallium (Am), gallium (Cm), beryllium (Bk), gallium (Cf), gallium (Es), fermium (Fm), mendium (Md) , 鍩(No), 鍩(Lr), combinations thereof or other suitable metals.

In some embodiments, the luminescent material of luminescent features 120 may include organic materials, such as compounds or polymers that include aromatic groups. For example, the luminescent material of luminescent feature 120 may include a luminescent material selected from the group consisting of benzene, naphthalene, pyridine, pyrimidine, triazine, thiophene, isothiazoles, triazole, pyridazine, pyrrole, pyrazole, imidazole, thiadiazole, pyrazine, furan, Isoxazole, oxazole, oxadiazole, quinoline, isoquinoline, quinoxaline, quinazoline, thiadiazole, benzotriazine, phthalazine, tetrazole, Indole, benzofuran, benzothiophene, benzoxazole, benzothiazole, indazole, benzimidazole, benzotriazole, benziisothiazole, benzothiadiazole, dibenzofuran, diphenyl functional groups of thiophene, dibenzoselenophene, carbazole or other suitable functional groups.

In some embodiments, the luminescent material of luminescent features 120 may include a semiconductor material. In some embodiments, the luminescent material of the luminescent feature 120 may include a homojunction, a heterojunction, a single quantum well (SQW), a multiple quantum well (MQW), or any other suitable structure. In some embodiments, the luminescent material may include _{InxGa (1-x} )N, _{AlxInyGa (1-xy) N} , or other suitable materials.

In some embodiments, pattern 111 may be disposed on light emitting features 120 . In some embodiments, pattern 111 may vertically overlap light emitting features 120 . In some embodiments, pattern 111 may overlap with light emitting features 120 in the Z direction. Pattern 111 may be provided within or underneath intermediate structure 130 . In some embodiments, pattern 111 may include the same material as an isolation structure. In some embodiments, pattern 111 may be disposed at the same elevation as the isolation structure. The isolation structure may include, for example, a shallow trench isolation (STI), a field oxide (FOX), a local oxide of silicon (LOCOS) feature, and/or other suitable isolation elements. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate (FSG), a low-k (dielectric constant) dielectric material, combinations thereof, and/or other suitable Material.

In some embodiments, pattern 111 may include the same material as a gate structure. The gate structure may be sacrificial, for example, a dummy gate structure. In some embodiments, the pattern 111 may be disposed at the same elevation as the gate structure. In some embodiments, the pattern 111 may include a dielectric layer made of the same material as a gate dielectric layer and a conductive layer made of the same material as a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. High-k dielectric materials may have a dielectric constant (k value) greater than 4. High-k dielectric materials may include hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ) or other suitable materials. Other suitable materials are contemplated by this disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may include conductive materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the electrode layer may include a work function layer. The work function layer includes a metal material, and the metal material may include an N-work function metal or a P-work function metal. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC ), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are contemplated by this disclosure. The manufacturing technology of the gate electrode layer may include low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

In some embodiments, the pattern 111 may include the same material as a conductive via, which may be disposed on a conductive trace, such as zero metal layer (M0), first metal layer (M1), second metal layer (M1), M2) etc. In this embodiment, the pattern 111 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may include metal nitride or other suitable materials. The conductive layer may include metals such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloys, or other suitable materials. In this embodiment, the manufacturing technology of the pattern 111 may include a suitable deposition process, such as sputtering and physical vapor deposition. product(PVD).

Intermediate structure 130 may include one or more intermediate layers including insulating material, such as silicon oxide or silicon nitride. In some embodiments, the intermediate structure 130 may include a conductive layer, such as a metal layer or alloy layer.

The pattern 112 is provided on the intermediate structure 130 . The pattern 112 may be disposed on or on the surface 100s2 of the substrate 100. In some embodiments, pattern 112 may at least vertically overlap pattern 111 . In some embodiments, pattern 112 may overlap pattern 111 at least along the Z direction. In some embodiments, pattern 112 may at least vertically overlap light emitting features 120 . In some embodiments, pattern 112 may overlap light emitting features 120 at least along the Z direction. In some embodiments, pattern 112 may be a plurality of openings defined by mask 140 . Mask 140 may be formed on intermediate structure 130 and will be removed in subsequent processes. Mask 140 may include a positive or negative photoresist, such as polymer, or a hard mask, such as silicon nitride or silicon oxynitride. The current layer, including the mask 140 and the pattern 112, can be patterned using a suitable lithography process. For example, a photoresist layer is formed on the intermediate structure 130, and a photomask is used to expose the photoresist layer to a pattern. The photoresist is baked and developed to form mask 140 and pattern 112 . The mask 140 can then be used to define patterns into the intermediate structure 130 so that the exposed portions of the intermediate structure 130 from the photoresist layer can be removed.

In some embodiments, stacked mark structure 110a may be configured to absorb and/or reflect light (or fluorescence) emitted from light emitting features 120. In some embodiments, pattern 111 may be configured to absorb and/or reflect light (or fluorescence) emitted from light emitting features 120 . Pattern 111 may have a first transmittance for a first band (or wavelength) of light (or fluorescence) emitted by light emitting features 120 . The pattern 112 may have a second transmittance for the first band (or wavelength) of light (or fluorescence) emitted by the light emitting feature 120 . In some embodiments, the first transmittance and the second transmittance The emissivity is different. In some embodiments, the first transmittance is less than the second transmittance. In some embodiments, the first transmittance may be less than 30%, such as 30%, 20%, 15%, 10%, 7%, 5%, 3%, 1%, or even less. A larger transmittance difference between patterns 111 and 112 may help an overlay measurement device identify patterns 111 and 112 in an optical image. In this embodiment, the light (or fluorescence) emitted by the light-emitting features 120 can improve the contrast between the patterns 111 and 112 of the optical image. For example, the outlines of patterns 111 and 112 in the optical image can be clearly recognized by the sensors of the overlay measurement device. Therefore, the overlay error can be calculated more accurately.

FIG. 4B illustrates a light emitting mechanism of the light emitting feature 120 .

In some embodiments, luminescent features 120 may include metal ions LE1 therein. In some embodiments, the light emitting feature 120 may emit light (or fluorescent light) F1 when the metal ion LE1 receives the light L1. In some embodiments, the first transmittance of the pattern 111 to the light (or fluorescent light) F1 and the second transmittance of the pattern 112 to the light (or fluorescent light) F1 are different.

FIG. 5 is a top view illustrating a semiconductor device structure 50b according to some embodiments of the present disclosure. The semiconductor element structure 50b shown in FIG. 5 may be similar to the semiconductor element structure 50a shown in FIG. 3 , except that the semiconductor element structure 50b may include a stacked mark structure 110b in place of the stacked mark structure 110a.

As shown in FIG. 5 , the stacked mark structure 110b may include a plurality of patterns 111 and 112 . Each pattern 111 or 112 may be located in one of four orthogonal destination areas, two configured to measure overlay error in the X-direction and two configured to measure overlay error in the Y-direction.

FIG. 6A is an optical image 200a illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, optical image 200a may include outline 211 and outline 230. The outline 211 may correspond to the image of the pattern 111 . Outline 230 may correspond to an image of intermediate structure 130 . In some embodiments, the intermediate structure 130 may have a third transmittance for the first band (or wavelength) of light (or fluorescence) emitted by the light emitting feature 120 . In some embodiments, the first transmittance and the third transmittance are different. In some embodiments, the first transmittance is less than the third transmittance. As shown in FIG. 6A , in the optical image 200a, the brightness of the contour 230 may exceed the brightness of the contour 211.

FIG. 6B is an optical image 200b illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, optical image 200b may include contours 211' and 230'. The outline 211' may correspond to the image of the pattern 111. Outline 230' may correspond to an image of intermediate structure 130. In some embodiments, the first transmittance may exceed the third transmittance. As shown in FIG. 6B, in the optical image 200b, the brightness of the contour 211' may exceed the brightness of the contour 230'.

In this embodiment, the contrast between the pattern 111 and the intermediate structure 130 of the optical image (eg, 200a or 200b) can be improved, which helps to identify the outline of the pattern 111. Therefore, the overlay error can be calculated more accurately.

Likewise, the contrast between pattern 112 and intermediate structure 130 may also be controlled or modified. In some embodiments, the second transmittance may be less than the third transmittance. In some embodiments, the second transmittance may exceed the third transmittance. In some embodiments, the third transmittance may be within the range of the first transmittance and the second transmittance. By adjusting the relationship between the first transmittance, the second transmittance and the third transmittance, the overlay error can be calculated more accurately.

FIG. 7A is a cross-sectional view illustrating a semiconductor device structure 50c of various aspects of the present disclosure. The semiconductor element structure 50c shown in FIG. 7A may be similar to the semiconductor element structure 50a shown in FIG. 4A, except that the semiconductor element structure 50c may also include a light emitting feature 150.

In some embodiments, light emitting features 150 may be disposed beneath pattern 112 . In some embodiments, light emitting features 150 may be disposed between patterns 111 and 112 . In some embodiments, light emitting features 150 may be disposed between intermediate structure 130 and pattern 112 . In some embodiments, light emitting features 150 may be embedded into intermediate structure 130 . In some embodiments, pattern 112 may vertically overlap light emitting features 150 . In some embodiments, pattern 112 may overlap with light emitting features 150 in the Z direction. In some embodiments, the light emitting feature 150 may be utilized to emit light having a second band (or wavelength) that is different from the first band (or wavelength). In some embodiments, luminescent features 150 may be used to emit fluorescent light having a second band (or wavelength). In some embodiments, light emitting feature 150 may include a dielectric layer and a light emitting material doped therein. For example, after a light of a specific wavelength is incident on the luminescent feature 150, the luminescent material can absorb the light and be excited. The excited luminescent material can emit light with a second waveband (or wavelength).

The wavelength of the light that induces fluorescence may depend on the luminescent material of the luminescent feature 150 . In some embodiments, the second waveband (or wavelength) may range from about 100 nanometers to about 1000 nanometers, such as 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers nanometer, 700 nanometer, 800 nanometer, 900 nanometer or 1000 nanometer.

The dielectric layer of light emitting feature 150 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), oxynitride (SiON), or other suitable materials.

In some embodiments, the luminescent material of luminescent features 150 may include metal ions of transition metals, such as Eu, Tm, Pr, Nd, Sm, Tb, Dy, Ho, Er, Yb, Ce, Pm, Gd, Lu, Th , Pa, U, Np, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, No, Lr or other suitable metals. In some embodiments, the luminescent material of luminescent features 150 may include organic materials, such as compounds or polymers that include aromatic groups. things. In some embodiments, the luminescent material of luminescent features 150 may include a semiconductor material. In some embodiments, the luminescent material of luminescent features 150 may include a homogeneous interface, a heterogeneous interface, a single quantum well (SQW), a multiple quantum well (MQW), or any other suitable structure.

In some embodiments, stacked mark structure 110a may be configured to absorb and/or reflect light (or fluorescence) emitted from light emitting features 150. In some embodiments, pattern 112 may be configured to absorb and/or reflect light (or fluorescence) emitted from light emitting features 150 . The pattern 112 may have a fourth transmittance for a second band (or wavelength) of light (or fluorescence) emitted by the light emitting feature 150 . In some embodiments, the fourth transmittance is different from the first transmittance. In some embodiments, the fourth transmittance is different from the second transmittance. In some embodiments, the fourth transmittance is less than the second transmittance. In some embodiments, the fourth transmittance is different from the third transmittance. In some embodiments, the fourth transmittance is less than the third transmittance. In some embodiments, the fourth transmittance may be less than 30%, such as 30%, 20%, 15%, 10%, 7%, 5%, 3%, 1%, or less. The light (or fluorescence) emitted by the light emitting features 150 can improve the contrast of the patterns 111, 112 and/or the intermediate structure 130. Therefore, the overlay error can be calculated more accurately.

FIG. 7B illustrates a light emission mechanism of the light emitting feature 150.

In some embodiments, luminescent features 150 may include metal ions LE2 therein. In some embodiments, when metal ion LE2 receives light L2, light emitting feature 150 may emit light (or fluorescence) F2. In some embodiments, the third transmittance of the pattern 112 to the light (or fluorescent light) F2 and the second transmittance of the pattern 112 to the light (or fluorescent light) F1 (as shown in FIG. 4B ) are different. In some embodiments, the wavelength of light L1 may be different from the wavelength of light L2. In some embodiments, the wavelength of light (or fluorescent light) F1 may be different from the wavelength of light (or fluorescent light) F2. In some embodiments, metal ion LE1 may be different from metal ion LE2.

8 is an optical diagram illustrating the structure of a semiconductor device according to some embodiments of the present disclosure. Image 200c.

In this embodiment, the overlay error between patterns 111 and 112 is not equal to zero. That is, patterns 111 and 112 are offset in the X-direction, Y-direction, or a combination thereof. In some embodiments, optical image 200c may include contours 221, 222, 223, and 224. The outline 221 may correspond to an image of an area in which no patterns 111 and 112 are disposed on the intermediate structure 130 . Outline 222 may correspond to an image of an area where pattern 112 does not vertically overlap pattern 111 . Outline 223 may correspond to an image of an area where pattern 111 vertically overlaps pattern 112 . Outline 224 may correspond to an area of the image where pattern 111 does not vertically overlap pattern 112 .

In some embodiments, outline 221 may exhibit a color that includes a first band (or wavelength) and a second band (or wavelength). In some embodiments, outline 222 may exhibit colors that include the first band (or wavelength). In some embodiments, outline 223 may appear in a less bright color than outline 221, 222, or 224. In some embodiments, outline 224 may exhibit a color that includes a second band (or wavelength).

Since the contrast between the pattern 111, the pattern 112, and the overlapping area between the patterns 111 and 112 can be improved in the optical image 200c, the overlay error can be calculated more accurately.

FIG. 9 is an optical image 200d illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

In this embodiment, the overlay error between patterns 111 and 112 is equal to zero. That is, the pattern 111 is aligned with the pattern 112 along the X-direction and the Y-direction. In some embodiments, optical image 200d may include outline 221 and outline 223.

By calculating the area of contour 223, the extent of the overlay error can be determined. Depend on Since the contour 223 can be clearly identified in this embodiment, the overlay error can be calculated more accurately.

FIG. 10 is a block diagram illustrating a semiconductor manufacturing system 300 according to some embodiments of the present disclosure.

The semiconductor preparation system 300 may include manufacturing equipment 320-1, . . . , and 320-N, 330, 340-1, . Overlay correction system 370 may be included in or built into overlay measurement device 360 . The manufacturing equipment 320-1,..., and 320-N, 330, 340-1,..., and 340-N, the exposure equipment 350, and the overlay measurement equipment 360 can perform signal coupling with the controller 390 through the network 380. In some embodiments, the overlay correction system 370 may be a stand-alone system that is signal-coupled with the overlay measurement device 360 through the network 380 .

Fabrication equipment 320-1,..., and 320-N may be used to form elements or features, such as light emitting features 120 shown in Figure 4A, between a pre-layer (eg, pattern 111) and the substrate. Each manufacturing equipment 320-1, ..., and 320-N may be used to perform a deposition process, etching process, chemical mechanical polishing process, photoresist coating process, baking process, alignment process, or other processes.

Fabrication equipment 330 can be used to form patterns in a pre-layer, such as pattern 111 shown in Figure 4A. In some embodiments, fabrication equipment 330 may be used to form an isolation structure, a gate structure, a conductive via, or other layers. The pattern of prelayers may include dielectric, semiconductor, or conductive materials.

Fabrication equipment 340-1,..., and 340-N may be used to form an intermediate structure, such as intermediate structure 130 shown in Figure 4A. Each of the manufacturing devices 340-1, ..., and 340-N may be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

Exposure equipment 350 may be used to form a pattern of a current layer, such as pattern 112 shown in Figure 4A.

In some embodiments, the overlay measurement device 360 may be used to obtain optical images of patterns of pre-layers and current layers, and based on the optical images (e.g., patterns 111 and 112) of the pre-layer and current layers (e.g., patterns 111 and 112), , the optical image 200a, 200b, 200c or 200d) produces a superposition error.

Overlay correction system 370 may include correction parameters for generating corrected first and second overlay errors. Overlay correction system 370 may include, for example, a calculator or a server. In some embodiments, the corrected overlay error may be generated or calculated by programming code or programming language. For example, the corrected overlay error may be determined from the overlay error obtained from the overlay measurement device 360 and the correction parameters of the overlay correction system 370 . In some embodiments, the X-direction deviation (ΔX), the Y-direction deviation (ΔY), or a combination of both, may be generated from the correction parameters. Each X-direction deviation (ΔX), Y-direction deviation (ΔY), or a combination of both, can be expressed by a formula in which the correction parameters are used as variables. In some embodiments, the overlay correction system 370 can receive optical image information from the pre-layer pattern and the current layer pattern, and then generate an X-direction deviation (ΔX), a Y-direction deviation (ΔY), or both. A combination of these to compensate for the overlay error obtained from the overlay measurement device 360.

Network 380 may be the Internet or an internal network implementing a network communication protocol such as Transmission Control Protocol (TCP). Through network 380, each manufacturing device 320-1, ..., and 320-N, 330, 340 -1,..., and 340-N, exposure equipment 350, and overlay measurement equipment 360 may download or upload work-in-progress (WIP) information about the wafer or manufacturing equipment from the controller 390.

Controller 390 may include a processor, such as a central processing unit (CPU). In some embodiments, the controller 390 may be utilized to generate whether the error and the second overlay error to adjust the instructions of the exposure device 350 .

Although FIG. 10 does not show any other manufacturing equipment prior to manufacturing equipment 320, this exemplary embodiment is not meant to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged before the manufacturing equipment 320 and may be used to perform various processes according to design requirements.

In the exemplary embodiment, wafer 310 is transferred to fabrication equipment 320 to begin a series of different processes. Wafer 310 may be formed with at least one layer of material through various stages of processes. The illustrative embodiments are not intended to limit the manufacturing process of wafer 310 . In other exemplary embodiments, the wafer 310 may include various layers before the wafer 310 is transferred to the fabrication equipment 320, or at any stage between the start and completion of the product. In an exemplary embodiment, wafer 310 may be sequentially produced by fabrication equipment 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and overlay measurement equipment 360 for processing.

FIG. 11 is a flowchart illustrating a method of fabricating a semiconductor device structure according to various aspects of the present disclosure.

The preparation method 400 begins with operation 410, where a substrate is provided. The base may have a first surface and a second surface opposite to the first surface. The first surface may also be referred to as the back surface. The second surface may also be referred to as the active surface, on which active features are formed, such as gate structures or wires connected to the input/output terminals.

The method 400 continues with operation 420 where a first luminescent feature is formed on the substrate. In some embodiments, the first luminescent feature may include a luminescent material in the dielectric layer. In some embodiments, the luminescent material may include, for example, Eu, Tm, Pr, Nd, Sm, Tb, Dy, Ho, Er, Yb, Ce, Pm, Gd, Lu, Th, Pa, U, Np, Pu, Am , Cm, Bk, Cf, Es, Fm, Md, No, Lr or other suitable metal ions. exist In some embodiments, the metal ions may be formed in a liquid dielectric material. Liquid dielectric materials, including metal ions, can be formed on the substrate by, for example, spin coating. An annealing process and/or a baking process may be performed to solidify the liquid dielectric material, thereby forming the first light emitting feature. In other embodiments, the first light-emitting feature may include organic materials and/or semiconductor materials, and the fabrication technology may include appropriate processes. Fabrication techniques for the first light emitting feature may include devices 320-1, ..., and 320-N shown in Figure 10.

The manufacturing method 400 continues with operation 430, where a first pattern and a first conductive feature are formed on the second surface of the substrate. The first pattern may include the same material as the first conductive features. In some embodiments, the first conductive feature is a conductive via in a metallization layer (eg, M0, M1, M2, etc.). The manufacturing technology of the first pattern and the first conductive feature may include processes, such as CVD, PVD, ALD or other suitable processes. The fabrication technique of the first pattern and the first conductive feature may include the device 330 shown in FIG. 10 .

The manufacturing method 400 continues with operation 440, where an intermediate structure is formed to cover the first pattern and the first conductive feature. The intermediate structure may include one or more intermediate layers containing an insulating material, such as silicon oxide or silicon nitride. The intermediate structure may include conductive features formed in the dielectric layer. In some embodiments, the manufacturing technology of the intermediate structure may include CVD, PVD, ALD, dry etching, wet etching, CMP, and photolithography processes. Fabrication techniques for the first light emitting feature may include devices 340-1, ..., and 340-N shown in Figure 10.

The method 400 continues with operation 450, where a second luminescent feature is formed on the substrate. In some embodiments, the second luminescent feature may include luminescent material in a dielectric layer. In some embodiments, the luminescent material may include metal ions, such as Eu, Tm, Pr, Nd, Sm, Tb, Dy, Ho, Er, Yb, Ce, Pm, Gd, Lu, Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, No, Lr or other suitable gold genus. In some embodiments, the metal ions may be produced in a liquid dielectric material. Fabrication techniques for liquid dielectric materials (including metal ions) may include, for example, spin coating, to be formed on the intermediate structure. An annealing process and/or a baking process may be performed to solidify the liquid dielectric material, thereby forming the second light emitting feature. In other embodiments, the second light-emitting feature may include organic materials and/or semiconductor materials, and the fabrication technology may include appropriate processes. In some embodiments, operation 450 is optional. In some embodiments, operation 450 may be omitted.

The method 400 continues with operation 460 where a second pattern is formed on the second light emitting feature. In some embodiments, the second pattern may be an opening of a mask (eg, a photoresist layer). In some embodiments, operation 460 may include, for example, forming a photoresist layer on the intermediate structure or on the second light emitting feature, exposing the photoresist layer to a pattern of a photomask, baking and developing the photoresist layer. Form a second pattern. Additionally, the opening defined by the mask may be vertically aligned with the first conductive feature. The production technology of the second pattern may include at least the exposure device 350 shown in FIG. 10 .

The preparation method 400 continues with operation 470, in which an overlay error is generated. Overlay errors may be generated based on the first pattern and the second pattern. In some embodiments, an optical image can be obtained by stacking measurement devices. In some embodiments, the overlay measurement device may include a light source, a light sensor, and a light filter. In some embodiments, a light source may be utilized to emit light to excite the luminescent material of the first luminescent feature, thereby inducing fluorescence. In some embodiments, a light sensor may be used to receive fluorescent light emitted by the first luminescent feature and/or the second luminescent feature, thereby generating an optical image. In some embodiments, a filter may be used to select a specific wavelength of light received by the light sensor, thereby improving the contrast of the optical image. Overlay errors can be determined from optical images. In this embodiment, the contrast of the outlines of the first pattern, the second pattern and the intermediate structure can be determined by the fluorescent light emitted by the first luminescent feature and/or the second luminescent feature. Light to improve. Therefore, the overlay error can be calculated more accurately. Overlay errors may be generated by the exposure apparatus 350 shown in FIG. 10 .

The method 400 continues with operation 480 where a second conductive feature vertically aligned with the first conductive feature may be formed. In some embodiments, after the overlay error is generated, an etching process is performed to remove the intermediate structure on the first conductive feature, thereby forming an opening exposing the first conductive feature. Next, a conductive material can be deposited to fill the opening and fill the second pattern. Therefore, the second conductive feature can be formed on the first conductive feature. In some embodiments, the second conductive feature is a conductive via on a metallization layer, such as M1, M2, etc. The manufacturing technology of the second conductive feature may include a process, such as CVD, PVD, ALD or other suitable processes.

12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12I, 12J, 12K, 12L, 12M, 12N, 12O, and 12P are examples One or more stages of a method of manufacturing a semiconductor device structure 500a according to some embodiments of the present disclosure.

Referring to Figure 12A, a substrate 502 may be provided. Substrate 502 may be a semiconductor substrate. In some embodiments, metallization layer 504 may be formed on substrate 502 . In some embodiments, underlayer 506 may be formed over metallization layer 504 . Metallization layer 504 may include metals such as W, Al, Cu, Ti, Ta, alloys thereof, or other suitable materials. Metallization layer 504 may be M0, M1, M2, etc. Bottom layer 506 may include multiple dielectric layers, some of which may act as an anti-reflective coating (ARC) layer.

Referring to FIG. 12B, a photosensitive layer 508 may be formed on the bottom layer 506. In some embodiments, the photosensitive layer 508 may include a photoresist, such as a positive or negative photoresist.

Referring to FIG. 12C, an etching process may be performed to remove portions of the photosensitive layer 508 and the bottom layer 506, thereby forming a groove. In some embodiments, the exposed upper surface of bottom layer 506 may serve as a bottom of the groove. The light emitting material 510 may be formed on the photosensitive layer 508 . In some embodiments, luminescent material 510 may fill the grooves defined by photosensitive layer 508 and bottom layer 506 . In some embodiments, the luminescent material 510 may include metal ions doped with transition metals in a dielectric layer, such as SiO ₂ , SiN, SiON, or other suitable materials. The luminescent material 510 can emit fluorescence after the metal ions absorb light of a specific wavelength.

Referring to FIG. 12D, an etching process may be performed to remove part of the luminescent material 510 and the bottom layer 506, as well as the remaining photosensitive layer 508, thereby forming the luminescent feature 510a. In some embodiments, the etching process may include, for example, a dry etching process. In some embodiments, a portion of the lateral surface of light emitting feature 510a may be exposed. In some embodiments, a portion of the light emitting feature 510a may be embedded in the underlying layer 506.

Referring to Figure 12E, dielectric layer 512 may be formed to cover light emitting features 510a. In some embodiments, dielectric layer 512 may cover the upper and side surfaces of light emitting feature 510a. In some embodiments, dielectric layer 512 may include SiO ₂ , SiN, SiON, or other suitable materials.

Referring to FIG. 12F , dielectric layer 514 may be formed on dielectric layer 512 . Dielectric layer 514 may be patterned to form a plurality of openings, some of which vertically overlap light emitting features 510a. In some embodiments, dielectric layer 514 may include SiO ₂ , SiN, SiON, or other suitable materials. In some embodiments, dielectric layers 512 and 514 may have different etch selectivities to etchants such as HF, H3PO4, or other suitable etchants.

Referring to Figure 12G, a mask 516 may be formed to fill the opening vertically overlapping the light emitting feature 510a. An etching process may be performed to form the opening O1. The opening O1 can penetrate the dielectric layers 512 and 514 and the bottom layer 506 . In some embodiments, metallization layer 504 may be exposed from opening O1. In some embodiments, mask 516 may include, for example, a photoresist.

Referring to Figure 12H, mask 516 can be removed so that the opening vertically overlapping the light emitting feature 510a can be exposed. A conductive material may be formed to fill opening O1 and vertically overlap the opening of light emitting feature 510a. Accordingly, conductive features 518 and a pattern 520 may be formed. In some embodiments, conductive features 518 may laterally overlap light emitting features 510a. In some embodiments, conductive features 518 may laterally overlap pattern 520 . In some embodiments, conductive features 518 may include W, Al, Cu, Ti, Ta, alloys thereof, or other suitable materials. In some embodiments, pattern 520 may include W, Al, Cu, Ti, Ta, alloys thereof, or other suitable materials. In some embodiments, conductive features 518 may contact metallization layer 504 . In some embodiments, conductive features 518 may be electrically connected to metallization layer 504 .

Referring to Figure 12I, a base layer 522 and a photosensitive layer 524 may be formed to cover the conductive features 518 and patterns 520. Bottom layer 522 may include multiple dielectric layers, some of which may serve as an ARC layer. The photosensitive layer 524 may include, for example, a photoresist.

Referring to FIG. 12J, an etching process may be performed to remove portions of the bottom layer 522 and the photosensitive layer 524, thereby forming a groove vertically aligned with the pattern 520 and the light emitting feature 510a. In some embodiments, the exposed upper surface of the bottom layer 522 may serve as the bottom of the groove. In some embodiments, luminescent material 526 may fill the groove defined by bottom layer 522 and photosensitive layer 524 . In some embodiments, the luminescent material 526 may include metal ions of transition metals doped in the dielectric layer, such as SiO ₂ , SiN, SiON, or other suitable materials. The luminescent material 526 can fluoresce after the metal ions absorb light of a specific wavelength. In some embodiments, the fluorescent light emitted by luminescent material 526 may be at a different wavelength than that emitted by luminescent material 510 .

Referring to FIG. 12K, an etching process may be performed to remove part of the luminescent material 526 and the bottom layer 522, as well as the remaining photosensitive layer 524, thereby forming the luminescent feature 526a. In some embodiments, the etching process may include, for example, a dry etching process. In some embodiments, hair A portion of the lateral surface of light feature 526a may be exposed. In some embodiments, a portion of the light emitting feature 526a may be embedded into the underlying layer 522. In some embodiments, light emitting feature 526a may vertically overlap light emitting feature 510a. In some embodiments, light emitting features 526a may vertically overlap pattern 520. In some embodiments, light emitting features 526a may not laterally overlap conductive features 518.

Referring to FIG. 12L, dielectric layer 528 may be formed on dielectric layer 512. In some embodiments, dielectric layer 528 may include SiO ₂ , SiN, SiON, or other suitable materials. In some embodiments, dielectric layer 528 may cover the upper and side surfaces of light emitting feature 526a.

Referring to Figure 12M, a mask 530 may be formed to cover the dielectric layer 528. Mask 530 may include, for example, a photoresist.

Referring to FIG. 12N, an etching process may be performed to remove a portion of mask 530, thereby forming pattern 532. In some embodiments, pattern 532 may be an opening defined by mask 530 . In some embodiments, pattern 532 may vertically overlap light emitting features 526a. In some embodiments, pattern 532 may vertically overlap light emitting features 510a. In some embodiments, pattern 532 may vertically overlap pattern 520. In some embodiments, pattern 532 may be at least vertically aligned with pattern 520. Additionally, some openings defined by mask 530 may be vertically aligned with conductive features 518 and expose dielectric layer 528 . In some embodiments, patterns 520 and 532 may serve as stacked mark structures 540. In some embodiments, after pattern 532 is formed, an overlay error may be generated to determine a degree of misalignment between patterns 520 and 532 .

In some embodiments, the overlay measurement device may include a light source to emit a light ray. Light can be used to induce luminescent features 510a and/or 526a to fluoresce. The above-mentioned fluorescent light can help improve the contrast of patterns 520 and 532 in the optical image. Therefore, the overlay error between patterns 520 and 532 can be measured more accurately.

Referring to FIG. 12O, an etching process may be performed to form the opening O2. The opening O2 can penetrate the mask 530, the dielectric layer 528 and the bottom layer 522. In some embodiments, conductive features 518 may be exposed from opening O2. In some embodiments, a mask (not shown) may be formed to fill the opening vertically overlapping the light emitting feature 526a. After the opening O2 is formed, the mask can be removed.

Referring to FIG. 12P, a conductive material may be formed to fill opening O2 and pattern 532, thereby forming conductive features 534. Therefore, the semiconductor element structure 500a can be produced. In some embodiments, conductive features 534 may laterally overlap light emitting features 526a. In some embodiments, conductive features 534 may laterally overlap pattern 532 . In some embodiments, conductive features 534 may include W, Al, Cu, Ti, Ta, alloys thereof, or other suitable materials. In some embodiments, conductive features 534 may be in contact with conductive features 518 . In some embodiments, conductive feature 534 may be electrically connected to conductive feature 518 . In some embodiments, conductive features 534 may be vertically aligned with conductive features 518 .

FIG. 13 is a cross-sectional view illustrating a semiconductor device structure 500b according to some embodiments of the present disclosure. The semiconductor element structure 500b shown in FIG. 13 may be similar to the semiconductor element structure 500a shown in FIG. 12 except that the semiconductor element structure 500b may have a light emitting feature 510b instead of the light emitting feature 510a.

Light emitting feature 510b has projected area A1 on substrate 502 . Light emitting feature 526a has projected area A2 on substrate 502. In some embodiments, projection area A1 may not be equal to projection area A2. In some embodiments, projection area A1 may exceed projection area A2.

FIG. 14 is a cross-sectional view illustrating a semiconductor device structure 500c according to some embodiments of the present disclosure. The semiconductor element structure 500c shown in FIG. 14 may be similar to the semiconductor element structure 500a shown in FIG. Luminous properties 526b of property 526a.

In some embodiments, the projected area A2 of the light emitting feature 526b may exceed the projected area A1 of the light emitting feature 510a.

FIG. 15 is a cross-sectional view illustrating a semiconductor device structure 500d according to some embodiments of the present disclosure. The semiconductor element structure 500d shown in FIG. 15 may be similar to the semiconductor element structure 500a shown in FIG. 12, except that the semiconductor element structure 500d may have a light emitting characteristic 510c instead of the light emitting characteristic 510a.

In some embodiments, light emitting features 510c may be in direct contact with pattern 520. In some embodiments, light emitting features 510c may be in direct contact with the bottom surface of pattern 520.

The processes illustrated in FIGS. 11 and 12A to 12P may be implemented in the controller 390, or in a computing system that organizes the preparation of wafers by controlling a portion of all the manufacturing equipment in the facility. 16 is a diagram illustrating hardware of a semiconductor fabrication system 600 in various aspects of the present disclosure. The semiconductor manufacturing system 600 includes one or more processors 601 and code, that is, a storage medium 603 storing program code (ie, a set of executable instructions). Storage medium 603 may also be encoded with instructions for interfacing with manufacturing equipment that produces semiconductor equipment. The processor 601 is electrically connected to the storage medium 603 through the bus 605 . Processor 601 is also electrically coupled to input and output (I/O) interface 607 via bus 605 . The network interface 609 is also electrically connected to the processor 601 via the bus 605 . The network interface is connected to a network, so processor 601 and storage medium 603 can be connected to external components via network 380. The processor 601 is configured to execute computer code encoded in the storage medium 603 so that the semiconductor manufacturing system 600 can be used to perform some or all of the operations described in the method shown in FIG. 11 .

In some exemplary embodiments, processor 601 is, but is not limited to, a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit circuit (ASIC) and/or a suitable processing unit. Various circuits or units are within the scope of this disclosure.

In some exemplary embodiments, storage medium 603 is, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the storage medium 603 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a hard disk and/or an optical disk. . In one or more exemplary embodiments using optical discs, storage medium 603 also includes a compact disc-read-only memory (CD-ROM), a compact disc-read/write (CD-R/W), and/or a digital Versatile audio-visual disc (DVD).

In some exemplary embodiments, storage medium 603 stores computer code configured to cause semiconductor manufacturing system 600 to perform the method illustrated in FIG. 11 . In one or more exemplary embodiments, storage medium 603 also stores information required to perform the methods illustrated in Figure 11 as well as information generated during the performance of these methods and/or a method of performing the operations of the method illustrated in Figure 11 Group of executable instructions. In some exemplary embodiments, a user interface 610 , such as a graphical user interface (GUI), may be provided for the user to operate on the semiconductor manufacturing system 600 .

In some exemplary embodiments, storage medium 603 stores instructions for interfacing with external machines. This instruction enables the processor 601 to generate instructions readable by an external machine to effectively implement the method illustrated in Figure 11 during analysis.

Semiconductor manufacturing system 600 includes an input and output (I/O) interface 607. The I/O interface 607 is connected to external circuits. In some exemplary embodiments, I/O interface 607 may include, but is not limited to, a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for directing processing Device 601 conveys information and commands.

In some exemplary embodiments, I/O interface 607 may include a display, such as a cathode ray tube (CRT), liquid crystal display (LCD), speakers, etc. For example, a monitor displays information.

Semiconductor manufacturing system 600 may also include a network interface 609 coupled to processor 601. Network interface 609 allows semiconductor manufacturing system 600 to communicate with network 380 to which one or more other computer systems are connected. For example, the semiconductor manufacturing system 600 can be connected to the manufacturing equipment 320-1, . . . , and 320-N, 330, 340-1, . and overlay measurement equipment 360.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first conductive feature, a first light emitting feature, a first pattern, and a second pattern. The first luminescent feature is disposed on the substrate. The first pattern is disposed on the first luminescent feature. The second pattern is disposed on the first pattern. The first conductive feature at least laterally overlaps the first pattern. The first light emitting feature is configured to emit a light including a first wavelength. The first pattern has a first transmittance for the light of the first wavelength. The second pattern has a second transmittance for the light of the first wavelength. The first transmittance is different from the second transmittance.

Another aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first light-emitting feature, a stacked mark structure, and a first conductive feature. The first luminescent feature is disposed on the substrate. The first luminescent feature includes metal ions for emitting a fluorescent light including a first wavelength. The stacked mark structure is disposed on the first light emitting feature. The stacked mark structure is configured to absorb and/or reflect the fluorescent light emitted from the first luminescent feature. The first conductive feature at least laterally overlaps the stacked mark structure.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device structure Law. The preparation method includes: providing a substrate; forming a first luminescent feature on the substrate; forming a first pattern on the first luminescent feature; forming a first conductive feature laterally overlapping the first pattern; and A second pattern is formed on the first pattern, wherein the first luminescent feature is configured to emit a light including a first wavelength, and the first pattern has a first transmittance for the light including the first wavelength. , the second pattern has a second transmittance for the light including the first wavelength, and the first transmittance is different from the second transmittance.

Embodiments of the present disclosure provide a semiconductor device structure including light emitting features. The luminescent features can be configured to emit fluorescent light. Fluorescence can improve the contrast between the current layer and the pre-layer of the superimposed mark structure in the optical image. Therefore, the overlay error can be calculated more accurately based on the above optical images.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

500a: Semiconductor component structure 502: Base 504:Metalization layer 506: Bottom layer 510a: Luminous Characteristics 512: Dielectric layer 514: Dielectric layer 518: Conductive characteristics 520: Pattern 522: Bottom layer 526a: Luminous characteristics 528: Dielectric layer 530:Mask 532:Pattern 534: Conductive characteristics 540: mark structure X: direction Y: direction Z: direction

Claims (21)

A semiconductor element structure including: a base; a first luminescent feature disposed on the substrate; a first pattern disposed on the first luminescent feature; a first conductive feature disposed on the substrate and at least laterally overlapping the first pattern; and a second pattern disposed on the first pattern; wherein the first light emitting feature is configured to emit a light including a first wavelength, and the first pattern pair includes the first wavelength of light having a first transmittance, and the second pattern pair includes the first wavelength The light has a second transmittance, and the first transmittance is different from the second transmittance. The semiconductor device structure of claim 1, wherein the first pattern and the second pattern together serve as a stacked mark structure. The semiconductor element structure of claim 1, wherein the first transmittance is smaller than the second transmittance. The semiconductor device structure of claim 1, wherein the first pattern at least vertically overlaps the second pattern. The semiconductor device structure of claim 1, wherein the first conductive feature and the first light-emitting feature laterally overlap. The semiconductor device structure as described in claim 1 further includes: A second light emitting feature is disposed between the first pattern and the second pattern, wherein the second light emitting feature is configured to emit a light including a second wavelength that is different from the first wavelength. The semiconductor device structure of claim 6, wherein the second pattern has a third transmittance for the light including the second wavelength, and the third transmittance is different from the second transmittance. The semiconductor device structure of claim 6, wherein the first conductive feature does not laterally overlap the second light emitting feature. The semiconductor device structure of claim 6, wherein the first light-emitting feature and the second light-emitting feature vertically overlap. The semiconductor device structure of claim 6, wherein the first light-emitting feature has a first projection area on the substrate, the second light-emitting feature has a second projection area on the substrate, and the first projection area It is different from the second projection area. The semiconductor device structure as described in claim 6 further includes: A second conductive feature is vertically aligned with the first conductive feature, wherein the second conductive feature at least laterally overlaps the second pattern. The semiconductor device structure of claim 11, wherein the second conductive feature and the second light-emitting feature laterally overlap. A semiconductor element structure including: a base; A first luminescent feature is disposed on the substrate, wherein the first luminescent feature is used to emit a fluorescent light including a first wavelength; a stacked mark structure disposed on the first luminescent feature, wherein the stacked mark structure is configured to absorb or reflect the fluorescent light emitted from the first luminescent feature; and A first conductive feature at least laterally overlaps the stacked mark structure. The semiconductor device structure of claim 13, wherein the first luminescent feature includes metal ions. The semiconductor device structure of claim 13, wherein the stacked mark structure includes a first pattern and a second pattern on the first pattern, wherein the first pattern pair includes the phosphor of the first wavelength Having a first transmittance, the second pattern has a second transmittance for the fluorescent light including the first wavelength, and the first transmittance is different from the second transmittance. The semiconductor device structure of claim 15, wherein the first pattern at least laterally overlaps the first conductive feature. The semiconductor device structure as described in claim 15 further includes: A second luminescent feature is disposed between the first pattern and the second pattern, wherein the second luminescent feature is used to emit a fluorescent light that includes a second wavelength different from the first wavelength. The semiconductor device structure of claim 17, wherein the second pattern has a third transmittance for the fluorescent light including the second wavelength, and the third transmittance is different from the second transmittance. The semiconductor device structure of claim 17, wherein the first conductive feature does not laterally overlap the second light emitting feature. The semiconductor device structure of claim 17, wherein the first light-emitting feature and the second light-emitting feature vertically overlap. The semiconductor device structure as described in claim 17 further includes: A second conductive feature is vertically aligned with the first conductive feature, wherein the second conductive feature at least laterally overlaps the second light emitting feature.