JPH11307418A - Mask alignment mark and mask aligning method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of an alignment mark for obtaining a mask alignment correction position for minimizing the overlap deviation of an alignment layer to two layers to be aligned on a semiconductor substrate, and to easily calculate a correction value. SOLUTION: A mask alignment mark M is composed of a pattern 1 formed of a first layer to be aligned, pattern 2 formed of a second layer to be aligned, and resist pattern 3 for a third alignment layer formed between those patterns 1 and 2. Then, distances between the resist pattern 3 and both the patterns 1 and 2, for example, x5 and x6 are measured, and position correction is operated so that x5=x6. Thus, the overlap deviation can be minimized. Therefore, the correction is attained by one mark M so that the chip size can be reduced, and productivity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, which is used in a process of manufacturing a semiconductor device. The present invention relates to a mask alignment mark and a mask alignment method for minimizing the misalignment of a mask position by one mark when performing pattern mask alignment.

[0002]

2. Description of the Related Art A mask aligning device such as a stepper is generally used for aligning a mask in a semiconductor manufacturing process. However, when an upper layer pattern is aligned with a lower alignment mark, the lower alignment mark is always fixed. In many cases, mask alignment is performed while shifting in the direction. That is, the mask alignment apparatus often has a characteristic of causing an inherent systematic shift. In addition, since this kind of mask misalignment also occurs variously between mask aligning apparatuses, especially in a mass production site where a plurality of apparatuses are arranged and a mask having the same pattern is aligned, such a misalignment between the apparatuses is minimized. It is necessary to control.

For this reason, the usual mask alignment processing is
It is often performed in the following procedure. That is, a mask alignment process is performed on a trial basis for the semiconductor substrate for each lot ahead of one slice, a mask alignment shift of the slice is measured, and a mask alignment process of the remaining slices is performed so as to correct the shift. ing. Alternatively, a process is performed in which the misalignment of a previous lot, which has been processed by the same equipment in the same process, is measured, and the next lot is corrected based on the value.

A conventional technique for measuring the misalignment of the third layer with respect to two different layers to be aligned will be described below.

FIGS. 2 (a) and 2 (b) show the alignment,
That is, for two pattern layers (hereinafter referred to as alignment target layers) A and B to be mask-aligned,
FIGS. 4A and 4B are diagrams for explaining conventional marks M _L and M _R for measuring the position of an alignment layer C for performing alignment so that overlay deviation is minimized, wherein reference numeral 1 denotes an alignment target layer A formed on a semiconductor substrate 5. 2 is a thin film pattern formed on the alignment target layer B,
Denotes a resist pattern of the alignment layer C, and 4 denotes an interlayer insulating film.

FIG. 2A is a plan view, in which the left side is a mark M _L for measuring the position of the alignment layer C with respect to the alignment target layer A, and the right side is a mark for measuring the position of the alignment layer C relative to the alignment target layer B. M _R , two of which are arranged side by side on the semiconductor substrate 5. FIG. 2B shows each mark M _L ,
It is a sectional view along line b-b is the center portion of the M _R. Actually, the two cross sections in the figure are formed on one continuous semiconductor substrate 5, but are divided into two for convenience.

2 (a) and 2 (b), two marks M _L and M _R are respectively provided between the concave pattern 1 formed by the mask of the layer A to be aligned and the convex resist of the alignment layer C. The structure has a structure in which the pattern 3 is formed and a structure in which a convex resist pattern of the alignment layer C is formed between the convex patterns 2 formed by the mask of the layer B to be aligned.

In FIG. 2 (a), X, Y
When the axis is defined, the overlay deviation of the alignment layer C with respect to the alignment target layer A (RegXC-A, RegYC-
When A) measures the x1, x2, y1, y2 using the mark M _L,
It is represented by the following equation (Equation 1).

[0009]

## EQU00001 ## (RegXC-A, RegYC-A) = ((x1-x2) / 2, (y1-y2) / 2) where RegXC-A is the X-direction of the alignment layer C with respect to the alignment target layer A in the X direction. The misalignment, RegYC-A, indicates the misalignment of the alignment layer C with respect to the alignment target layer A in the Y direction.

Next, the misalignment of the alignment layer C with respect to the alignment target layer B (RegXC-B, RegYC
-B), when measured x3, x4, y3, y4 using the mark M _R, it is expressed by the following equation (2).

[0011]

(RegXC-B, RegYC-B) = ((x3-x4) / 2, (y3-y4) / 2) where RegXC-B is the X-direction of the alignment layer C with respect to the alignment target layer B in the X direction. The misalignment, RegYC-B, indicates the misalignment of the alignment layer C with respect to the alignment target layer B in the Y direction.

The correction values (X, X) of the position of the alignment layer C at which the overlay shift is minimized for both of the layers A and B to be aligned based on the respective overlay shifts
When Y) is obtained, the following equation (Equation 3) is obtained.

[0013]

(X, Y) = (− (RegXC-A + RegXC-B), − (RegYC
-A + RegYC-B)) = ((-X1 + X2-X3 + X4) / 2, (-Y1 + Y2-Y3 + Y4) / 2) Correct the above values and perform the mask alignment processing of the alignment layer C. By doing so, the alignment target layers A and B
Can be minimized.

[0014]

However, in the conventional alignment method in which the overlay is minimized, two types of marks M _L and M _R for overlay displacement measurement in the alignment layer C are required. There has been a problem that the mark area occupying the chip becomes large and the method of obtaining the correction value of the mask position that minimizes the misalignment is complicated.

The present invention solves the above-mentioned conventional problem. The present invention solves the above-mentioned problem by reducing the area by about one half by using one measurement mark, and calculating the correction value of the mask position of the alignment layer C from a simpler equation. An object of the present invention is to provide a mask alignment mark and a mask alignment method which can be obtained.

[0016]

In order to achieve the above object, a mask alignment mark according to the present invention comprises a pattern of an alignment layer C and two different alignment marks provided in close proximity to the pattern of the alignment layer C. It is composed of a pattern of the layer A and two different patterns of the to-be-aligned layer B provided close to the pattern of the alignment layer C.

Further, the mask alignment method of the present invention uses the mask alignment mark described above to determine a distance on the substrate between a pattern of the alignment layer C and two different patterns of the alignment target layer A on the substrate; The distance on the substrate between the pattern C and the two different patterns of the alignment target layer B is measured on the substrate, and from the measured value, the overlay deviation of the alignment layer C with respect to the two alignment target layers A and B is determined. , A correction value for a mask alignment position that minimizes the following is obtained, and the correction is performed in the next mask alignment.

By employing the above-described configuration of the mask alignment mark, the conventional mark has a total of eight patterns of the layers A and B to be aligned.
This has the advantage that the area occupied by the mark on the semiconductor substrate is reduced to about half. Where 1
In order to specify the amount of misalignment on a plane for one alignment layer, it is sufficient to measure two distances. Since the patterns of the alignment layers A and B are close to the pattern of the alignment layer C, the misalignment of the alignment layer C with respect to both the alignment layers A and B can be measured in the same manner as in the related art. it can.

With the mark and mask alignment method configured as described above, a mask alignment correction value can be immediately obtained from four distance measurement values, and the calculation is easier than in the past.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

FIG. 1A shows a mark M for masking the pattern of the alignment layer C with respect to the layers A and B to be aligned in an embodiment of the present invention.
FIG. 1B is a cross-sectional view taken along the line aa which is the center of the mark M in FIG. 1A.

1A and 1B, reference numeral 1 denotes a mark pattern formed of an alignment target layer A for forming an element isolation region formed on a semiconductor substrate 5, and a groove is formed on the surface of the semiconductor substrate 5. After that, the insulator is buried and formed, and on a plane, one line is arranged in each of the lines extending in the X direction and the Y direction perpendicular to the X direction. Reference numeral 2 denotes a mark pattern formed of the alignment target layer B formed by the gate electrode forming conductive film, and is arranged one by one in the X direction and the Y direction in the same manner as the mark pattern 1. Reference numeral 3 denotes a resist pattern formed of a resist including an alignment layer C for forming a contact hole. 4 is a semiconductor substrate 5
Is a region in which the circuit element is formed, and is a layer serving as an interlayer insulating film above the gate electrode.

A method for manufacturing the mask alignment mark M will be described.

First, as shown in FIG. 1, a concave mark pattern 1 is formed on the surface of the semiconductor substrate 5 using the mask of the layer A to be aligned. Next, by embedding the concave mark pattern 1 with an insulating film and flattening, an element isolation region is formed in the circuit formation region of the semiconductor substrate 5. Next, a conductive film formed on the surface of the semiconductor substrate 5 using the mask of the alignment target layer B, for example, a polysilicon or a metal silicide / polysilicon structure,
In the circuit region, a convex pattern 2 serving as a gate electrode is formed. Next, an interlayer insulating film 4 having a stacked structure of an oxide film containing no impurities and a BPSG film is deposited and planarized.

Thereafter, a resist pattern 3 of the alignment layer C is formed between the patterns 1 and 2 of the layers A and B to be aligned. By doing so, different patterns of the alignment layers A and B are formed on the left and right or upper and lower sides of the resist pattern 3.

In the above pattern, the distance between the center positions of the linear patterns 1 and 2 of the layers A and B to be aligned and the center position of the resist pattern of the alignment layer C is determined as a reference position.

Hereinafter, the mask alignment method will be described.

In FIG. 1 (a), as shown in FIG.
When the axis is defined, the alignment layer C with respect to the average position of the aligned layers A and B
The overlay misregistration (RegXC-AB, RegYC-AB) is calculated by using the mark M to measure x5, x6, y5, and y6.
It is represented by

[0029]

(RegXC-AB, RegYC-AB) = ((x5-x6) / 2, (y5-y6) / 2) where RegXC-AB is the average position of the alignment target layers A and B of the alignment layer C. RegYC-AB represents the misalignment of the alignment layer C in the Y direction with respect to the average position of the layers A and B to be aligned.

When the correction value (X, Y) of the position of the alignment layer C at which the overlay deviation is minimized with respect to both of the layers A and B to be aligned is obtained from the overlay deviation, the following equation (Equation 5) is obtained. )become that way.

[0031]

## EQU5 ## (X, Y) = (− RegXC-AB, −RegYC-AB) = ((− X5 + X6) / 2, (−Y5 + Y6) / 2) In short, in order to suppress overlay displacement (RegXC-
AB, RegYC-AB) is (0, 0), that is, x5 = x6, y
Correction is made so that 5 = y6.

The above values are obtained in advance for one slice of the semiconductor substrate for each lot, and the shift is corrected and the mask alignment processing of the remaining slices is performed. The overlay deviation can be minimized. This method can be used not only for correcting the misalignment unique to one mask aligning apparatus and the misalignment for each lot, but also for minimizing different misalignments between a plurality of mask aligning apparatuses. .

As shown in the present embodiment, by providing two different patterns 1 and 2 in the X direction and the Y direction in one measurement mark M,
The number of measured values is smaller than before. Conventionally, the distance to the resist pattern 3 is one type of the pattern 1 or 2 regardless of whether the two distances measured at one time in one direction are left or right or up and down. However, in the present embodiment, by providing the two patterns 1 and 2 on the mark M, it is possible to include both the distance to the pattern 1 or 2 as the two distances. Therefore, the correction amount can be easily calculated by a simpler equation. Further, since only one measurement mark M is used, the area occupied on the semiconductor substrate 5 is reduced to about half.

In this embodiment, a linear pattern is used as the alignment layers A and B, and a square pattern is used as the alignment layer C.
Other patterns may be used as long as two different distances from the alignment layer C can be measured for one alignment target layer.

[0035]

As described above, according to the present invention,
By using the overlay measurement pattern having the pattern of the third alignment layer between the patterns formed by the two layers to be aligned, the misalignment of the mask for the two layers can be reduced by one mark and by a smaller number. Can be easily calculated based on the measured values, and the chip area can be reduced and the productivity can be improved.

[Brief description of the drawings]

FIG. 1 shows a mask alignment mark portion on a semiconductor substrate for explaining an embodiment of the present invention;
(A) is a plan view, (b) is a sectional view taken along line aa in (a).

2 (a) is a plan view and FIG. 2 (b) is a cross-sectional view taken along the line bb in FIG. 2 (a), showing a mask alignment mark portion in a conventional semiconductor substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Pattern formed by layer A to be aligned 2 Pattern formed by layer B to be aligned 3 Pattern (resist pattern) formed by alignment layer C 4 Interlayer insulating film 5 Semiconductor substrate

Claims (3)

[Claims] A first mask layer and a second mask layer different from each other;
A mask alignment mark for superimposing a pattern of the third mask layer on a pattern formed by the first mask layer, the mask alignment mark being provided close to the alignment pattern of the third mask layer; It is characterized by comprising two different matching patterns belonging to a mask layer and two different matching patterns provided close to the matching pattern of the third mask layer and belonging to the second mask layer. Mask alignment mark. 2. The first mask layer and the second mask layer each having two different matching patterns both having a linear shape and extending substantially at right angles to each other. The three mask layers have a square matching pattern, two sides of which belong to the first mask layer, and the second mask pattern has a square shape.
A mask alignment mark that is arranged so as to be substantially parallel to two different alignment patterns belonging to the same mask layer. 3. A mask alignment method using a mask alignment mark transferred to a substrate according to claim 1, wherein each of two different alignment patterns belonging to the first mask layer and a third mask layer. The distance from the matching pattern, and 2 belonging to the second mask layer.
The distance between each of the different matching patterns and the matching pattern of the third mask layer is measured, and the first mask layer and the second mask layer are measured based on the measured value of the distance.
Of the pattern formed by the third mask layer
A correction value for a mask alignment position that minimizes a misalignment of the pattern of the mask layer, and performing a correction in a next mask alignment step based on the correction value.