JPH05121284A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To establish means for conducting accurate position alignment of mask and checkup of misaligument thereof quickly and easily in a manufacturing method of a semiconductor device having a plurality of masking steps. CONSTITUTION:A primary mask to be used in an initial masking step is provided with a plurality of patterns 9a to 9c for inspection (Fig. (a)) and thereby position alignment reference points for subsequent masking step are formed on a wafer surface of a semiconductor device, while masks to be used in subsequent masking steps are provided with patterns 10 to 12 for inspection which are in accord with at least one of the reference points and located at different positions from ones of other masks respectively. The masking steps (Figs. (b) to (d)) are executed with the corresponding position alignment reference points superposed on the patterns 10 to 12 for inspection respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a plurality of mask steps.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for higher frequency and higher functionality of semiconductor devices, and along with this, the miniaturization and high integration of mask patterns during exposure and the like have been advanced (industrial research See "Latest LSI Process Technology" published by the Society).

Generally, a semiconductor device is manufactured by a method of arranging p-type and n-type semiconductor layers in a pattern by diffusion or ion implantation, and further arranging a protective oxide film and a metal for electrodes in a pattern on the surface thereof. Has been done.

FIG. 2 is a diagram showing an example of a cross-sectional structure diagram of a basic npn transistor. In this example, an n ⁻ layer 2 is formed by epitaxial growth on an n ⁺ type silicon substrate 1 and boron is diffused on the surface thereof. And the like to form the p-type diffusion layer 3 and the p-type diffusion layer 3 has an n-type diffusion layer 4 formed on the surface thereof by phosphorus diffusion or the like.
O ₂ ) 5 is formed, and finally the electrode metal 6 is provided in the opening of the protective oxide film 5.

Even in the case of a semiconductor device having such a simple structure, a mask process, that is, an exposure process and an etching process associated therewith, are subjected to a boron diffusion, a phosphorus diffusion window opening, and a protective oxide film 5 at the time of manufacturing the semiconductor device. At least four times are required for opening the contact hole and forming the pattern of the electrode metal 6.

Conventionally, the positional relationship of the mask patterns in each process is accurately overlapped each time.

[0007]

However, with the miniaturization and high integration of the mask pattern, the alignment of the mask pattern becomes difficult, and most of the manufacturing defects occur in each mask process.

In order to prevent this, it is sufficient to inspect all the wafers after each masking process, but this is not generally done in a mass production factory because it takes a long time. Therefore, once a defect occurs, the period until the cause is investigated,
There was a problem that the recurrence of defects could not be prevented.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which can perform accurate alignment of mask patterns in a plurality of mask processes and inspection thereof quickly and easily. To aim.

[0010]

According to the present invention, in a method of manufacturing a semiconductor device having a plurality of mask steps, a primary mask used in the first mask step is provided with at least the same number of inspection patterns as the number of subsequent mask steps. At the same time, each of the masks used in the subsequent mask process is provided with an inspection pattern at the same position as at least one of the inspection patterns of the primary mask, and the alignment reference point is set on the wafer surface of the semiconductor device by the inspection pattern of the primary mask. After the formation, the mask process from the next time onward is carried out while making the inspection pattern of each mask coincide with the alignment reference point on the wafer surface.

[0011]

First, an alignment reference point having the same shape as the inspection pattern is formed on the wafer surface of the semiconductor device by the primary mask. In the subsequent mask process, accurate positioning can be performed by matching the inspection pattern of each mask with the corresponding alignment reference point. Therefore, regardless of the shape of the mask pattern, the alignment is easy, and when the alignment is defective, the discrepancy between the two can be visually confirmed, so not only during the process but also after the process is completed. Inspection of alignment accuracy becomes easy.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1D are process explanatory views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. For example, a mask for obtaining an npn-type transistor having the structure shown in FIG. The steps are shown in sequence. Therefore, each semiconductor layer, protective oxide film, and electrode metal will be described with the same reference numerals as in FIG.

Further, in FIGS. 1A and 1B, the drawings on the left side are the pattern diagrams provided on the mask of each process, and the drawings on the right side are the specific exposure, etching, and
The cross-sectional structural diagram of the wafer after carrying out the diffusion is shown.

First, FIG. 1A will be described. n ⁺
After the n ⁻ layer 2 is formed by epitaxial growth on the p-type silicon substrate 1, a mask pattern 8a having the shape shown in the figure is used as a primary mask used when the p-type diffusion layer 3 is formed. Inspection pattern 9a
9c are provided at a predetermined interval. The number of the inspection patterns 9a to 9c is three in this embodiment, but at least the number of mask processes after the next time is arranged.

In this way, the patterns having the same shape as the patterns 7a and 9a to 9c are printed on the surface of the silicon wafer.

In FIG. 1B, in addition to the mask pattern 8b for forming the n-type diffusion layer 4, the alignment pattern 7b.
The inspection pattern 10 is provided on the mask. The alignment pattern 7b is at the same position as the alignment pattern 7a of FIG. 1A, and the inspection pattern 10 is shown in FIG.
At least one of the inspection patterns 9a to 9c, for example, the same position as the first inspection pattern 9a. Then, among the figures formed on the wafer surface in the step of FIG. 1A, one corresponding to the alignment pattern 7a and the first inspection pattern 9a, and the alignment pattern 7b and the inspection pattern 10 in this step. Are overlapped with each other, and exposure, etching, and diffusion processing are performed.

Similarly, in the process shown in FIG. 1C in which a window is formed in the protective oxide film 5, thereafter, in addition to the mask pattern 8c, the alignment pattern 7a and the second inspection pattern 9b shown in FIG. The mask 7 is provided with an alignment pattern 7c and an inspection pattern 11 at positions corresponding to
1 (d) for forming the mask pattern 8d
In addition to the above, the alignment pattern 7a and the third alignment pattern 9c of FIG.
d and the inspection pattern 12 are provided on the mask. Then, when performing each mask process, each pattern 7c,
7d, 11 and 12 are formed on the wafer surface, respectively.
The patterns corresponding to the patterns 7a, 9b, and 9c in (a) are overlaid.

As described above, in this embodiment, the primary mask is used to form the alignment reference points having the same shape as the inspection patterns 9a to 9c on the wafer surface of the semiconductor device. Therefore, in the subsequent mask process, Accurate positioning is possible by making the inspection patterns 10 to 12 of each mask coincide with the corresponding alignment reference points.
Therefore, regardless of the shape of the mask pattern, alignment of the mask is easy, and when the alignment is defective, the mismatch between the two can be visually confirmed, so that the alignment accuracy inspection after the process is completed quickly. And it can be done easily.

Since the mask inspection patterns 10 to 12 used in the subsequent steps are arranged differently from each other, the alignment accuracy of a specific mask step is inspected even after the completion of all steps. It is possible to quickly investigate the cause when a defect occurs.

In this embodiment, the case where the alignment patterns 7a to 7d and the inspection patterns 9a to 9c and 10 to 12 are separately provided has been described, but the inspection pattern is used as a mask for each process. It is also possible to provide them at two or more locations with a predetermined interval, respectively, and also use this as a pattern for alignment. With such a method, it is possible to always perform alignment by a new alignment pattern for each mask process, and the overlay accuracy is further improved.

[0022]

As described above, according to the present invention,
A plurality of inspection patterns are provided on the primary mask used in the first mask process, thereby forming alignment reference points for the subsequent mask process on the wafer surface of the semiconductor device, and for each mask used in the next mask process and thereafter. Since it corresponds to at least one of the reference points, and an inspection pattern is provided at a position different from other masks, each mask step is performed while superposing the alignment reference point and each inspection pattern. There is an effect that the overlay accuracy in a specific mask process can be easily and quickly inspected not only immediately after each mask process but also after the completion of all processes. As a result, the productivity and yield rate of the semiconductor device are significantly improved as compared with the conventional manufacturing method.

Further, a mask used in each process is provided with inspection patterns at two or more places at predetermined intervals, and this mask is also used as an alignment pattern, so that a new alignment pattern is always provided for each mask process. Positioning can be performed by using, and the accuracy of overlaying can be further improved.

By selecting the shape of the inspection pattern so that the pattern can be easily recognized by the computer, the computer can automatically determine the quality (accuracy) of the pattern overlay in each mask process. it can.

[Brief description of drawings]

FIG. 1 is a mask process explanatory diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) is a pattern diagram of a primary mask and a resulting wafer cross-sectional structure diagram;
(B) to (d) are a pattern diagram of the mask after the next time and a wafer cross-sectional structure diagram obtained as a result.

FIG. 2 is a cross-sectional structure diagram of a general npn-type transistor.

[Explanation of symbols]

7a to 7d ... Alignment pattern, 8a to 8d ... Mask pattern, 9a to 9c, 10-12 ... Inspection pattern.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 19, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Detailed explanation of the invention

[Correction method] Change

[Correction content]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a plurality of mask steps.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for higher frequency and higher functionality of semiconductor devices, and along with this, the miniaturization and high integration of mask patterns during exposure and the like have been advanced (industrial research See "Latest LSI Process Technology" published by the Society).

Generally, a semiconductor device is manufactured by a method of arranging p-type and n-type semiconductor layers in a pattern by diffusion or ion implantation, and further arranging a protective oxide film and a metal for electrodes in a pattern on the surface thereof. Has been done.

FIG. 2 is a diagram showing an example of a cross-sectional structure diagram of a basic npn transistor. In this example, an n ⁻ layer 2 is formed by epitaxial growth on an n ⁺ type silicon substrate 1 and boron is diffused on the surface thereof. And the like to form the p-type diffusion layer 3 and the p-type diffusion layer 3 has an n-type diffusion layer 4 formed on the surface thereof by phosphorus diffusion or the like.
O ₂ ) 5 is formed, and finally the electrode metal 6 is provided in the opening of the protective oxide film 5.

Even in the case of a semiconductor device having such a simple structure, a mask process, that is, an exposure process and an etching process associated therewith, are subjected to a boron diffusion, a phosphorus diffusion window opening, and a protective oxide film 5 at the time of manufacturing the semiconductor device. At least four times are required for opening the contact hole and forming the pattern of the electrode metal 6.

Conventionally, the positional relationship of the mask patterns in each process is accurately overlapped each time.

[0007]

However, with the miniaturization and high integration of the mask pattern, the alignment of the mask pattern becomes difficult, and most of the manufacturing defects occur in each mask process.

In order to prevent this, it is sufficient to inspect all the wafers after each masking process, but this is not generally done in a mass production factory because it takes a long time. Therefore, once a defect occurs, the period until the cause is investigated,
There was a problem that the recurrence of defects could not be prevented.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which can perform accurate alignment of mask patterns in a plurality of mask processes and inspection thereof quickly and easily. To aim.

[0010]

According to the present invention, in a method of manufacturing a semiconductor device having a plurality of mask steps, a primary mask used in the first mask step is provided with at least the same number of inspection patterns as the number of subsequent mask steps. At the same time, each of the masks used in the subsequent mask process is provided with an inspection pattern at the same position as at least one of the inspection patterns of the primary mask, and the alignment reference point is set on the wafer surface of the semiconductor device by the inspection pattern of the primary mask. After the formation, the mask process from the next time onward is carried out while making the inspection pattern of each mask coincide with the alignment reference point on the wafer surface.

[0011]

First, an alignment reference point having the same shape as the inspection pattern is formed on the wafer surface of the semiconductor device by the primary mask. In the subsequent mask process, accurate positioning can be performed by matching the inspection pattern of each mask with the corresponding alignment reference point. Therefore, regardless of the shape of the mask pattern, the alignment is easy, and when the alignment is defective, the discrepancy between the two can be visually confirmed, so not only during the process but also after the process is completed. Inspection of alignment accuracy becomes easy.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1D are process explanatory views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. For example, a mask for obtaining an npn-type transistor having the structure shown in FIG. The steps are shown in sequence. Therefore, each semiconductor layer, protective oxide film, and electrode metal will be described with the same reference numerals as in FIG.

Further, in FIGS. 1A and 1B, the drawings on the left side are the pattern diagrams provided on the mask of each process, and the drawings on the right side are the specific exposure, etching, and
The cross-sectional structural diagram of the wafer after carrying out the diffusion is shown.

First, FIG. 1A will be described. n ⁺
After the n ⁻ layer 2 is formed by epitaxial growth on the p-type silicon substrate 1, a mask pattern 8a having the shape shown in the figure is used as a primary mask used when the p-type diffusion layer 3 is formed. Inspection pattern 9a
9c are provided at a predetermined interval. The number of the inspection patterns 9a to 9c is three in this embodiment, but at least the number of mask processes after the next time is arranged.

In this way, the patterns having the same shape as the patterns 7a and 9a to 9c are printed on the surface of the silicon wafer.

In FIG. 1B, in addition to the mask pattern 8b for forming the n-type diffusion layer 4, the alignment pattern 7b.
The inspection pattern 10 is provided on the mask. The alignment pattern 7b is at the same position as the alignment pattern 7a of FIG. 1A, and the inspection pattern 10 is shown in FIG.
At least one of the inspection patterns 9a to 9c, for example, the same position as the first inspection pattern 9a. Then, among the figures formed on the wafer surface in the step of FIG. 1A, one corresponding to the alignment pattern 7a and the first inspection pattern 9a, and the alignment pattern 7b and the inspection pattern 10 in this step. Are overlapped with each other, and exposure, etching, and diffusion processing are performed.

Similarly, in the process shown in FIG. 1C in which a window is formed in the protective oxide film 5, thereafter, in addition to the mask pattern 8c, the alignment pattern 7a and the second inspection pattern 9b shown in FIG. The mask 7 is provided with an alignment pattern 7c and an inspection pattern 11 at positions corresponding to
1 (d) for forming the mask pattern 8d
In addition to the above, the alignment pattern 7a and the third alignment pattern 9c of FIG.
d and the inspection pattern 12 are provided on the mask. Then, when performing each mask process, each pattern 7c,
7d, 11 and 12 are formed on the wafer surface, respectively.
The patterns corresponding to the patterns 7a, 9b, and 9c in (a) are overlaid.

As described above, in this embodiment, the primary mask is used to form the alignment reference points having the same shape as the inspection patterns 9a to 9c on the wafer surface of the semiconductor device. Therefore, in the subsequent mask process, Accurate positioning is possible by making the inspection patterns 10 to 12 of each mask coincide with the corresponding alignment reference points.
Therefore, regardless of the shape of the mask pattern, alignment of the mask is easy, and when the alignment is defective, the mismatch between the two can be visually confirmed, so that the alignment accuracy inspection after the process is completed quickly. And it can be done easily.

Since the mask inspection patterns 10 to 12 used in the subsequent steps are arranged differently from each other, the alignment accuracy of a specific mask step is inspected even after the completion of all steps. It is possible to quickly investigate the cause when a defect occurs.

In this embodiment, the case where the alignment patterns 7a to 7d and the inspection patterns 9a to 9c and 10 to 12 are separately provided has been described, but the inspection pattern is used as a mask for each process. It is also possible to provide them at two or more locations with a predetermined interval, respectively, and also use this as a pattern for alignment. With such a method, it is possible to always perform alignment by a new alignment pattern for each mask process, and the overlay accuracy is further improved.

[0022]

As described above, according to the present invention,
A plurality of inspection patterns are provided on the primary mask used in the first mask process, thereby forming alignment reference points for the subsequent mask process on the wafer surface of the semiconductor device, and for each mask used in the next mask process and thereafter. Since it corresponds to at least one of the reference points, and an inspection pattern is provided at a position different from other masks, each mask step is performed while superposing the alignment reference point and each inspection pattern. There is an effect that the overlay accuracy in a specific mask process can be easily and quickly inspected not only immediately after each mask process but also after the completion of all processes. As a result, the productivity and yield rate of the semiconductor device are significantly improved as compared with the conventional manufacturing method.

Further, a mask used in each process is provided with inspection patterns at two or more places at predetermined intervals, and this mask is also used as an alignment pattern, so that a new alignment pattern is always provided for each mask process. Positioning can be performed by using, and the accuracy of overlaying can be further improved.

By selecting the shape of the inspection pattern so that the pattern can be easily recognized by the computer, the computer can automatically determine the quality (accuracy) of the pattern overlay in each mask process. it can.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a plurality of mask steps, wherein the primary mask used in the first mask step is provided with at least the same number of inspection patterns as the number of subsequent mask steps, and in the subsequent mask step. Each of the masks to be used is provided with an inspection pattern at the same position as at least one of the inspection patterns of the primary mask, and after the alignment reference points are formed on the wafer surface of the semiconductor device with the inspection pattern of the primary mask, the masks for the next and subsequent masks A method of manufacturing a semiconductor device, characterized in that the steps are carried out while matching the inspection pattern of each mask with the alignment reference point on the wafer surface. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the inspection patterns provided on the mask after the next step are arranged at different positions.