JPS5828736B2 - 平坦な薄膜の形成方法 - Google Patents

平坦な薄膜の形成方法

Info

Publication number
JPS5828736B2
JPS5828736B2 JP52031202A JP3120277A JPS5828736B2 JP S5828736 B2 JPS5828736 B2 JP S5828736B2 JP 52031202 A JP52031202 A JP 52031202A JP 3120277 A JP3120277 A JP 3120277A JP S5828736 B2 JPS5828736 B2 JP S5828736B2
Authority
JP
Japan
Prior art keywords
layer
thin film
metal
removable material
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52031202A
Other languages
English (en)
Japanese (ja)
Other versions
JPS52132688A (en
Inventor
ジヤノス・ハーベス
ジヨセフ・スキンナー・ローガン
ジヨン・エス・レチヤトン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS52132688A publication Critical patent/JPS52132688A/ja
Publication of JPS5828736B2 publication Critical patent/JPS5828736B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H10W20/01
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10P76/202
    • H10W20/058
    • H10W20/063
    • H10W20/40
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143Masks therefor
    • H10P14/6329
    • H10P14/68
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/951Lift-off
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24777Edge feature

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP52031202A 1976-04-29 1977-03-23 平坦な薄膜の形成方法 Expired JPS5828736B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/681,380 US4035276A (en) 1976-04-29 1976-04-29 Making coplanar layers of thin films

Publications (2)

Publication Number Publication Date
JPS52132688A JPS52132688A (en) 1977-11-07
JPS5828736B2 true JPS5828736B2 (ja) 1983-06-17

Family

ID=24735037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52031202A Expired JPS5828736B2 (ja) 1976-04-29 1977-03-23 平坦な薄膜の形成方法

Country Status (6)

Country Link
US (2) US4035276A (cg-RX-API-DMAC10.html)
JP (1) JPS5828736B2 (cg-RX-API-DMAC10.html)
CA (1) CA1062658A (cg-RX-API-DMAC10.html)
DE (1) DE2709986C2 (cg-RX-API-DMAC10.html)
FR (1) FR2349956A1 (cg-RX-API-DMAC10.html)
IT (1) IT1115626B (cg-RX-API-DMAC10.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176830U (ja) * 1984-04-29 1985-11-22 有限会社 小森谷製作所 ねじ込シヤンク
JPS62137629U (cg-RX-API-DMAC10.html) * 1986-02-19 1987-08-29

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2350697A1 (fr) * 1976-05-06 1977-12-02 Cii Structure perfectionnee de circuits multicouches
DE2800635C2 (de) * 1978-01-07 1985-03-14 Fa. Leonhard Kurz, 8510 Fürth Prägefolie, insbesondere Heißprägefolie
JPS5513962A (en) * 1978-07-17 1980-01-31 Nec Corp Method of processing very fine electrode
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
US4181755A (en) * 1978-11-21 1980-01-01 Rca Corporation Thin film pattern generation by an inverse self-lifting technique
US4389481A (en) * 1980-06-02 1983-06-21 Xerox Corporation Method of making planar thin film transistors, transistor arrays
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4337132A (en) * 1980-11-14 1982-06-29 Rockwell International Corporation Ion etching process with minimized redeposition
JPS57176746A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit and manufacture thereof
US4564997A (en) * 1981-04-21 1986-01-21 Nippon-Telegraph And Telephone Public Corporation Semiconductor device and manufacturing process thereof
US4389294A (en) * 1981-06-30 1983-06-21 International Business Machines Corporation Method for avoiding residue on a vertical walled mesa
US4396458A (en) * 1981-12-21 1983-08-02 International Business Machines Corporation Method for forming planar metal/insulator structures
US4703392A (en) * 1982-07-06 1987-10-27 General Electric Company Microstrip line and method for fabrication
US4600663A (en) * 1982-07-06 1986-07-15 General Electric Company Microstrip line
US4461071A (en) * 1982-08-23 1984-07-24 Xerox Corporation Photolithographic process for fabricating thin film transistors
US4562091A (en) * 1982-12-23 1985-12-31 International Business Machines Corporation Use of plasma polymerized orgaosilicon films in fabrication of lift-off masks
US4493855A (en) * 1982-12-23 1985-01-15 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
US4606931A (en) * 1983-06-27 1986-08-19 International Business Machines Corporation Lift-off masking method
CA1247464A (en) * 1985-05-13 1988-12-28 Hiroaki Nakamura Method for forming a planarized thin film
US4731340A (en) * 1987-02-24 1988-03-15 Rockwell International Corporation Dual lift-off self aligning process for making heterojunction bipolar transistors
US4917963A (en) * 1988-10-28 1990-04-17 Andus Corporation Graded composition primer layer
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
TW408420B (en) * 1998-08-14 2000-10-11 Mosel Vitelic Inc A method to measure if the connecting via in the metal wiring layer is aligned correctly
US6524937B1 (en) * 2000-08-23 2003-02-25 Tyco Electronics Corp. Selective T-gate process
US6768204B1 (en) * 2001-04-05 2004-07-27 Advanced Micro Devices, Inc. Self-aligned conductive plugs in a semiconductor device
US6503847B2 (en) * 2001-04-26 2003-01-07 Institute Of Microelectronics Room temperature wafer-to-wafer bonding by polydimethylsiloxane
DE10222609B4 (de) * 2002-04-15 2008-07-10 Schott Ag Verfahren zur Herstellung strukturierter Schichten auf Substraten und verfahrensgemäß beschichtetes Substrat
AU2003247287A1 (en) * 2002-05-23 2003-12-12 Schott Ag Glass material for use at high frequencies
US7205228B2 (en) * 2003-06-03 2007-04-17 Applied Materials, Inc. Selective metal encapsulation schemes
US20060009038A1 (en) * 2004-07-12 2006-01-12 International Business Machines Corporation Processing for overcoming extreme topography
KR101431466B1 (ko) * 2008-07-30 2014-08-22 삼성디스플레이 주식회사 유기 발광 소자의 제조 방법
CN105097433B (zh) * 2014-05-14 2018-05-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3442012A (en) * 1967-08-03 1969-05-06 Teledyne Inc Method of forming a flip-chip integrated circuit
US3661761A (en) * 1969-06-02 1972-05-09 Ibm Rf sputtering apparatus for promoting resputtering of film during deposition
GB1286737A (en) * 1969-10-15 1972-08-23 Itt Multilevel conductive systems
FR2119930B1 (cg-RX-API-DMAC10.html) * 1970-12-31 1974-08-19 Ibm
JPS4830888A (cg-RX-API-DMAC10.html) * 1971-08-25 1973-04-23
JPS4960870A (cg-RX-API-DMAC10.html) * 1972-10-16 1974-06-13
US3844831A (en) * 1972-10-27 1974-10-29 Ibm Forming a compact multilevel interconnection metallurgy system for semi-conductor devices
US3868723A (en) * 1973-06-29 1975-02-25 Ibm Integrated circuit structure accommodating via holes
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
JPS5128780A (en) * 1974-09-04 1976-03-11 Hitachi Ltd Haisenso no keiseihoho
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176830U (ja) * 1984-04-29 1985-11-22 有限会社 小森谷製作所 ねじ込シヤンク
JPS62137629U (cg-RX-API-DMAC10.html) * 1986-02-19 1987-08-29

Also Published As

Publication number Publication date
IT1115626B (it) 1986-02-03
US4090006A (en) 1978-05-16
FR2349956A1 (fr) 1977-11-25
DE2709986C2 (de) 1986-01-30
FR2349956B1 (cg-RX-API-DMAC10.html) 1980-01-11
JPS52132688A (en) 1977-11-07
US4035276A (en) 1977-07-12
DE2709986A1 (de) 1977-11-17
CA1062658A (en) 1979-09-18

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