JPS58220293A - 記憶装置 - Google Patents

記憶装置

Info

Publication number
JPS58220293A
JPS58220293A JP57102619A JP10261982A JPS58220293A JP S58220293 A JPS58220293 A JP S58220293A JP 57102619 A JP57102619 A JP 57102619A JP 10261982 A JP10261982 A JP 10261982A JP S58220293 A JPS58220293 A JP S58220293A
Authority
JP
Japan
Prior art keywords
line
bit line
data bit
gate
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57102619A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0235398B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Katsuhiko Nakagawa
克彦 中川
Takao Kusano
隆夫 草野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57102619A priority Critical patent/JPS58220293A/ja
Priority to DE8383303470T priority patent/DE3378143D1/de
Priority to EP83303470A priority patent/EP0098080B1/en
Publication of JPS58220293A publication Critical patent/JPS58220293A/ja
Priority to US07/166,788 priority patent/US4780849A/en
Publication of JPH0235398B2 publication Critical patent/JPH0235398B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP57102619A 1982-06-15 1982-06-15 記憶装置 Granted JPS58220293A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57102619A JPS58220293A (ja) 1982-06-15 1982-06-15 記憶装置
DE8383303470T DE3378143D1 (en) 1982-06-15 1983-06-15 Dynamic memory with a reduced number of signal lines
EP83303470A EP0098080B1 (en) 1982-06-15 1983-06-15 Dynamic memory with a reduced number of signal lines
US07/166,788 US4780849A (en) 1982-06-15 1988-03-02 Information handling apparatus having memory means

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57102619A JPS58220293A (ja) 1982-06-15 1982-06-15 記憶装置

Publications (2)

Publication Number Publication Date
JPS58220293A true JPS58220293A (ja) 1983-12-21
JPH0235398B2 JPH0235398B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-08-09

Family

ID=14332260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57102619A Granted JPS58220293A (ja) 1982-06-15 1982-06-15 記憶装置

Country Status (4)

Country Link
US (1) US4780849A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0098080B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS58220293A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3378143D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6196595A (ja) * 1984-10-17 1986-05-15 Toshiba Corp 半導体記憶装置
JPS63894A (ja) * 1986-06-20 1988-01-05 Hitachi Ltd メモリ
JPH01129376A (ja) * 1987-11-16 1989-05-22 Oki Electric Ind Co Ltd Ｉｃカード
US5594698A (en) * 1993-03-17 1997-01-14 Zycad Corporation Random access memory (RAM) based configurable arrays
JP2013191265A (ja) * 2012-02-17 2013-09-26 Semiconductor Energy Lab Co Ltd 記憶装置、記憶装置の駆動方法、及び該記憶装置を備えた電子機器

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路
JP2587229B2 (ja) * 1987-03-11 1997-03-05 日本テキサス・インスツルメンツ株式会社 アービタ回路
US5007022A (en) * 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
EP1323168A2 (en) 2000-08-30 2003-07-02 Micron Technology, Inc. Semiconductor memory having dual port cell supporting hidden refresh
US6903964B2 (en) * 2002-06-28 2005-06-07 Freescale Semiconductor, Inc. MRAM architecture with electrically isolated read and write circuitry
JP2004054547A (ja) * 2002-07-19 2004-02-19 Nec Electronics Corp バスインタフェース回路及びレシーバ回路
US7187610B1 (en) * 2003-07-17 2007-03-06 Actel Corporation Flash/dynamic random access memory field programmable gate array
US6891769B2 (en) * 2003-07-17 2005-05-10 Actel Corporation Flash/dynamic random access memory field programmable gate array

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651472A (en) * 1970-03-04 1972-03-21 Honeywell Inc Multistate flip-flop element including a local memory for use in constructing a data processing system
DE2364253A1 (de) * 1973-12-22 1975-06-26 Olympia Werke Ag Schaltungsanordnung fuer mikroprogrammierte geraete der datenverarbeitung
US3919694A (en) * 1974-05-10 1975-11-11 Hewlett Packard Co Circulating shift register memory having editing and subroutining capability
NL7713707A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met variabele ingang en vaste uitgang.
JPS56147203A (en) * 1980-04-17 1981-11-16 Toshiba Mach Co Ltd Sequence control device equipped with row cyclic operation part
US4456965A (en) * 1980-10-14 1984-06-26 Texas Instruments Incorporated Data processing system having multiple buses
NL8103477A (nl) * 1981-07-23 1983-02-16 Philips Nv Kantoorsysteem met eindstations, een dataverwerkende processor en hulpapparaten en een doorschakelinrichting voor het verzorgen van massaal datatransport tussen de hulpapparaten.

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6196595A (ja) * 1984-10-17 1986-05-15 Toshiba Corp 半導体記憶装置
JPS63894A (ja) * 1986-06-20 1988-01-05 Hitachi Ltd メモリ
JPH01129376A (ja) * 1987-11-16 1989-05-22 Oki Electric Ind Co Ltd Ｉｃカード
US5594698A (en) * 1993-03-17 1997-01-14 Zycad Corporation Random access memory (RAM) based configurable arrays
JP2013191265A (ja) * 2012-02-17 2013-09-26 Semiconductor Energy Lab Co Ltd 記憶装置、記憶装置の駆動方法、及び該記憶装置を備えた電子機器
JP2017174491A (ja) * 2012-02-17 2017-09-28 株式会社半導体エネルギー研究所 記憶装置

Also Published As

Publication number Publication date
EP0098080B1 (en) 1988-09-28
EP0098080A3 (en) 1985-05-15
JPH0235398B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-08-09
US4780849A (en) 1988-10-25
DE3378143D1 (en) 1988-11-03
EP0098080A2 (en) 1984-01-11

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