US4780849A - Information handling apparatus having memory means - Google Patents

Information handling apparatus having memory means Download PDF

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Publication number
US4780849A
US4780849A US07/166,788 US16678888A US4780849A US 4780849 A US4780849 A US 4780849A US 16678888 A US16678888 A US 16678888A US 4780849 A US4780849 A US 4780849A
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Prior art keywords
bit line
digital signal
memory cells
output terminal
memory
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US07/166,788
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English (en)
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Katsuhiko Nakagawa
Takao Kusano
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NEC Corp
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NEC Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Definitions

  • the present invention relates to an information-handling apparatus having memory means, and more particularly, to a data processor, such as a microcomputer including a digital IC chip on which data processing circuitry and memory circuitry are integrated and coupled to each other by signal lines called a bus; or a computer system comprising one or more processor chips, memory chips, peripheral control chips, interface chips, and peripheral devices, which are all coupled by a bus cable.
  • a data processor such as a microcomputer including a digital IC chip on which data processing circuitry and memory circuitry are integrated and coupled to each other by signal lines called a bus; or a computer system comprising one or more processor chips, memory chips, peripheral control chips, interface chips, and peripheral devices, which are all coupled by a bus cable.
  • an area on the digital IC chip occupied by signal lines (buses) provided for transferring information is predominantly large as compared with an area of active elements on that IC.
  • the proportion occupied by signal lines is at least 50% or more of the chip area, and in some case is 70 to 80%.
  • the number of required signal lines is increased further. Since the signal lines must be formed so as not to cause undesired interference with active elements and other signal lines, the more active elements and the signal lines there are, the less freedom there is in bus layout design. Thus, layout of a circuit pattern on an IC chip becomes difficult.
  • Another object of the present invention is to provide an information-handling apparatus having a digital IC which is suitable for high density integration and in which design and layout of a circuit pattern is easy.
  • Still another object of the present invention is to provide an information processing system in which bus coupling for information transfer is easy.
  • Yet another object of the present invention is to provide an information-handling apparatus or system that is suitable for transferring different kinds of information through a small number of signal lines, while omitting a roundabout route.
  • a further object of the present invention is to provide a data processor in which a data transferring section and a data receiving section are coupled to each other via circuitry having an information storing function and a direct information transfer function.
  • a still further object of the present invention is to provide a data processor suitable for use in a serial bus coupling system, such as a pipeline processor.
  • the data processor is always provided with memory means for storing information, such as read only type memories and random access type memories. These memory means have been coupled to many signal lines, but used only for storing information.
  • the present invention has the feature that the memory means is used as a direct path of data transfer.
  • the information handling apparatus having memory means comprises an information input portion, an information output portion, a first signal line for operatively coupling the information input and output portions with each other, an information storing circuit including therein a portion of the first signal line and coupled to a second signal line, a first control circuit for reading information out of the information storing circuit and for transferring the information to the information output portion through the second signal line, and a second control circuit for directly transferring information from the information input portion to the information output portion through the first signal line.
  • a third control circuit for writing information applied from the information input portion into the random access type memory may be provided in addition to the above-mentioned structure.
  • the present invention utilizes a part of a memory means as a data line for directly transferring information from an input portion to an output portion without destroying the memory function.
  • the external second signal line serves as a reading line or a writing line of information for the memory circuit by the first control circuit or the third control circuit, and moreover the first signal line maintains the condition where the information input portion and the information output portion are electrically coupled to the same voltage level (potential) by the second control circuit.
  • the first signal line serves as a conventional bus through which information is directly transferred from the input portion to the output portion.
  • information fed to the output portion can be in itself transmitted to the output portion through the first signal line within the memory means.
  • the input portion and the output portion are maintained at the same potential, information can be transferred in both directions. In other words, it is possible to transfer information from the output portion towards the input portion.
  • information can be transferred through the interior of the memory means without providing a separate roundabout signal line. Consequently, a data receiving circuit can be coupled to the data transferring circuit using only a memory means of the present invention.
  • the omission of signal lines and/or reduction of in the number of contacts to signal lines is made possible. Therefore, the density of signal lines can be greatly reduced. Also, the shortcomings associated with multi-layer wirings and cross-over wirings can be prevented.
  • the freedom of wiring is enhanced, circuit pattern layout becomes very simple. Furthermore, in an information processing system, the number of cables and the number of terminals coupling the cables can be greatly reduced, and so, there is an advantage that system construction becomes very simple. As a result, an improved integrated circuit with enhanced performance can be achieved.
  • the memory circuit of the invention can be used as a bidirectional bus, a greater freedom in circuit pattern design, particularly in regard to the positioning of circuit patterns, is achieved.
  • FIG. 1 is a block diagram of a known memory device, particularly of a dynamic RAM
  • FIG. 2 is a circuit diagram showing the details of one memory cell of the dynamic RAM shown in FIG. 1;
  • FIG. 3 is a system block diagram of a known information processor arrangement including the RAM shown in FIG. 1;
  • FIG. 4 is a circuit diagram of a dynamic RAM cell constructed in accordance with the teaching of the present invention.
  • FIG. 5 is a system block diagram of an information processor having the dynamic RAM shown in FIG. 4 included therein;
  • FIG. 6 is a circuit diagram of another preferred embodiment of the present invention as applied to a dynamic RAM
  • FIG. 7 is a block diagram of a prior art processing circuit having a delay circuit therein;
  • FIG. 8 is a block diagram of still another preferred embodiment of the present invention as applied to a delay circuit section
  • FIG. 9 is a circuit block diagram of the embodiment of the invention shown in FIG. 8 with the dynamic RAM outputs connected to a multiplexer;
  • FIG. 10 is a block diagram of a prior art processing circuit including an ALU.
  • FIG. 11 is a block diagram of a still further preferred embodiment of the present invention as applied to a processing circuit including an ALU;
  • FIG. 12 is a circuit diagram of still another preferred embodiment of the present invention.
  • FIG. 13 is a timing chart for the circuit of FIG. 12.
  • FIG. 1 A block diagram of a prior art RAM that can be accessed by an 8-bit address is shown in FIG. 1.
  • a row address AD X and a column address AD y are respectively applied to a row address decoder 1 and a column address decoder 2, and these decoders generate signals for selecting a designated cell in a memory cell matrix 6.
  • outputs to the row address decoder 1 are coupled to the respective word lines 7, while outputs of the column address decoder 2 are coupled to the respective bit lines 8.
  • the column decoder 2 is coupled to the memory cell matrix 6 via an input/output circuit 4 and a refresh circuit 5. Data to be written into a designated memory cell is fed through a terminal 9, and data stored in designated memory cell is derived through the same terminal 9.
  • the terminal 9 is used as an input/output data terminal.
  • An input/output control circuit 3 controls the refresh circuit 5, the input/output circuit 4 and the column address decoder 2 in response to a read/write control signal R/W and a precharge control signal PC.
  • FIG. 2 is a circuit diagram of a dynamic RAM in which each memory cell is formed of three transistors. This figure illustrates one memory cell in the dynamic RAM.
  • a dash line block 20 shows one memory cell, in which a data write transistor Q 1 , a data storage transistor Q 2 and a data read transistor Q 3 are arranged in the illustrated manner.
  • Written data are stored in a capacitor C between the gate and the source of the storage transistor Q 2 .
  • input data are fed through an input/output terminal 21 and transferred to the memory cell 20 through a write bit line 22.
  • the data on the write bit line 22 is written into the transistor Q 2 .
  • a signal line 28 is a precharge line for precharging the bit lines 22 and 23 via transistors Q 4 and Q 5 .
  • the input/output common terminal 9 is coupled to the write bit line (also called digit line) 22 and read bit line so as to form a closed loop, and these lines are used as an exclusive route for writing and/or reading data to and from a memory cell. Accordingly, data to be transferred without passing through the RAM must be transmitted through a signal line which bypasses the RAM region, so as not to interfere with the RAM operation. As a result, a shortcoming occurs in that the number and lengths of signal lines are both increased and hence the region where active elements are formed is greatly restricted. In addition, since a large number of signal lines must be wired, there is the disadvantage that the design of the circuit pattern becomes difficult, while the freedom to select circuit pattern layouts is greatly restricted.
  • a dynamic RAM having a refresh control transistor is well known.
  • the RAM of this type has a refresh control transistor 202, shown by dotted line in FIG. 2. This transistor is inserted between node 200 and node 201 instead of a signal line 203.
  • the refresh control transistor 202 is turned on in response to a refresh control signal 204 which is periodically generated by a refresh counter at a predetermined refresh cycle.
  • transistor 202 is conducting the read bit line is coupled to the write bit line 22 via an inverter 27 and the refresh control transistor 202. At this point, a refresh operation is executed according to a read control signal and write control signal.
  • the RAM of this type is also used as only a memory device, and not, in any sense, are the teachings of this invention incorporated into this prior art RAM. Further, even if the write bit line 22 is decoupled from the read bit line 23 before and after a refresh operation, the write bit line 22 can not be used as a bus, because an information input portion and an information output portion are common to terminal 21.
  • this RAM is coupled to a transmitter circuit and to a receiver circuit as shown in FIG. 3.
  • lines 34 and 35 are formed such that a transmitter circuit 30 may be coupled to the input terminal 21 of the RAM (shown in FIG.
  • Reference number 33 designates an address line for the RAM 32.
  • the transmitter circuit 30 can write data into the RAM 32 through the signal line 34, and also can transmit data stored within the RAM32 to the receiver circuit 31 through the signal line 35.
  • a separate signal line 36 must be provided so as not to interfere with the RAM32.
  • the signal line 36 becomes quite long in order to avoid any interference with the RAM32.
  • FIG. 4 is a circuit diagram of an essential part of an improved memory according to one preferred embodiment of the present invention.
  • a dash-line block 40 indicates one memory cell, which includes a write transistor Q 41 , a data hold transistor Q 42 and a read transistor Q 43 , and in which a datum is stored in a capacitor C 44 between the gate and the source of the transistor Q 42 .
  • Write operation of a datum is effected when a write address has been fed to a write word line 404, and read operation of a datum is effected when a read address has been fed to a read word line 405.
  • Refresh operation is effected by reading a datum onto a read bit line 49, inverting this datum by means of an inverter 46 via a signal line 45 and then transferring the invented datum to a write bit line 48.
  • both the write transistor Q 41 and the read transistor Q 43 become active.
  • a transistor Q 47 serving as a switching gate transistor is provided in the refresh path. Upon refresh, this transistor Q 47 is conducting, and hence the read bit line 49 and the write bit line 48 are electrically coupled via the inverter 46. Although only one memory cell is shown in FIG. 4, other memory cells could be coupled to the bit lines and the word lines.
  • Write data is fed through an input terminal 400 and are stored into the cell 40 through the write bit line 48.
  • the stored data is read through the read bit line 49.
  • the write bit line 48 and the read bit line 49 are respectively provided with independent output terminals 401 and 402. More particularly, provision is made such that the write bit line 48 may be coupled to a first output terminal 401, while the read bit line 49 may be coupled to a second output terminal 402.
  • the first and second output terminals 401 and 402 are coupled to receiving terminals of a processor circuit 403 by using signal lines 404 and 405. It is to be noted that a precharge circuit and a sense amplifier circuit that are required for a dynamic memory are omitted from the illustration for the sake of brevity.
  • the illustrated RAM of FIG. 4 has a specific output portion including the first output terminal 401 which is coupled to the write bit line 48 and coupled to the input terminal 400 and is separated from the input terminal 400.
  • input data applied from the input terminal 400 can be directly transferred to the first output terminal 401 by using the write bit line 48 when it is not being used during a refresh operation.
  • the switching gate transistor Q 47 becomes conductive in response to a refresh control signal which is generated from a control circuit 410 and is transferred through a signal line 406.
  • the control circuit 410 operates in such a manner that the switching gate transistor Q 47 is held in a non-conductive state during the period when the write bit line 48 is used as a bus for directly transferring data from the input terminal 400 to the output terminal 404.
  • the switching transistor Q 47 may be turned ON by the control circuit 410 to electrically couple the read bit line 49 and the write bit line 48 with each other. Then, data is fed through the input terminal 400 and stored in the transistor Q 42 , and the stored data is transferred via the read bit line 49 to the second output terminal 402. Further, a refresh operation is also executed at every predetermined refresh cycle. While the direct data transfer is executed, the switching transistor Q 47 is turned OFF by the control circuit 410. The write bit line 48 and the read bit line 49 are electrically disconnected from each other. Accordingly, under this condition, the write terminal 400 and the first output terminal 401 assume the same potential.
  • the write bit line 48 is decoupled from the refresh circuit, and it is ready to be used as a signal bus line. Under this condition, date input through the input terminal 400 is in itself transferred to the first output terminal 401 through the write bit line 48. Accordingly, the write bit line 48 within the memory can be used as an independent signal line without requiring a separate signal line outside of the memory.
  • the write bit line can be used as one signal line That is the write bit line 48 is available as a bus.
  • a circuit equivalent to that shown in FIG. 3 can be constructed with a pattern layout as shown in FIG. 5.
  • a transmitter circuit 50 is coupled to a receiver circuit 51 only through a RAM 52, and thereby the following operations can be executed.
  • the transmitter circuit 50 can transmit data stored within the RAM 52 to the receiver circuit 51 via a data bus 405 by transferring an address through an address bus 53 to the RAM 52, and also it can write data in the RAM 52 via a data bus 54 coupled to the input terminal 400.
  • the transmitter circuit 50 can directly feed data to the receiver circuit 51 by transmitting data through the interior of the RAM 52 and the bus 404 coupled to the first output terminal 401 without requiring a separate bus 36 shown in FIG. 3. Accordingly, bus forming becomes very simple as a compared to the prior art shown in FIG. 3, and hence substantial freedom is attained in pattern layout.
  • FIG. 6 is a block diagram of another preferred embodiment of the present invention. This figure shows eight memory cell blocks 60-67, and each cell includes three transistors as shown within the block 63 (corresponding to the block 40 of FIG. 4).
  • the respective cells are coupled in common to a write bit line 600 (corresponding to the line 48 of FIG. 4) and a read bit line 601 (corresponding the line 49 of FIG. 4).
  • the read bit line 601 is coupled to the write bit line 600 via an inverter 602 (corresponding to the inverter 46 in FIG. 4) and a transistor 603 (corresponding to the transistor Q 47 of FIG. 4) for refresh control.
  • the write bit line 600 is coupled to a data input terminal 607 (corresponding the terminal 400 of FIG.
  • a data output terminal 605 (corresponding the terminal 401 of FIG. 4) via a switching transistor 604.
  • This output terminal 605 may be coupled to a processor circuit (not shown).
  • the read bit line 601 is coupled to another output terminal 609 (corresponding to the terminal 402 in FIG. 4) via an inverter 608.
  • Write transistors in the respective cells are coupled to write word lines 610-613 (610 corresponds to the line 404 of FIG. 4), and read transistors are coupled to read word lines 614-617 (614 corresponds to the line 405 of FIG. 4), respectively.
  • the write word lines are coupled to output ends of NOR gates 618-621, respectively.
  • each NOR gate To one input of each NOR gate is fed decoded signals 622-625 of a write address, while the other input is adapted to receive a write inhibit signal 626.
  • the switching transistor 604 is controlled by a control signal fed through a gate signal line 627.
  • This gate signal line 627 and a refresh signal line 628 (corresponding to 406 of FIG. 4) are coupled to a control circuit 630.
  • the write bit line 600 can be coupled to the output terminal 605 by turning ON the transistor 604.
  • the data input terminal 607 and the output terminal 605 assume the same potential, and hence the write bit line 600 can be used as an independent signal line.
  • the write bit line 600 can be used as a bidirectional signal line. In other words, it is also possible to input data from the output terminal 605 and to take out the data from the input terminal 607.
  • the times when the write bit line 600 can be used as a signal line is limited to times other than the time for the memory refresh cycle. Since refresh of the memory is made possible by turning ON the refresh control transistor 603, the transistor 604 can be controlled by an inverted refresh control signal.
  • the transistor 603 is turned OFF and the write word lines 610-613 are also made inactive.
  • the write word lines 610-613 are inactive unless write addresses 622-625 are fed to these write word lines 610-613, a write address register (not shown) is normally constructed in such manner that undesired signals cause it to be maintained in its set state even during a period other than the write cycle.
  • NOR gates 618-621 adapted to receive an inhibit signal via a signal line 626 so as to inhibit the write addresses from being transferred to the respective word lines. If such provision is made, the write transistors in the respective memory cells are all made inactive simultaneously, and the write bit line is freed from the memory cells.
  • the output of the inverter 608 could be coupled to the write bit line 600.
  • the output terminal 609 can be omitted, and the data stored in the cells can be taken out either through the input terminal 607 or through the output terminal 605.
  • FIG. 7 shows a circuit pattern in which data from an input end 70 is either directly transferred through a signal line 73 or its is transferred after having been delayed by a delay circuit 71 to a multiplexer 72 where it is switched.
  • the signal line 73 had to be provided outside of the delay circuit 71 whose input portion is coupled to a signal line 74 and whose output portion is coupled to a signal line 75.
  • the equivalent circuit is achieved by the circuit shown in FIG. 8,
  • the input end 70 is coupled to the memory 52 shown in FIG. 8 via the signal line 74.
  • the output of the multiplexer 72 corresponds to the output of the memory 52, which is transferred through the signal line 404.
  • Data required to be delayed can be temporarily stored in the cell of the memory 52 and can be taken out of the memory through the writs bit line 45 of FIG. 4 after the delay time passes. Data which need not be delayed can be directly transferred through the write bit line 48 to the signal line 404. Therefore, no signal line 73 and no multiplexer 72 are required. However, if both a delayed data and a no delayed data are simultaneously to be outputted, the second out terminal 402 and the signal line 405 would be required.
  • FIG. 9 a circuit could be constructed as shown in FIG. 9.
  • a temporary memory circuit is formed of transistors Q 41 , Q 42 and Q 43 .
  • Reference numeral 400 designates an input end
  • numeral 91 designates an output end.
  • the transistor Q 47 is turned OFF by a control signal 406 which is sent from the timing control circuit 410, while a transistor 99 within a multiplexer 903 is turned ON by a control signal 902 to thereby couple a bit line 48 to the output end 91.
  • a transistor 100 is turned ON by a control signal 901 to couple a bit line 49 to the output end 91.
  • a control signal 901 it is only additionally required to turn ON the transistor Q 47 for refreshing the data via an inverter 46.
  • a new inverter (not shown) is required to invert data in the cell.
  • the refresh transistor Q 47 has to be turned ON by a control signal 406 generated by the control circuit 410.
  • the transistor 99 is also turned ON in response to the control signal 902.
  • a data bus 101 to an ALU 102 via a RAM 52 according to the present invention.
  • the data to be latched in the latch 103 is temporarily stored in the cell or the RAM 52, while the data which later comes in through the data bus 101 is passed through the RAM 52 and are output through a signal line 404. At this moment, the previously stored data is simultaneously output through a signal line 405.
  • FIG. 12 is a more detailed embodiment of FIG. 4.
  • the illustrated circuit includes a memory cell 40, a refresh circuit (a transistor Q 47 and an inverter 46), a write bit line 48, a read bit line 49 and a control circuit 410.
  • a data input terminal 400 is coupled to the write bit line 48 via a switching gate 120, a NOR gate 121 and a transistor 122.
  • the NOR gate 121 receives a timing pulse ⁇ 1, through an inverter 123.
  • Transistors 124 and 125 are precharge transistors for the write bit line 48 and the read bit line 49, respectively, and operate in response to two kinds of clock pulses ⁇ 2 and ⁇ 1 .
  • the control circuit 410 receives the clock pulses ⁇ 1 and ⁇ 2 , a refresh signal (REF) and a write signal (WRITE) and outputs a control signal 406 and a write control signal (WR).
  • the control signal 406 is applied to the refresh transistor Q 47 and to the switching gate 120 through an inverter 126.
  • FIG. 13 is a timing chart illustrating the operation of the circuit of FIG. 12.
  • the write signal WR is applied to the transistor Q 41 .
  • the refresh signal is applied to the transistor Q 47 as the control signal 406 in synchronism with the clock pulse ⁇ 2 during a refresh cycle.
  • the switching gate 120 is turned OFF, and any input datum is inhibited.
  • the circuit is set in a read cycle mode.
  • the input terminal 400 is coupled to the output terminal 401, and therefore, the write bit line 49 can be used as a bus line through which data is directly transferred.
  • the present invention provides the advantage of freeing a bit line from a memory circuit, where upon the bit line can be used as a discrete bus. Accordingly, a number of buses used in an IC or the like can be greatly reduced, and freedom in regards to pattern layout can be enhanced. It is to be noted that while an example in which a write bit line is used as a bus has been described in connection to the aforementioned embodiments, if a switching transistor is provided in a read bit line, obviously this read bit line can be used as a bus. Furthermore, the present invention could be applied not only to an IC but also to a computer system.
  • a ROM bit line can be used as a bus in a manner similar to the present invention.
  • the present invention is equally applicable to RAM's of the types other than the three-transistor dynamic memory such as, for example, a two transistor-type memory, a one-transistor memory and the like, and to a static type memory.

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US07/166,788 1982-06-15 1988-03-02 Information handling apparatus having memory means Expired - Fee Related US4780849A (en)

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JP57-102619 1982-06-15
JP57102619A JPS58220293A (ja) 1982-06-15 1982-06-15 記憶装置

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US4956820A (en) * 1987-03-11 1990-09-11 Texas Instruments Incorporated Arbiter circuit for establishing priority control of read, write and refresh operations with respect to memory array
US5007022A (en) * 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
US6438016B1 (en) 2000-08-30 2002-08-20 Micron Technology, Inc. Semiconductor memory having dual port cell supporting hidden refresh
US20040001358A1 (en) * 2002-06-28 2004-01-01 Nahas Joseph J. MRAM architecture with electrically isolated read and write circuitry
US20040013021A1 (en) * 2002-07-19 2004-01-22 Hiroyuki Takahashi Bus interface circuit and receiver circuit
US20050190626A1 (en) * 2003-07-17 2005-09-01 Actel Corporation Flash/dynamic random access memory field programmable gate array
US20070104009A1 (en) * 2003-07-17 2007-05-10 Actel Corporation Flash/dynamic random access memory field programmable gate array
JP2013191265A (ja) * 2012-02-17 2013-09-26 Semiconductor Energy Lab Co Ltd 記憶装置、記憶装置の駆動方法、及び該記憶装置を備えた電子機器

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JPS6196595A (ja) * 1984-10-17 1986-05-15 Toshiba Corp 半導体記憶装置
JPS63894A (ja) * 1986-06-20 1988-01-05 Hitachi Ltd メモリ
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路
JP2578139B2 (ja) * 1987-11-16 1997-02-05 沖電気工業株式会社 Ｉｃカード
WO1994022142A1 (en) * 1993-03-17 1994-09-29 Zycad Corporation Random access memory (ram) based configurable arrays

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Also Published As

Publication number Publication date
EP0098080B1 (en) 1988-09-28
EP0098080A3 (en) 1985-05-15
JPH0235398B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-08-09
JPS58220293A (ja) 1983-12-21
DE3378143D1 (en) 1988-11-03
EP0098080A2 (en) 1984-01-11

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