JPS58175665U - Printed board - Google Patents
Printed boardInfo
- Publication number
- JPS58175665U JPS58175665U JP7209382U JP7209382U JPS58175665U JP S58175665 U JPS58175665 U JP S58175665U JP 7209382 U JP7209382 U JP 7209382U JP 7209382 U JP7209382 U JP 7209382U JP S58175665 U JPS58175665 U JP S58175665U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- chip
- electronic component
- shaped electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図はプリント基板の部分平面図及びＴ１
−Ｔ□線断面図、第３図及び第４図は第１図のプリント
基板のチップ部品実装時の部分平面図及びＴ２−Ｔ２線
断面図、第５図及び第６図と第７図及び第８図は本考案
によるプリント基板の一実施例を示す各状態での部分平
面図及びＴ３−Ｔ３線とＴ、−Ｔ、線断面図である。
６・・・・・・チップ形電子部品、７・・・・・・絶縁
基板、８・・・・・・導電パターン、９ａ、９ｂ・・・
・・・半田レジスト膜、ｍ・・・・・・半田付は予定部
分、ｎ・・・・・・仮固定予定部分。Figures 1 and 2 are partial plan views of the printed circuit board and T1
-T□ line sectional view, Figures 3 and 4 are partial plan views of the printed circuit board in Figure 1 when chip components are mounted, T2-T2 line sectional views, Figures 5 and 6, Figures 7 and 4. FIG. 8 is a partial plan view of an embodiment of the printed circuit board according to the present invention in various states and a sectional view taken along the line T3-T3 and T, -T. 6... Chip type electronic component, 7... Insulating substrate, 8... Conductive pattern, 9a, 9b...
...Solder resist film, m...Soldering is planned for area, n......Temporary fixation is planned for area.
Claims (1)
るプリント基板であって、前記チップ形電子部品の半田
付は予定部分を除く前記プリント基板全チップ形電子部
品の仮固定予定部分のみを２回塗りで他より厚目にして
、接着性のある半田レジスト膜を塗着形成したふとを特
徴とするプリント基板。A printed circuit board on which a chip-shaped electronic component is soldered to a predetermined position of a conductive land, wherein the chip-shaped electronic component is soldered twice to only the portion of the printed circuit board where the chip-shaped electronic component is temporarily fixed except for the planned portion. A printed circuit board that is coated thicker than others and features an adhesive solder resist film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7209382U JPS58175665U (en) | 1982-05-17 | 1982-05-17 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7209382U JPS58175665U (en) | 1982-05-17 | 1982-05-17 | Printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58175665U true JPS58175665U (en) | 1983-11-24 |
Family
ID=30081671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7209382U Pending JPS58175665U (en) | 1982-05-17 | 1982-05-17 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58175665U (en) |
-
1982
- 1982-05-17 JP JP7209382U patent/JPS58175665U/en active Pending
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