JPS58161426A - デイジタルｐｌｌ回路のル−プフイルタ - Google Patents

デイジタルｐｌｌ回路のル−プフイルタ

Info

Publication number
JPS58161426A
JPS58161426A JP57042268A JP4226882A JPS58161426A JP S58161426 A JPS58161426 A JP S58161426A JP 57042268 A JP57042268 A JP 57042268A JP 4226882 A JP4226882 A JP 4226882A JP S58161426 A JPS58161426 A JP S58161426A
Authority
JP
Japan
Prior art keywords
signal
loop filter
phase
pll circuit
digital pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57042268A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0429256B2 (enrdf_load_stackoverflow
Inventor
Hisahiro Koga
古賀　寿浩
Yoshifumi Toda
戸田　善文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57042268A priority Critical patent/JPS58161426A/ja
Publication of JPS58161426A publication Critical patent/JPS58161426A/ja
Publication of JPH0429256B2 publication Critical patent/JPH0429256B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
JP57042268A 1982-03-17 1982-03-17 デイジタルｐｌｌ回路のル−プフイルタ Granted JPS58161426A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57042268A JPS58161426A (ja) 1982-03-17 1982-03-17 デイジタルｐｌｌ回路のル−プフイルタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57042268A JPS58161426A (ja) 1982-03-17 1982-03-17 デイジタルｐｌｌ回路のル−プフイルタ

Publications (2)

Publication Number Publication Date
JPS58161426A true JPS58161426A (ja) 1983-09-26
JPH0429256B2 JPH0429256B2 (enrdf_load_stackoverflow) 1992-05-18

Family

ID=12631286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57042268A Granted JPS58161426A (ja) 1982-03-17 1982-03-17 デイジタルｐｌｌ回路のル−プフイルタ

Country Status (1)

Country Link
JP (1) JPS58161426A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60244124A (ja) * 1984-03-19 1985-12-04 ウエスタン、デジタル、コ−ポレ−シヨン デジタル・フエ−ズロツクル−プ装置
US6157690A (en) * 1997-03-26 2000-12-05 Nec Corporation Digital PLL circuit
DE10129783C1 (de) * 2001-06-20 2003-01-02 Infineon Technologies Ag Verzögerungsregelkreis

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49119503A (enrdf_load_stackoverflow) * 1973-03-15 1974-11-15
JPS56748A (en) * 1979-06-15 1981-01-07 Fujitsu Ltd Phase control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49119503A (enrdf_load_stackoverflow) * 1973-03-15 1974-11-15
JPS56748A (en) * 1979-06-15 1981-01-07 Fujitsu Ltd Phase control circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60244124A (ja) * 1984-03-19 1985-12-04 ウエスタン、デジタル、コ−ポレ−シヨン デジタル・フエ−ズロツクル−プ装置
US6157690A (en) * 1997-03-26 2000-12-05 Nec Corporation Digital PLL circuit
DE10129783C1 (de) * 2001-06-20 2003-01-02 Infineon Technologies Ag Verzögerungsregelkreis
US6586978B2 (en) 2001-06-20 2003-07-01 Infineon Technologies Ag Delay locked loop

Also Published As

Publication number Publication date
JPH0429256B2 (enrdf_load_stackoverflow) 1992-05-18

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