JPS58161426A - Loop filter of digital pll circuit - Google Patents

Abstract

PURPOSE:To obtain a loop filter for a digital PLL circuit with a simple circuit constitution, by adopting a so-called continuous count system which outputs discrimination output only when N-set of consecutive ''1s'' or ''0s'' in discriminating a phase comparison signal. CONSTITUTION:A phase comparison signal A outputted from a phase comparator 1 is given to a shift register 21 in synchronizing with a clock signal CK. Further, AND gates 22 and 23 monitors at all times that outputs Q1, Q2...QN of a shift register 21 are all ''1'' or outputs Q1', Q2'...QN' are all zero, and when the conditions are satisfied, the AND gate 22 or 23 outputs a set signal S or a reset signal R. A flip-flop 24 generates a phase control signal B with the set signal S or the reset signal R. That is, the loop filter is the continuous count system which discriminates the phase control signal as ''1'' or ''0'', when the phase comparison signal A is ''1'' or ''0'' consecutively for N-set.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a loop filter for a digital PLLDOM.

Background of the Invention In recent years, with the advancement of digital technology, digital PLL (phase-locked loop) circuits have come into practical use.Furthermore, this digital PLIL circuit frame naturally maintains high performance. A device with a simplified circuit configuration is desired.

(3) Prior art and problems An example of the configuration of a digital PT and +L circuit is shown in FIG. This PLL circuit has one phase comparator 1. Loop filter 2. It consists of a variable oscillator 3.

Here, a variable oscillator is an oscillator whose frequency or phase changes according to a control signal applied from the outside.

An example is a voltage controlled oscillator.

The phase comparator 1 compares the phases of the input signal and the output signal, and generates a phase comparison signal A1 of, for example, 11' if the output signal is ahead of the input, and @0'' if the output signal is behind the input.Loop filter 2
The number of occurrences of @1" or r1'"O" of this signal A is counted for a certain period t, and depending on the counting result, it is 11" or @0".
A phase control signal BQ is generated. The variable oscillator 3 uses this signal BK to control the phase of the output signal so that the phase of the output signal matches the phase of the input signal. In this way, even if noise is mixed into the input signal, a stable output signal synchronized with the input signal that is less affected by this noise is generated.

Fig. 2 shows an example of a conventional loop filter.
Reset signal RLt for sampling every bit
14 is an N-bit counter that counts the number of @1m+ included in the signal AK; 16 is an N-bit counter that counts the number of 10" included in the signal M; the counters 14 and 15 are reset; It is reset by the signal RL. 17 is set when counter 1 counts @1'?N or more during the sampling period of M bits, and counter 16 counts @O'QN during the sampling period of M bits. This is an RS flip-flop which is reset when the count is greater than or equal to 1, and thereby generates a signal Bf that controls the phase of the output signal of the variable oscillator 3 shown in FIG.

The values of the number of bits N and V of the counters 13, 14 and 15 are set to satisfy the relationship N(M(2N). For example, if M==xL2.N, set to 8, then t.

The signal At-12 bits are sampled every 12 bits.
If there are eight or more @1'' or @0'' in the bits, the result of one phase comparison is determined to be mlIT or @0'', respectively.

A conventional loop filter frame, as shown in this example, 1
Even if they are not continuous in 2 bits, if you count a total of 8 or more "1m" or ""O" tubes, it will be as fine as possible even if the continuity is disturbed instantaneously by @1" or mixed in. Although it is based on the idea of using a judgment tube, it has the drawback that the single circuit configuration is complicated.

(4) Object of the Invention An object of the present invention is to provide a loop filter for a digital PLL circuit with a simple circuit configuration.

(5) Structure of the Invention The idea of the present invention is that when determining a phase comparison signal in a digital PLL loop filter, 72N
We focused on the fact that there is virtually no difference in phase control even if we use the so-called continuous counting method, which counts the number of 1's or 0's and makes a judgment only when the time is right.

The loop filter according to the above-mentioned continuous counting method is constructed as all shift registers centered.

(6) Examples of the invention Embodiments of the present invention will be described in detail below.

@3 Figure is an embodiment of the loop filter according to the present invention.

In the figure, 11" or '"O# V of the phase comparison signal 21 is shown.
, 8-stage shift register for counting, 22 AIJD that generates a set signal S when N consecutive Fx signals A are "1"
Gate 23 is an AND gate that generates a reset signal R when N consecutive signals are @0, and 24 is an R-8 fringe that generates all phase control signals B with the set signal or reset signal R. .

The phase comparison signal A output from the phase comparator 1 shown in FIG.
to go into. On the other hand, AND gates 22 and 23 output the outputs Q, $Q, of the shift register 21.

...QN is all @1" or output Qll-Q!...Q
It constantly monitors whether N is all "0", and when the above condition is satisfied, the AND gate 22 or ij2'slj: set signal 124 generates a phase control signal Bt-.

As shown in the above embodiments, it is conceivable that the loop filter according to the present invention is qualitatively larger than the case where N consecutive phase comparison signals A are based on the "1" formula.

However, in the normal case, the magnitude of pull/pull is small, around the value of N dlo, and in relation to the speed of the input signal and the transient characteristics of noise, it is virtually impossible to It has been experimentally shown that there is almost no difference in terms of performance.(Ma) Effects of the Invention According to the present invention, as will be explained in detail.

It becomes possible to easily modify the circuit configuration of the loop filter without substantially impairing the phase control characteristics of the Pl and L circuits, and the number of parts used can be reduced.

[Brief explanation of drawings]

Claims (1)

[Claims] In a digital PLL circuit that is completely equipped with a phase comparator, a loop filter, and a variable oscillator, a signal indicating the phase comparison result 1 outputted from the phase comparator (an Al-based shift register that counts serially, and a continuous N of the shift register) is used. A circuit that generates a set signal or a reset signal tube when all bit outputs become @1'' or @0'', and a phase tM of the variable oscillator according to the set signal or reset signal.
Signal to be generated (B)
- Characteristic loop filter of digital PLL circuit.