JP3783323B2 - Digital PLL circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital PLL circuit used in a data transmission system using digital signal processing.
[0002]
[Prior art]
In the conventional digital PLL, as shown in FIGS. 10 to 12, the reference clock CLK_refAnd output clock CLK_outControl is performed so as to match the phases.
This will be described in detail with reference to the drawings.
[0003]
FIG. 10 shows a configuration of a conventional example. In this conventional example, the reference clock CLK_refRising detector 1 for detecting the rising edge and outputting rising detection signal S, and output clock CLK_outAnd the count value output from the counter 2 when the rising detection signal S is output from the rising detector 1 and the sampling value is within the first range. When the sampling value is in the third range that is intermediate between the first range and the second range, either the UP signal or the DOWN signal is output. The phase comparison circuit is composed of the comparison circuit 3 that does not output the signal.
[0004]
The variable frequency dividing circuit 4 divides the signal of the oscillator 5 having a period T, and is set to a relatively small first frequency dividing ratio (N-1) while the UP signal is input. The second division ratio (N + 1) is set to a relatively large value while the DOWN signal is being input, and a third intermediate division that is a standard while neither the UP signal nor the DOWN signal is input. The frequency ratio is set to N and the reference clock CLK_refOutput clock CLK synchronized to_outWorks to generate
[0005]
This conventional example will be described in more detail. Reference clock CLK_refPeriod and output clock CLK of the PLL circuit_outThe cycle for counting (M + 1) is the same. In FIG. 11A, the count values 0 to M1-1 are set to the first range, and the count value M2 +.1To M is the second range, and the count values M1 to M2 are the third range. As shown in FIG. 11B, the first range and the second range are expressed as logical values as a simple expression of the count value as “1”, The third range is indicated as “0”.
[0006]
  When the reset signal shown in FIG. 12A changes from “0” to “1” and the reset is released, the counter 4 starts counting, and the count value is as shown in FIG. Output. And the first reference clock CLK after reset release_refIs input as shown in FIG. 12B, the rising detector 1 detects the rising edge and outputs the rising detection signal S as shown in FIG. 12C. At this time, the comparison circuit 3 samples the count value of the counter 2 and outputs a DOWN signal as shown in FIG. 12 (f) if the value is within the second range. Thereby, the variable frequency dividing circuit 4 has a frequency dividing ratio as shown in FIG.In the period during which the rising detection signal S is detected,Change to N + 1 frequency division. In this way, the digital PLL circuit enters the pull-in operation as shown in FIG._refThe pull-in is completed when the rising edge detection of the signal reaches the third range, and the reference clock CLK_refOutput clock CLK synchronized to_outIs generated.
[0007]
In the above operation, the UP signal is not output as shown in FIG.
[0008]
[Problems to be solved by the invention]
Incidentally, during the initial operation shown in FIG. 12, the reference clock CLK shown in FIG._refIf the phase difference in the third range is significantly different from the reference clock CLK_refThe time T1 for pulling the rising edge to the third range is the equation shown in FIG.
T1 = AT_ref/ T
(However, A is the first reference clock CLK after the count value exceeds the third range after the count starts._refTime to rise, T_refIs the reference clock CLK_ref, T indicates the period of the oscillation signal of the oscillator 5. )
It will be the time required. Also, phase correction is applied and the output clock CLK_outThe timing at which the period of 変 化 changes by ± T is the input reference clock CLK_refIt depends on.
[0009]
For example, output clock CLK_outCorrection of the reference clock CLK_refAt the timing when the rising detector 1 detects the rising edge, it is determined by the comparison circuit 3 whether the count value is in the first to third ranges, and the division ratio is changed by one cycle based on the determination. Is done. In the case of FIG. 13, after the reset signal shown in FIG. 13A changes to “1” and the reset is released, the reference clock CLK shown in FIG._refSince the count value ((d)) of the rising detection timing (FIG. (C)) from the first rising detection timing to the second and third times is within the second range, Then, the DOWN signal is output from the comparison circuit 3 as shown in FIG. 5E, and the variable frequency dividing circuit 4 changes the frequency division ratio to N + 1 for one cycle, and the output clock CLK_outIs output as shown in FIG.
[0010]
Similarly, in the case of FIG. 14, after the reset signal shown in FIG. 14A changes to “1” and the reset is released, the reference clock CLK shown in FIG._refIs within the first range of the count value (FIG. (C)) of the rising detection timing (FIG. (B)) from the first rising detection timing to the second and third times. In this case, the UP signal is output from the comparison circuit 3 as shown in FIG. 4D, and is corrected at the timing shown in FIG. 5F, and the variable frequency dividing circuit 4 sets the frequency dividing ratio to N for one cycle. Change to -1. In the above operation, the DOWN signal is not output as shown in FIG.
[0011]
As shown in FIG. 15 (a), the conventional digital PLL circuit 6 in which the phase correction is performed at an arbitrary point is shown in FIG._outIn the case of a data transmission apparatus that uses as a clock signal for processing timing, when a timing signal is given from the processing timing generation circuit 7 to the arithmetic processing unit 8, as shown in FIG. Deviation occurs between the timing and the timing of correction, and there may be cases where the time required for arithmetic processing cannot be secured, so it is necessary to design based on when the clock is the shortest due to phase correction, There was a problem that the degree of freedom in designing the subsequent circuit was low.
[0012]
The present invention has been made in view of the above points, and an object of the present invention is to provide a digital PLL circuit having a small jitter width and a high pull-in speed during initial operation. .
ContractThe object of the invention of claim 2 is that a digital PL for fixing the timing when the phase of the output clock is changed due to phase correction.L timesTo provide a road.
[0013]
The object of the invention of claim 3 is to fix the timing at which the phase of the output clock changes due to the phase correction, and to complete the phase synchronization pull-in in one cycle of the phase correction cycle, and also to increase the degree of freedom in designing the subsequent circuit. An object of the present invention is to provide a digital PLL circuit that can be secured.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a phase comparison circuit that compares the phases of the reference clock and the output clock, and a frequency dividing ratio that increases or decreases in accordance with the output of the phase comparison circuit, is higher than the reference clock. A digital PLL circuit comprising a variable frequency dividing circuit for frequency-dividing the first clock, wherein the phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal; and the rising edge detection circuit This is initialized by the rising detection signal output for the first time after resetting from the counter, and after this initialization, the counter that counts the output clock and outputs the count value, and the detection signal is output from the rising detector. The count value output from the counter is sampled at the time, and when the sampling value is in the first range, an UP signal is output, and when the sampling value is in the second range, DO is output. N signal is output, and when the sampling value is in the third range which is intermediate between the first range and the second range, it is constituted by a comparison circuit which outputs neither the UP signal nor the DOWN signal, and the variable frequency division The circuit sets the first division ratio smaller than the standard division ratio while the UP signal is input, with the division ratio while neither the UP signal nor the DOWN signal is input as a standard. When the DOWN signal is input, the second frequency division ratio is set to be larger than the standard frequency division ratio. When the UP signal or the DOWN signal of the phase comparison circuit is input, the frequency is divided by one period. The ratio is configured to be the first or second division ratio, and the time until the completion of synchronization in the initial operation can be shortened.
[0015]
  According to a second aspect of the present invention, there is provided a phase comparison circuit for comparing the phases of the reference clock and the output clock, and a variable for dividing the clock having a frequency higher than that of the reference clock by increasing / decreasing the division ratio according to the output of the phase comparison circuit. A digital PLL circuit comprising a frequency divider and a phase correction timing pulse, wherein the phase comparator circuit detects a rising edge of the reference clock and outputs a detection signal; and counts the output clock A counter that outputs the count value, and the count value output from the counter when the detection signal is output from the rising detector, and when the sampling value is within the first range, an UP signal is output. DOWN signal is output when in the second range, and UP signal is output when the sampling value is in the third range which is intermediate between the first range and the second range. Comparing circuit that outputs neither of the DOWN signals, and the variable frequency dividing circuit receives the UP signal as a standard frequency division ratio while neither the UP signal nor the DOWN signal is input. Is set to a first division ratio smaller than a standard division ratio, and is set to a second division ratio larger than a standard division ratio while the DOWN signal is input, and the phase Phase correction timing based on input of UP signal or DOWN signal of comparison circuitWhen the signal is input, the period of the phase correction timing signal,The division ratio is configured to be the first division ratio or the second division ratio, and it is possible to fix the timing for the phase correction.
[0016]
  According to a third aspect of the present invention, there is provided a phase comparison circuit for comparing the phases of the reference clock and the output clock, and a variable for dividing the clock having a frequency higher than that of the reference clock by increasing / decreasing the division ratio according to the output of the phase comparison circuit. A digital PLL circuit comprising a frequency divider, a phase correction timing pulse, and a high-speed pull-in control circuit, wherein the phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal; A counter that counts the output clock and outputs the count value; and a count value output from the counter when the detection signal is output from the rising detector, and the sampling value is in the first range Output the UP signal, output the DOWN signal when in the second range, and the sampling value is in the third range which is intermediate between the first range and the second range. Is constituted by a comparator circuit does not output any of the UP signal, DOWN signal when the high-speed pull-in control circuit, the countingInstrument totalA phase difference timing pulse is output from the numerical value and the phase correction timing pulse, and the variable frequency dividing circuit uses the frequency dividing ratio during which neither the UP signal nor the DOWN signal is input as a standard. While the signal is being input, the first frequency dividing ratio is set to be smaller than the standard frequency dividing ratio, and while the DOWN signal is being input, the second frequency dividing ratio is set to be larger than the standard frequency dividing ratio. The timing pulse output from the high-speed pull-in control circuit based on the input of the UP signal or DOWN signal output from the phase comparison circuitOnly forThe frequency division ratio is configured to be the first or second frequency division ratio, and the timing for phase correction can be fixed and the time until the completion of synchronization can be shortened.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
The present embodiment corresponds to the invention of claim 1, and as shown in FIG. 1, a rising detector 1 for detecting a rising edge of a reference clock and outputting a rising detection signal S, and a reset release from the rising detector 1. Thereafter, it is initialized by the rising detection signal S output for the first time, and after this initialization, the counter 2 that counts the output clock and outputs the count value, and the rising detection signal S from the rising detector 1 The count value output from the counter 2 at the time of output is sampled. When the sampling value is in the first range, the UP signal is output, and when it is in the second range, the DOWN signal is output. Is in a third range that is intermediate between the first range and the second range, a phase comparison circuit is configured by the comparison circuit 3 that outputs neither the UP signal nor the DOWN signal.
[0018]
The variable frequency dividing circuit 4 divides the signal from the oscillator 5 having a period T, and is set to a relatively small first frequency dividing ratio (N-1) while the UP signal is input. The second frequency division ratio (N + 1) is set to a relatively large value while the DOWN signal is being input, and the standard third intermediate ratio is set while neither the UP signal nor the DOWN signal is input. When the UP signal or the DOWN signal of the comparison circuit 3 is input, the circuit has a frequency division ratio of the first or second frequency division ratio for one period.
[0019]
Next, the operation of this embodiment will be described with reference to FIGS. First, in this embodiment, the reference clock CLK_refPeriod and output clock CLK of the PLL circuit_outThe cycle for counting (M + 1) is the same. In FIG. 2A, the count values 0 to M1-1 are set to the first range, and the count value M2 +.1To M is the second range, and the count values M1 to M2 are the third range, and the first range and the second range are set to “1” as shown in FIG. The third range is indicated as “0”.
[0020]
If the reset signal shown in FIG. 3A is reset to “0” in the counter 2, the count value initialization flag of the counter 2 is “0” as shown in FIG. The count value is 0 as shown in FIG. After the reset signal becomes “1” and the reset is released, the initialization flag maintains “0”, and the counter 2 outputs the output clock CLK_outStarts counting and outputs the count value. Here, after the reset is released, the reference clock CLK shown in FIG._refWhen the rising detector 1 detects the first rising edge, the rising detector 1 outputs a rising edge detection signal S as shown in FIG.
[0021]
Since the initialization flag is 0 and the rising detection signal S is input, the counter 2 is initialized to the count value in the third range between M1 and M2 as shown in FIG. As shown in 3 (e), “0” is changed to “1”. This initialization flag is maintained until it is reset.
By this operation, the next reference clock CLK_refThe count value of the counter 2 is in the third range at the rise timing of the reference clock CLK_refAnd the reference clock CLK to the count value Ml or M2 due to the difference in accuracy between the oscillator 5 and the oscillator 5_refRising edge of the reference clock CLK_refAnd output clock CLK_outWill be synchronized.
[0022]
In the comparison circuit 3, the count value output from the counter 2 is sampled at the time when the first and subsequent rising signals are input, and when the sampling value is within the first range, as shown in FIG. The UP signal is output, and when it is within the second range, the DOWN signal is output as shown in FIG.
(Embodiment 2)
The second embodiment corresponds to the invention of claim 2 and, as shown in FIG._refRising detector 1 for detecting the rising edge and outputting rising detection signal S, and output clock CLK_outAnd the count value output from the counter 2 when the rising detection signal S is output from the rising detector 1 and the sampling value is within the first range. When the sampling value is in the third range that is intermediate between the first range and the second range, either the UP signal or the DOWN signal is output. The phase comparison circuit is composed of the comparison circuit 3 that does not output the signal.
[0023]
The variable frequency dividing circuit 4 divides the signal of the oscillator 5 having a period T, and is set to a relatively small first frequency dividing ratio (N-1) while the UP signal is input. While the DOWN signal is input, the second frequency division ratio (N + 1) is set to a relatively large value, and while neither the UP signal nor the DOWN signal is input, a standard intermediate frequency division ratio N is set. The frequency division ratio is set to the first or second frequency division ratio for one period by the phase correction timing pulse TP based on the input of the UP signal or DOWN signal output from the comparison circuit 3.
[0024]
Next, the operation of this embodiment will be described with reference to FIGS. First, in this embodiment, the reference clock CLK_refPeriod and output clock CLK of the PLL circuit_outThe cycle for counting (M + 1) is the same. In FIG. 5A, the count values 0 to M1-1 are set to the first range, and the count value M2 +.1To M is the second range, and the count values M1 to M2 are the third range. As a simple expression of the count value, the first range and the second range are set to “1” as shown in FIG. The third range is indicated as “0”.
[0025]
Now, the circuit of this embodiment has a reference clock CLK shown in FIG._ref6 is detected by the rising detector 1, and the comparison circuit 3 samples the count value of the counter 2 shown in FIG. 6 (c) in response to the rising detection signal S shown in FIG. 6 (b). Accordingly, the UP signal shown in FIG. 6D (not output in the figure) or the DOWN signal shown in FIG. 6E is output, and the variable frequency dividing circuit 4 corresponds to these UP signal or DOWN signal. The operation for performing the division ratio control is basically the same as the conventional example of FIG. 10, but in the present embodiment, the output clock CLK of the digital PLL circuit._outA phase correction timing pulse TP shown in FIG. 6 (f) that is output at a timing at which the degree of freedom of design of a circuit that operates using, for example, a time zone during which no arithmetic processing is performed, can be used. That is, when the phase correction timing signal TP is input to the variable frequency dividing circuit 4, the frequency dividing ratio is changed at the timing, and the output clock CLK as shown in FIG._outCorrection control is performed.
[0026]
By this operation, the output clock CLK of the digital PLL circuit_outThis makes it possible to predict when the phase correction of the digital PLL circuit will take place.
(Embodiment 3)
The third embodiment corresponds to the invention of claim 3, and as shown in FIG._refRising detector 1 for detecting the rising edge and outputting rising detection signal S, and output clock CLK_outWhen the detection value S is output from the rising detector 1 and the count value output from the counter 2 is sampled and the sampling value is within the first range Outputs an UP signal, outputs a DOWN signal when it is in the second range, and if the sampling value is in a third range that is intermediate between the first range and the second range, both the UP signal and the DOWN signal are output. A phase comparison circuit is constituted by the comparison circuit 3 which does not output.
[0027]
  The high-speed pull-in control circuit 9Count value of measuring instrument 2And a high-speed pull-in signal HTP that is a phase difference timing pulse from the phase correction timing pulse TP.
  The variable frequency dividing circuit 4 divides the signal of the oscillator 5 having a period T, and is set to a relatively small first frequency dividing ratio (N−1) while the UP signal is input. While the DOWN signal is input, the second frequency division ratio (N + 1) is set to a relatively large value. When neither the UP signal nor the DOWN signal is input, the standard intermediate frequency division ratio N is set. The frequency division ratio is set to the first or second frequency division by one period by the high-speed pull-in signal HTP output from the high-speed pull-in control circuit 9 based on the input of the UP signal or DOWN signal output from the comparison circuit 3 It becomes the composition which becomes ratio.
[0028]
Next, the operation of this embodiment will be described with reference to FIGS. First, in this embodiment, the reference clock CLK_refPeriod and output clock CLK of the PLL circuit_outThe period for counting (M + 1) is the same. In FIG. 8A, the count values 0 to M1-1 are set to the first range, and the count value M2 +.1To M is the second range, and the count values M1 to M2 are the third range. As a simple expression of the count value, the first range and the second range are set to “1” as shown in FIG. The third range is indicated as “0”.
[0029]
  Now, the circuit of the present embodiment has a reference clock CLK shown in FIG._ref9 is detected by the rising detector 1, and the comparison circuit 3 samples the count value of the counter 2 shown in FIG. 9C corresponding to the rising detection signal S shown in FIG. Accordingly, the UP signal shown in FIG. 9D (not output in the figure) or the DOWN signal shown in FIG. 9E is output, and the variable frequency dividing circuit 4 responds to these UP signal or DOWN signal. The operation for performing the division ratio control is basically the same as the conventional example of FIG. 10, but in the present embodiment, the output clock CLK of the digital PLL circuit._outOutput clock CLK accompanying the phase correction operation_outIt is possible to predict when the period of the period changes and to obtain a high rate of phase pull-in operation so that synchronization can be achieved in a short time. For example, assuming that the count value at the time of rising detection is MD, at this time, the reference clock CLK_refRise of a phase difference between the value Ml at the end of the third range and (M1-MD).This (M1-MD) is the output clock CLK _out In order to be counted, the period of (M1-MD) is the output clock CLK _out Is an integral multiple of the period T. Therefore, since there is a difference of (M1−MD) = aT, the difference of (M1−MD) becomes 0 when the variable frequency dividing circuit 4 performs frequency division N + 1 to N−1.Therefore, when the phase correction timing pulse TP shown in FIG. 9F is input to the high-speed pull-in control circuit 9, the high-speed pull-in control circuit 9 a = (Ml−MD) in order to reduce the phase difference by (M1−MD). ) / T times high-speed pull-in signal HTP is output in FIG. As shown in FIG. 9 (h), the variable frequency dividing circuit 4 changes the frequency dividing ratio at the timing of the high-speed pull-in signal HTP to output clock CLK_outIs output, and the pull-in operation can be completed in a short time.
[0030]
【The invention's effect】
According to a first aspect of the present invention, there is provided a phase comparison circuit that compares the phases of the reference clock and the output clock, and a variable that divides the frequency of the clock having a frequency higher than that of the reference clock by increasing or decreasing the frequency division ratio according to the output of the phase comparison circuit. The phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal, and a first time after resetting from the rising detector. And a counter that counts the output clock and outputs the count value after the initialization, and from the counter when the detection signal is output from the rising detector. The output count value is sampled, and when the sampling value is in the first range, the UP signal is output, and when the sampling value is in the second range, the DOWN signal is output. And a comparison circuit that outputs neither the UP signal nor the DOWN signal when the rounding value is in the third range that is intermediate between the first range and the second range, and the variable frequency dividing circuit includes the UP signal, While the UP signal is input with the frequency division ratio during which none of the DOWN signals are input as a standard, the first frequency division ratio is set to be smaller than the standard frequency division ratio, and the DOWN signal is input. During this time, the second division ratio is set to be larger than the standard division ratio, and when the UP signal or DOWN signal of the phase comparison circuit is input, the division ratio is changed to the first or second division by one period. Therefore, it is possible to reduce the time until the completion of synchronization at the initial operation, to provide a digital PLL circuit with a small jitter width and a high pull-in speed at the initial operation. Be able to There is a result.
[0031]
  According to a second aspect of the present invention, in the second aspect of the present invention, a phase comparison circuit that compares the phases of the reference clock and the output clock, and a frequency dividing ratio that increases or decreases in accordance with the output of the phase comparison circuit, is higher than the reference clock. A digital PLL circuit composed of a variable frequency dividing circuit that divides the clock and a phase correction timing pulse, wherein the phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal A counter that counts the output clock and outputs the count value, and samples the count value output from the counter when a detection signal is output from the rising detector, and the sampling value is within a first range. UP signal is output when in the second range, and DOWN signal is output when in the second range, and the sampling value is in the third range which is intermediate between the first range and the second range. In this case, the variable frequency dividing circuit is configured with a division ratio during which neither the UP signal nor the DOWN signal is input as a standard. While the signal is being input, the first frequency division ratio is set to be smaller than the standard frequency division ratio, and while the DOWN signal is being input, the second frequency division ratio is larger than the standard frequency division ratio. Phase correction timing based on the UP signal or DOWN signal input of the phase comparison circuit.When the signal is input, the period of the phase correction timing signal,Since the division ratio is configured to be the first or second division ratio,,There is an effect that it is possible to provide a digital PLL circuit that can fix the timing at which the phase correction is performed and fixes the timing at which the phase of the output clock is changed by changing the phase.
[0032]
  According to a third aspect of the present invention, there is provided a phase comparison circuit that compares the phases of the reference clock and the output clock, and a variable that divides a clock having a higher frequency than the reference clock by increasing / decreasing a division ratio according to the output of the phase comparison circuit. A digital PLL circuit comprising a frequency divider, a phase correction timing pulse, and a high-speed pull-in control circuit, wherein the phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal; A counter that counts the output clock and outputs the count value; and a count value output from the counter when the detection signal is output from the rising detector, and the sampling value is in the first range Output UP signal, output DOWN signal when in the second range, and the sampling value is in the third range which is intermediate between the first range and the second range The case is composed of a comparator circuit does not output any of the UP signal, DOWN signal, the high-speed pull-in control circuit, the countingInstrument totalA phase difference timing pulse is output from the numerical value and the phase correction timing pulse, and the variable frequency dividing circuit uses the frequency dividing ratio during which neither the UP signal nor the DOWN signal is input as a standard. While the signal is being input, the first frequency dividing ratio is set to be smaller than the standard frequency dividing ratio, and while the DOWN signal is being input, the second frequency dividing ratio is set to be larger than the standard frequency dividing ratio. The timing pulse output from the high-speed pull-in control circuit based on the input of the UP signal or DOWN signal output from the phase comparison circuitOnly forSince the frequency division ratio is configured to be the first frequency division ratio or the second frequency division ratio, the timing for performing phase correction can be fixed and the time until the completion of synchronization can be shortened. It is possible to provide a digital PLL circuit that fixes the timing at which the period of the signal changes and completes the synchronization of the phase synchronization by one period of the phase correction period, and the design criteria of the circuit in the subsequent stage is based on the period of the reference clock. Therefore, there is an effect that the degree of freedom of circuit design in the subsequent stage can be secured.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of the count value of the above.
FIG. 3 is a timing chart for explaining the operation.
FIG. 4 is a circuit configuration diagram of Embodiment 2 of the present invention.
FIG. 5 is an explanatory diagram of the count value of the above.
FIG. 6 is a timing chart for explaining the operation of the above.
FIG. 7 is a circuit configuration diagram of Embodiment 3 of the present invention.
FIG. 8 is an explanatory diagram of the count value of the above.
FIG. 9 is a timing chart for explaining the operation of the above.
FIG. 10 is a circuit configuration diagram of a conventional example.
FIG. 11 is an explanatory diagram of the count value of the above.
FIG. 12 is a timing chart for explaining the operation of the above.
FIG. 13 is a timing chart for explaining the operation of the above.
FIG. 14 is a timing chart for explaining the operation of the above.
FIG. 15 is an explanatory diagram of the problem described above.
[Explanation of symbols]
1 Rising detector
2 counter
3 Comparison circuit
4 Variable frequency divider
5 Oscillator
CLK_ref  Reference clock
CLK_out  Output clock
S Rise detection signal

Claims (3)

A phase comparison circuit that compares the phase of the reference clock and the output clock, and a variable frequency division circuit that increases or decreases the division ratio according to the output of the phase comparison circuit and divides the clock having a higher frequency than the reference clock. The phase comparison circuit includes a rising detector that detects a rising edge of the reference clock and outputs a detection signal, and a rising edge detection signal output from the rising detector for the first time after resetting. After the initialization, the counter that counts the output clock and outputs the count value, and the count value output from the counter when the detection signal is output from the rising detector are sampled. When the sampling value is in the first range, an UP signal is output. When the sampling value is in the second range, a DOWN signal is output. When it is in the third range which is the middle of the two ranges, it is constituted by a comparison circuit that outputs neither the UP signal nor the DOWN signal, and the variable frequency dividing circuit receives both the UP signal and the DOWN signal. When the UP signal is input as a standard frequency division ratio, the first frequency division ratio is set to be smaller than the standard frequency division ratio. When the DOWN signal is input, the standard frequency division ratio is set. When a second division ratio larger than the division ratio is set and the UP signal or DOWN signal of the phase comparison circuit is input, the division ratio is set to the first or second division ratio for one period. A digital PLL circuit characterized by comprising. A phase comparison circuit that compares the phase of the reference clock and the output clock, a variable frequency division circuit that increases and decreases the division ratio according to the output of the phase comparison circuit, and divides the clock having a higher frequency than the reference clock, and phase correction timing A digital PLL circuit comprising a pulse, wherein the phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal; and counts the output clock and outputs the count value When the detection signal is output from the counter and the rising detector, the count value output from the counter is sampled. When the sampling value is in the first range, an UP signal is output and the count value is output to the second range. In some cases, a DOWN signal is output, and when the sampling value is in a third range that is intermediate between the first range and the second range, either the UP signal or the DOWN signal is output. The variable frequency dividing circuit is standard while the UP signal is input with the frequency division ratio during which neither the UP signal nor the DOWN signal is input as a standard. The first frequency division ratio is set to be smaller than the frequency division ratio. While the DOWN signal is input, the frequency division ratio is set to a second frequency division ratio larger than the standard frequency division ratio, and the UP of the phase comparison circuit is set. signal or the period of the input when the phase correction timing signal based on is input to the phase correction timing signal DOWN signals, that formed by constituting the frequency division ratio so that the first or the second division ratio A featured digital PLL circuit. A phase comparison circuit that compares the phase of the reference clock and the output clock, a variable frequency division circuit that increases and decreases the division ratio according to the output of the phase comparison circuit, and divides the clock having a higher frequency than the reference clock, and phase correction timing A digital PLL circuit comprising a pulse and a high-speed pull-in control circuit, wherein the phase comparison circuit detects a rising edge of the reference clock and outputs a detection signal; A counter that outputs a count value, and a count value output from the counter when the detection signal is output from the rising detector, and outputs an UP signal when the sampling value is within the first range. DOWN signal is output when in the second range, and UP signal when the sampling value is in the third range which is intermediate between the first range and the second range, Any of OWN signal is constituted by a comparator circuit does not output, the high-speed pull-in control circuit, a count value of the counter, outputs a timing pulse phase difference from the phase correction timing pulse, the variable divider is The first division ratio smaller than the standard division ratio is set while the UP signal is input, with the division ratio during which neither the UP signal nor the DOWN signal is input as a standard. While the DOWN signal is input, the high-speed pull-in control circuit is set to a second frequency division ratio larger than a standard frequency division ratio and based on the input of the UP signal or the DOWN signal output from the phase comparison circuit. A digital PLL circuit configured so that the frequency division ratio becomes the first frequency division ratio or the second frequency division ratio only during the period of the timing pulse output from.

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