JPS5814575A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS5814575A JPS5814575A JP11202581A JP11202581A JPS5814575A JP S5814575 A JPS5814575 A JP S5814575A JP 11202581 A JP11202581 A JP 11202581A JP 11202581 A JP11202581 A JP 11202581A JP S5814575 A JPS5814575 A JP S5814575A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrodes
- thin film
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000007743 anodising Methods 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims description 11
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 14
- 238000007254 oxidation reaction Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Abstract
Description
【発明の詳細な説明】
本発明は、薄膜トランジスタ(TPT)のスイッチング
特性を左右するゲート絶縁膜の低温形成法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a gate insulating film at a low temperature, which influences the switching characteristics of a thin film transistor (TPT).
絶縁ゲート薄膜トランジスタの構造は、基板−半導体薄
膜一絶縁層一導電層である。薄膜トランジスタの特徴で
ある大面積化及び、安価である性賓を利用するためには
、基板として、ガラス及びセラミックスを使用する事が
考えられ、その場合には、高温での処理が難しくなる。The structure of an insulated gate thin film transistor is a substrate, a semiconductor thin film, an insulating layer, and a conductive layer. In order to take advantage of the large area and low cost that characterize thin film transistors, it is conceivable to use glass or ceramics as the substrate, but in that case, processing at high temperatures becomes difficult.
現在、半導体技術において使用されているゲート絶縁膜
には、5102及び、A/、03があるが、現在の所、
熱酸化法を主に利用している。だカー、基板により温度
の制約を受ける場合、一般に利用されている熱酸化は難
しい。他の絶縁膜形成法としては、PVD及びCVD法
があるが、熱酸化膜に比べて、膜の均一性、絶縁性、膜
中の欠陥、不−鈍物密度、界面準位密度等の点で劣って
いる?本発明は、低温で熱酸化膜に匹敵する絶縁膜を、
陽極酸化を利用して形成する方法を提供するものである
。Gate insulating films currently used in semiconductor technology include 5102 and A/03;
Thermal oxidation method is mainly used. Generally used thermal oxidation is difficult when temperature is restricted by the oxidizer or substrate. Other insulating film formation methods include PVD and CVD, but compared to thermal oxide films, these methods have disadvantages such as film uniformity, insulating properties, defects in the film, impurity density, interface state density, etc. Are you inferior? The present invention creates an insulating film comparable to a thermal oxide film at low temperatures.
The present invention provides a method of forming the film using anodic oxidation.
陽極酸化法としては、従来は金属が中心に行なわれ、半
導体技術としては、良導体膜において利用されていたの
に対し、本発明では、バタン化された電極を利用する事
により、高抵抗膜においても、均一な膜を形晟でき、か
つ、この電極をソース、ドレイン電極として使用してい
るため、工程的、面積的にも薄膜トランジスタ製造法と
しては適している。Conventionally, anodic oxidation was mainly applied to metals, and in semiconductor technology, it was used for good conductor films. However, in the present invention, by using a battened electrode, it can be applied to high resistance films. This method is also suitable as a method for manufacturing thin film transistors in terms of process and area because a uniform film can be formed and these electrodes are used as source and drain electrodes.
絶縁基板上に半導体膜を形成する方法としては、低温に
おいて、プラズマ及び低圧でのCVD、或は、PVD法
等が考えられるが、形成された膜は、シート抵抗が太き
(、従来の方法による陽極酸化は、利用しがたい。本発
明は、ソース及びドレイン電極として、基板上にバタン
化された電極、例えば、細線状電極をあらかじめ形成し
、その上に、非絶縁性薄膜、例えば、半導体膜を形成し
、前記した電極を陽極として利用し、半導体膜を層状に
陽極酸化し、上記層状陽極酸化膜を絶縁膜、例えば、ゲ
ート膜として利用し、上記細線状電極をソース及びドレ
イン電極とする薄膜トランジスタの製造方法である。さ
らに、基板として例えば、ガラス及びセラミックスを利
用する場合において、響を防ぐために、基板上へあらか
じめ、シリコンナイトライド等で不純物トラップ膜を形
成し、そ縁性薄膜、例えば、半導体膜を付けて、ソース
、ドレイン電極をす/ドイッチ状にして、陽極酸化ラン
ジスタの製造方法をも提供するものである。Possible methods for forming a semiconductor film on an insulating substrate include CVD using plasma and low pressure at low temperatures, PVD, etc.; However, in the present invention, as source and drain electrodes, battened electrodes, e.g., thin wire electrodes, are formed in advance on a substrate, and then a non-insulating thin film, e.g. A semiconductor film is formed, the above electrode is used as an anode, the semiconductor film is anodized in layers, the layered anodic oxide film is used as an insulating film, for example, a gate film, and the thin wire electrodes are used as source and drain electrodes. In addition, when using glass or ceramics as a substrate, an impurity trapping film is formed on the substrate in advance using silicon nitride or the like in order to prevent vibrations, and For example, the present invention also provides a method of manufacturing an anodized transistor by attaching a semiconductor film and forming source and drain electrodes in a switch/deutsch shape.
この場合、不純物トラップ膜は、陽極酸化時に半導体膜
に対し悪影響を及ぼす効果を防ぐと伴に、バタン化すべ
き電極のバタン精度の向上及び、トランジスタのスイッ
チング特性の向上等に重要である。また、上記トラップ
膜を形成する一事により、従来陽極酸化しにくい基板及
び、利用しにくかった電極の利用も可能にし、陽極酸化
の適応能力の向上に効果的であ逮。又、非絶縁性薄膜を
陽極酸化す゛る工程を含む薄膜トランジスタの製造にお
いて、基板上iパタン化されたソース、ドレイ/電
□極をあらかじめ形成した後、5非絶縁性薄膜を形成し
、新たに陽極を形成する事なく、上記ソース、ドレイン
電極を利用し、非絶縁性薄膜を陽極酸化する事により、
均一で、絶縁性の高い膜の形成が可能となる。次に図面
を用いて本発明の詳細な説明する。In this case, the impurity trap film is important for preventing adverse effects on the semiconductor film during anodic oxidation, improving the batting accuracy of the electrode to be battened, and improving the switching characteristics of the transistor. Furthermore, by forming the trap film described above, it is possible to use substrates and electrodes that have been difficult to use in the past, which is effective in improving the adaptability of anodic oxidation. In addition, in the manufacture of thin film transistors, which includes the process of anodizing non-insulating thin films, the i-patterned sources, drains, and electrodes are formed on the substrate.
□ After forming the electrode in advance, form a non-insulating thin film 5 and anodize the non-insulating thin film using the source and drain electrodes without forming a new anode.
It becomes possible to form a uniform and highly insulating film. Next, the present invention will be explained in detail using the drawings.
第1図は、本発明の一実施例で薄膜トランジスタの製造
を説明する工程図である。FIG. 1 is a process diagram illustrating the manufacture of a thin film transistor according to an embodiment of the present invention.
第1図(A)は、基板上への細線状電極の形成工程を示
している。細線状電極は、リフトオフ及び、エツチング
等を利用して行ない、1は基板、2はバタン化された電
極、例えば、細線状電極を示している。この細線状電極
2は、陽極酸化電極として利用し、かつ、ソース、ドレ
イン電極として利用する。FIG. 1(A) shows the process of forming thin wire electrodes on a substrate. The thin wire-like electrodes are formed by using lift-off, etching, etc., and 1 is a substrate, and 2 is a battened electrode, for example, a thin wire-like electrode. This thin wire electrode 2 is used as an anodic oxidation electrode, and also as a source and drain electrode.
第1図(B)は、第1図(A)で形成した細線電極上へ
非絶縁性薄膜、例えば、半導体薄膜3を形成し該半導体
薄膜3と、細線状・電極2との接触を十分に取り、かつ
、電極間距離20を短くする事により、半導体薄膜3が
高抵抗でも、表面電位を均一にでき、第1図(C)に示
す様に、陽極酸化を行う事により、均一な酸化膜5が形
成される。In FIG. 1(B), a non-insulating thin film, for example, a semiconductor thin film 3 is formed on the thin wire electrode formed in FIG. 1(A), and sufficient contact between the semiconductor thin film 3 and the thin wire electrode 2 is made. By taking this and shortening the distance 20 between the electrodes, even if the semiconductor thin film 3 has a high resistance, the surface potential can be made uniform, and as shown in FIG. An oxide film 5 is formed.
陽極酸化は、液相でも気相でも可能であり、特に、酸素
プラズマを用いた気相法は、気相のコンダクタンスが低
いために、高抵抗体でも、均一かつ、良質の酸化膜が得
られる。4は、陽極酸化の時の、対向電極であり、5は
、陽極酸化により形成された酸化膜である。第1図<
D > +i、第1図(B)により形成した半導体薄膜
3及び、第1図(C)により形成された酸化膜5をバタ
ーニングし、第1図(A)の細線状電極2を、ソース及
びドレイン電極として利用し、酸化膜5上にゲート電極
6を付け、絶縁ゲート薄膜トランジスタを形成したもの
である。Anodic oxidation can be performed in either liquid phase or gas phase, and in particular, the gas phase method using oxygen plasma has a low conductance in the gas phase, so it is possible to obtain a uniform and high-quality oxide film even on high-resistance materials. . 4 is a counter electrode during anodic oxidation, and 5 is an oxide film formed by anodic oxidation. Figure 1<
D > +i, the semiconductor thin film 3 formed in FIG. 1(B) and the oxide film 5 formed in FIG. 1(C) are buttered, and the thin wire-shaped electrode 2 in FIG. 1(A) is The oxide film 5 is used as a drain electrode, and a gate electrode 6 is attached on the oxide film 5 to form an insulated gate thin film transistor.
第2図は、基板と細線状電極21間に、基板10かもの
不純物拡散を防ぐための、シリコンナイトライド等で不
純物トラップ膜11の形成を含む工程を加えた場合であ
る。第2図(A−1)は、不純物トラップ暎11をあら
かじめ形成する工程を示している。他の工程は、第1図
の場合と同様であり、この場合は、第2図(C)に示す
様に、細線状電極21は、不純物トラップ膜11と半導
体膜31とのサンドイッチ構造になっている。ここに示
した工程は、ドーピングしていないが、ドーピング工程
を含める事も可能であるし、第2図のサンドイッチ構造
の不純物トラップは、基板10への細線状電極21の密
着向上を目的とした膜も含めている。尚、41は陽極酸
化のときの対向電極、51は酸化膜、61はゲート電極
である。FIG. 2 shows a case where a step including forming an impurity trap film 11 of silicon nitride or the like is added between the substrate and the thin wire electrode 21 in order to prevent impurity diffusion into the substrate 10. FIG. 2 (A-1) shows a step of forming the impurity trap layer 11 in advance. The other steps are the same as in the case of FIG. 1, and in this case, as shown in FIG. 2(C), the thin wire electrode 21 has a sandwich structure of the impurity trap film 11 and the semiconductor film 31. ing. Although the process shown here does not involve doping, it is possible to include a doping process, and the impurity trap of the sandwich structure shown in FIG. It also includes membranes. Note that 41 is a counter electrode for anodic oxidation, 51 is an oxide film, and 61 is a gate electrode.
第3図は、察際の陽極酸化装置の概要を示す説明図であ
る。30は、電解液35の上下による電圧の変動を少な
くし、均一な膜を形成するために利用する絶縁性物質で
あり、34が、陽極酸化しようとする非絶縁性膜、66
が、ソース及びドレインを兼ねたバタン化された電極で
、陽極として使用する。32は、基板であり、66は、
陰極である。37は、電源である。FIG. 3 is an explanatory diagram showing an outline of the anodic oxidation device in question. 30 is an insulating material used to reduce fluctuations in voltage due to the rise and fall of the electrolytic solution 35 and form a uniform film; 34 is a non-insulating film to be anodized; 66
is a battened electrode that doubles as a source and drain, and is used as an anode. 32 is a substrate, 66 is
It is a cathode. 37 is a power source.
以−上の工程例からも明らかな如く本発明は、陽極酸化
に利用する電極を新たに形成するのではな(、トランジ
スタ(MOS)の電極として当然必要す、トランジスタ
構成部分としての一部を利用するため、プロセスの単純
化につながり、均一な絶縁膜を形成する事ができ、同時
に、ソース、ドレイン電極も形成できる。As is clear from the above process examples, the present invention does not involve forming a new electrode for use in anodic oxidation. The use of this method simplifies the process and allows the formation of a uniform insulating film, as well as the formation of source and drain electrodes at the same time.
た、半絶縁膜に対しても陽極酸化できる様にでき低温で
均一良質な膜形成を可能にし、TPTの利点を生かすの
に有効である。In addition, semi-insulating films can also be anodized, making it possible to form uniform and high-quality films at low temperatures, which is effective in taking advantage of the advantages of TPT.
本発明は、特に液晶等を用いた表示パネル基板上のTP
Tに有効な技術であり、腕時計等の小型携帯機器への表
示装置として特に適している。The present invention particularly focuses on TP on display panel substrates using liquid crystal etc.
This technology is effective for T, and is particularly suitable as a display device for small portable devices such as wristwatches.
第1図は、本発明の薄膜トランジスタ製造工程第2図は
、本発明の薄膜トランジスタの他の製造工程を示す工程
図である。
第3図は、陽極酸化装置の概要を示す説明図である。
1.10.62・・・・・・基板、
2.21・・・・・・パ、り/化されたソース、ドレイ
ン電極、 6.31・・・・・・琲壜場増4#半導体
膜、4.36.41・・・・・・陽極酸化のときの対向
電極、5.51・・・・・・酸化膜(ゲート絶RM)、
6.61・・・・・・ゲート電極、
11・・・・・・不純物トラップ膜、
65・・・・・・電解液、
36・・・・・・陰極。
第1図
【
(B)
−7\
C(
(D〕
−\−1〜10
4鴫−2ノ □
第3図
35′FIG. 1 is a process diagram for manufacturing a thin film transistor according to the present invention. FIG. 2 is a process diagram showing another manufacturing process for a thin film transistor according to the present invention. FIG. 3 is an explanatory diagram showing an outline of the anodizing device. 1.10.62... Substrate, 2.21... Parallelized source, drain electrode, 6.31... 4# semiconductor Film, 4.36.41... Counter electrode during anodic oxidation, 5.51... Oxide film (gate isolation RM),
6.61... Gate electrode, 11... Impurity trap film, 65... Electrolyte, 36... Cathode. Figure 1 [ (B)
-7\C( (D)
-\-1~10 4-2-2 □ Figure 3 35'
Claims (1)
極を形成する工程と、該電極上に非絶縁性薄膜を形成す
る工程と、該パタン化されたソース、ドレイン電極を陽
極として、前記非絶縁性薄膜を陽極酸化する工程とか・
らなることを特徴とする薄膜トランジスタの製造方法。 (2)基板上に不純物トラップ膜を形、成する工程と、
該不純物嘆上にバタン化されたソース、ドレイ/電極を
形成する工程と、該電極上に非絶縁性薄膜を形成する工
程と、該パタン化されたソース、ドレイン電極を陽極と
し、前記非絶縁性薄膜を陽極酸化する工程とからなるこ
とを特徴とする薄膜トランジスタの製造方法。[Claims] (+) A step of forming a patterned source/drain/electrode on a substrate, a step of forming a non-insulating thin film on the electrode, and a step of forming a patterned source/drain electrode. A step of anodic oxidizing the non-insulating thin film using as an anode.
A method for manufacturing a thin film transistor, characterized in that: (2) forming and forming an impurity trap film on the substrate;
forming a patterned source/drain/electrode on the impurity layer; forming a non-insulating thin film on the electrode; using the patterned source/drain electrode as an anode; 1. A method for manufacturing a thin film transistor, comprising the step of anodizing a thin film.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11202581A JPS5814575A (en) | 1981-07-17 | 1981-07-17 | Manufacture of thin film transistor |
GB08221029A GB2107115B (en) | 1981-07-17 | 1982-07-19 | Method of manufacturing insulated gate thin film effect transitors |
US06/621,324 US4502204A (en) | 1981-07-17 | 1984-06-15 | Method of manufacturing insulated gate thin film field effect transistors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11202581A JPS5814575A (en) | 1981-07-17 | 1981-07-17 | Manufacture of thin film transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5814575A true JPS5814575A (en) | 1983-01-27 |
JPH0318356B2 JPH0318356B2 (en) | 1991-03-12 |
Family
ID=14576106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11202581A Granted JPS5814575A (en) | 1981-07-17 | 1981-07-17 | Manufacture of thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5814575A (en) |
-
1981
- 1981-07-17 JP JP11202581A patent/JPS5814575A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0318356B2 (en) | 1991-03-12 |
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