JPH0651350A - Display device - Google Patents

Abstract

PURPOSE:To provide the display device which obviates the generation of the short circuit between electrodes or electrostatic breakdown in an interlayer insulating film even if these electrodes are formed to face each other via the interlayer insulating film. CONSTITUTION:The gate electrode 21 consisting of a ground surface layer 22, a highly conductive layer 23 and an oxidation resistant conductive layer 24 is formed at nearly the same film thickness as the film thickness of an insulating film 9 on a glass substrate 1. The interlayer insulating film 9 as a gate insulating film is formed thereon and further, an ordinary a-Si film 4, an etch stopper layer 5, an n+Si film 6, a source electrode 7 and a drain electrode 8 are formed thereon, by which a TFT is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device having an interlayer insulating film.

[0002]

2. Description of the Related Art In recent years, liquid crystal display elements and electroluminescence display elements capable of displaying with low power have been attracting attention and put into practical use as display elements used in computer terminals such as watches and calculators and personal computers. There is. In particular, recently, a display device having a higher resolution has been demanded, but the conventional simple matrix type display element has a limit in the number of scanning lines, and the display quality becomes higher as the number of scanning lines increases. Since it decreases, M for each pixel
A display element (hereinafter referred to as an active element) by an active matrix driving method, which is provided with an IM (Metal-Insulator-Metal) element, a thin film transistor (hereinafter referred to as TFT), etc., has been actively developed.

As an example of a conventional active element, TF
A schematic sectional view of T is shown in FIG. In FIG. 5, 1 is a glass substrate, 2 is a gate electrode formed on the glass substrate 1,
3 is a gate insulating film formed on the gate electrode 2, 4 is an a-Si film, 5 is an etch stopper layer, and 6 is n + -Si.
A film, 7 is a source electrode, and 8 is a drain electrode. Generally, the gate electrode 2 is integrally connected to and formed with a bus line (not shown), and is formed of Cr, W or the like with a thickness of about 1000 A. The gate insulating film 3 is made of tantalum oxide (Ta2 O5), aluminum oxide (A
12O3) or silicon nitride (Si3 N4).

[0004]

However, the insulating film used in the conventional active element is the gate electrode 2 when the gate insulating film 3 is used as an interlayer insulating film as shown in FIG. Gate insulating film 3 at the step portion due to
Of the gate insulating film 3 becomes thin, or defects such as pinholes occur in the film of the gate insulating film 3, so that the withstand voltage is easily lowered. Therefore, there is a problem that a short circuit easily occurs and the quality is low, and the gate electrode 2 and the drain electrode 7 are caused by static electricity generated in the process of manufacturing an active element.
Between the gate electrode 2 and the source electrode 8 is liable to cause a dielectric breakdown in the gate insulating film 3, resulting in a low manufacturing yield.

Further, it is necessary to keep the wiring resistance value of the bus line low so as to prevent gate delay. If the bus line is formed thick to reduce the wiring resistance value, the bus The thickness of the gate electrode 2, which is a part of the line, is also increased, and the above problem is further increased.
On the other hand, if the width of the bus line is set large for the above purpose, a new problem arises that the aperture ratio of the active element decreases.

The present invention has been made in view of the above problems, and does not cause a short circuit between electrodes facing each other with an interlayer insulating film interposed therebetween, and further, due to static electricity generated in the manufacturing process of a display device, etc. An object of the present invention is to provide a display device capable of preventing dielectric breakdown in an insulating film and increasing the aperture ratio without causing problems such as gate delay.

[0007]

In a display device according to the present invention, an electrode and an insulating film are formed on a substrate with almost the same thickness so that they are adjacent to each other, and an interlayer is formed on the surface of the electrode and the insulating film. It is characterized by having a structure in which an insulating film is formed.

[0008]

Since the display device according to the present invention has a structure in which the interlayer insulating film is formed on the electrode and the insulating film which are formed so as to be adjacent to each other and have substantially the same thickness, the interlayer insulating film is formed at the edge portion of the electrode. Since a uniform film thickness is formed over the entire surface without creating a step, there is no short circuit between electrodes facing each other through the interlayer insulating film, and further, dielectric breakdown of the interlayer insulating film due to static electricity is prevented. And can be manufactured with a high yield. In addition, the thickness of the electrodes can be set arbitrarily, so by increasing the thickness of the electrodes and setting the width of the bus lines, etc. small, the display can be performed without causing problems such as gate delay. The aperture ratio of the device can be increased.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. The same components as those of the conventional example are designated by the same reference numerals to simplify the description. (Embodiment 1) FIG. 1 shows a TF according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view of T, and FIG. 2 shows each step of the manufacturing method of the main part of this TFT. In FIG. 1, 1 is a glass substrate, 21 is a gate electrode formed on the glass substrate 1,
Reference numerals 22 to 24 are laminated members constituting the gate electrode 21, 22 is a base layer formed on the glass substrate 1, and 23 is a base layer.
Is a highly conductive layer formed on the underlayer 22, and 24 is an oxidation resistant conductive layer formed on the highly conductive layer 23. Here, the underlayer 22 is preferably made of a metal such as Cr having high adhesion to the substrate such as the glass substrate 1 and the highly conductive layer 23, and other metals such as Ti, Ti2 Si, Ta2 Si and Pt2 Si which can endure high temperature. It is preferably used, but it may have conductivity such that it can be used as an electrode in a plating bath.

Further, the highly conductive layer 23 is 2 to 7 × 10 -6 Ω-
Those having a resistance of about cm are preferable, and Al, Cu, N
i and the like are preferably used. This highly conductive layer 23 is made of Al
Etc. can be formed by a vacuum deposition method or a sputtering method, but the height of the void portion 10 as shown in FIG.
In the case of μm or more, a means capable of performing selective growth without causing film defects such as pinholes, specifically, a means by a plating method or a metal selectively grown by a CVD method or the like is used as the underlayer 22. It can be formed by using a means for selectively growing.

The oxidation resistant conductive layer 24 may have any function as long as it has a function of preventing thermal oxidation in the subsequent manufacturing process. For example, when the high conductive layer 23 is Cu, Au or the like is preferable, In addition, the highly conductive layer is Au or N
In the case of i, this may also serve as the oxidation resistant conductive layer 24. In FIG. 1, 9 is an insulating film and 31 is a gate.
An interlayer insulating film as a gate insulating film, 4 is an a-Si film, 5 is an etch stopper layer, 6 is an n + -Si film, 7 is a source electrode, and 8 is a drain electrode. Here, the insulating film 9 is preferably made of, for example, SiO2 or SiOx Ny obtained by uniformly coating the sol-gel raw material on the glass substrate 1 and baking it by a spin coating method, a dipping method, or a spray method. .

Next, each step of the method of manufacturing the main part of the TFT will be described with reference to FIG. In this manufacturing method, (1) First, as shown in FIG.
59) A Cr film 20 is formed on top of this by a sputtering method. The Cr film thickness is preferably 200 to 1000A. (2) Next, as shown in FIG. 2B, a pattern of the underlayer 21 is formed by photolithography. (3) Polysilazane ([SiH2 (NH)] n) of 3000 was spin-coated on the substrate thus obtained.
By applying A and baking at a temperature of 500 ° C. while controlling the amount of water, as shown in FIG.
To form. (4) Next, the insulating film 9 is formed by photolithography so that the pattern of the underlayer 21 is exposed by using the reverse pattern of the pattern used in the step (2). The insulating film 9 is etched using buffered hydrofluoric acid. An ECR dry etcher or the like may be used for this etching process. (5) Next, the end portion of the underlayer 21 is connected to a power source with the cathode side as a cathode side, and immersed in a copper plating bath to perform Cu electrolytic plating to form a highly conductive layer 23 of about 2300A. After that, it is immersed in a gold plating bath, and gold electroplating is performed so that the height is almost the same as that of the insulating film 9 to form about 300 A of the oxidation resistant conductive layer 24. Plasma CVD on the substrate obtained by the above manufacturing process
The interlayer insulating film 31 as a gate insulating film by the method
0A is deposited.

Then, a-Si is formed by the plasma CVD method.
The layer 4 is deposited at 1000 A, and Si3 N4 is continuously deposited at 2000 A as an etch stopper, and this Si3 N4 is patterned into a predetermined shape by photolithography to form an etch stopper layer 5. Plasma CVD
The deposition conditions of Si3 N4 by the method are as follows: substrate temperature 350 ° C.,
The pressure was 0.1 Torr, the RF power was 400 W, and the source gases were monosilane (SiH4) and ammonia (NH4).
And hydrogen (H2) are used.

Then, n + -S is formed by the plasma CVD method.
The i layer 6 is formed at a substrate temperature of 250 ° C. and a pressure of 0.4 Torr for 20 times.
00A, a Cr layer of 200A and an Al layer of 2000A are further formed thereon by a sputtering method, and then the Cr layer and the Al layer are further wet-etched by photolithography to form an n + -Si layer 6 and a so-called The drain electrode 8 and the drain electrode 8 are formed.

In the TFT thus obtained, since the interlayer insulating film 31 as the gate insulating film is formed on the gate electrode 21 with no step and with a uniform film thickness, the gate electrode is formed. 21 does not cause a short circuit between the source electrode 7 and the source electrode 7 or between the gate electrode 21 and the drain electrode 8 and has excellent withstand voltage, so that static electricity may be generated in the manufacturing process of the active element. Dielectric breakdown does not occur. Further, in order to reduce the wiring resistance value of the bus line (not shown), the film thickness of the insulating layer 9 and the gate electrode 21 is increased, and at the same time, the width of the bus line (not shown) to which the gate electrode 21 is connected is set to 10 μm. Since the width can be set to the narrower width described below, the aperture ratio of the active element can be greatly improved as compared with the conventional one without causing gate delay.

(Embodiment 2) FIG. 3 is a schematic sectional view of a TFT showing a second embodiment of the present invention. In this TFT, the light-shielding layer 11 which also serves as a base layer of the gate electrode 21 is formed to have a width larger than that of the gate electrode 21 so that light incident from below the substrate 1 does not enter the channel layer. The configuration is the same as that of the first embodiment except that the configuration is cut off. According to this TFT, the light-shielding layer 11 which also serves as a base layer of the gate electrode 21 is formed larger than the width of the gate electrode 21. Therefore, in addition to the effect of the first embodiment, the influence of external light is exerted. It also has the effect of being as small as possible.

(Embodiment 3) FIG. 4 is a schematic sectional view of an MIM element showing a third embodiment of the present invention. This will be described according to the manufacturing process. First, the electrode 25 as the lower electrode and the insulating film 9 were formed on the surface of the glass substrate 1 by the same method as in Example 1. The insulating layer 12 is formed thereon by atomic layer deposition. The insulating layer 12 is formed by placing the substrate in an electric furnace heated to 300 ° C. and repeating the cycle of alternately introducing SiCl4 and water or hydrogen peroxide to obtain an insulating layer 12 made of SiO2 with a thickness of about 200 A. Formed in thickness.

Here, as the insulating layer 12, it is possible to form an atomic layer made of ZnO by repeating a cycle of alternately introducing zinc chloride and water or hydrogen peroxide, and Al2 O3 or the like can be substituted. Of course. Next, the insulating layer 12 was processed into a predetermined pattern by photolithography, an upper electrode 13 was further formed by sputtering, and then a protective film 14 was deposited by a plasma CVD method. This MIM element has the same effect as that of the first embodiment, and also has the effect of realizing a display element having a large area and high reliability.

In the above embodiments, examples in which the structure of the electrode, the insulating film and the interlayer insulating film according to the present invention is applied to a display element have been shown, but the present invention is not limited to these examples. Needless to say, the present invention can be applied to electric elements such as integrated circuits in which electrodes and various electric elements are wired in multiple layers.

[0020]

According to the present invention, since the electrode and the insulating layer of the display device are formed to have the same thickness so that they are adjacent to each other, the interlayer insulating film is formed on the electrode. Since the insulating film can be formed without a step and with a substantially uniform film thickness, and the insulation resistance can be significantly improved, dielectric breakdown due to static electricity, etc. does not occur, and defects such as short circuits do not occur. The quality and reliability of the display device can be significantly improved, and the manufacturing yield of the display device can be improved.
In addition, since the thickness of the electrodes can be set arbitrarily, by increasing the thickness of the electrodes and setting the width of the bus lines and the like small, the aperture ratio of the display device can be increased without causing problems such as gate delay. Can be large.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a first embodiment of a TFT according to the present invention.

2A to 2C are views for explaining a method of manufacturing a main part of the TFT shown in FIG.

FIG. 3 is a schematic sectional view of a second embodiment of a TFT according to the present invention.

FIG. 4 is a schematic cross-sectional view of an MIM showing a third embodiment according to the present invention.

FIG. 5 is a schematic cross-sectional view of a conventional TFT.

[Explanation of symbols]

 1 Glass Substrate 2, 21 Gate Electrode 3 Gate Insulating Film 4 a-Si Film 5 Etch Stopper Layer 6 n + -Si Film 7 Drain Electrode 8 Source Electrode 9 Insulating Film 10 Void 11 Light Shielding Layer 12 Insulating Layer 13 Upper Electrode 14 Protective film 22 Underlayer 23 Highly conductive layer 24 Oxidation resistant conductive layer 25 Electrode (lower electrode)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number in the agency FI Technical indication location H01L 29/784 49/02 8728-4M (72) Inventor Mitsuo Otsu Mitsuo Otsuka, Ota-ku, Tokyo No. 1-7 Alps Electric Co., Ltd. (72) Inventor Issei Takita No. 7 Yukiya Otsuka-cho, Ota-ku, Tokyo No. 7 Alps Electric Co., Ltd. Town No. 1-7 Alps Electric Co., Ltd. (72) Inventor Isao Nakamura No. 1-7 Yukiya Otsuka-cho, Ota-ku, Tokyo Alps Electric Co., Ltd.

Claims (1)

[Claims] 1. A structure in which an electrode and an insulating film are formed on a substrate with substantially the same thickness so as to be adjacent to each other, and an interlayer insulating film is formed on the surfaces of the electrode and the insulating film. A display device characterized by.