JPH06230425A - Liquid crystal display device and its production - Google Patents

Liquid crystal display device and its production

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Publication number
JPH06230425A
JPH06230425A JP1639593A JP1639593A JPH06230425A JP H06230425 A JPH06230425 A JP H06230425A JP 1639593 A JP1639593 A JP 1639593A JP 1639593 A JP1639593 A JP 1639593A JP H06230425 A JPH06230425 A JP H06230425A
Authority
JP
Japan
Prior art keywords
electrode
gate
drain
liquid crystal
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1639593A
Other languages
Japanese (ja)
Inventor
Koji Miyajima
康志 宮島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1639593A priority Critical patent/JPH06230425A/en
Publication of JPH06230425A publication Critical patent/JPH06230425A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To decrease the number of times of peeling photoresists, to prevent shorting and to improve 4 yield by continuously forming respective layers of a TFT and forming a drain electrode, drain line and source electrode of the same material as the material of a display electrode by the same processing. CONSTITUTION:The TFT has the gate electrode integral with the gate line, a gate insulating film which is provided on an insulating substrate so as to cover this gate electrode an amorphous silicon active layer which is provided thereon, two amorphous silicon contact layers which are provided apart from each other thereon and two metallic layers which are provided thereon. The source electrode 25 formed integrally with the display electrode 26 is formed on the one metallic layer of these two metallic layers and the drain electrode 23 which is formed integrally with the drain line 24 and made of the same material as the material of the display electrode 26 is formed on another metallic layer. An org. film of about the same film thickness as the film thickness of the TFT is provided under this display electrode 26 over the entire area of the insulating substrate exclusive of the TFT.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高歩留まりと製造工程
のマスク数の減少を達成した液晶表示装置とその製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a high yield and a reduced number of masks in the manufacturing process, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】近年、アクティブマトリクス型液晶表示
装置は、携帯用TV、ビデオモニタ−液晶プロジェクタ
−、およびOA機器等のディスプレイ装置などに用いら
れ、すでに商品化されている。従来の液晶表示用薄膜ト
ランジスタ基板として、図9に示すようなものがあっ
た。透明な絶縁性基板(50)上にゲ−ト電極(5
1)、ゲ−トライン(52)補助容量電極(53)が設
けられ、これを覆って絶縁性基板(50)全面にゲ−ト
絶縁膜(54)が設けられている。
2. Description of the Related Art In recent years, active matrix liquid crystal display devices have been used in portable TVs, video monitors, liquid crystal projectors, display devices such as office automation equipment, and the like, and have already been commercialized. As a conventional thin film transistor substrate for liquid crystal display, there is one as shown in FIG. A gate electrode (5) is formed on a transparent insulating substrate (50).
1), a gate line (52) is provided with an auxiliary capacitance electrode (53), and a gate insulating film (54) is provided on the entire surface of the insulating substrate (50) so as to cover it.

【0003】このゲ−ト絶縁膜(54)上の前記ゲ−ト
電極(51)に対応する領域には、ノンド−プのアモル
ファスシリコン(以下a−Siと略す)(55)不純物
ド−プのアモルファスシリコン(以下N+a−Siと略
す)(56)(57)、半導体保護膜(58)、ドレイ
ン電極(59)およびソ−ス電極(61)よりなるTF
Tが設けられている。
A non-doped amorphous silicon (hereinafter abbreviated as a-Si) (55) impurity dopant is formed in a region of the gate insulating film (54) corresponding to the gate electrode (51). Of amorphous silicon (hereinafter abbreviated as N + a-Si) (56) (57), a semiconductor protective film (58), a drain electrode (59) and a source electrode (61)
T is provided.

【0004】更に、前記ドレイン電極(59)と一体の
ドレインライン(60)が、前記ゲ−ト絶縁膜(54)
上の前記ゲ−トライン(52)に直交する方向に設けら
れている。また、前記ゲ−ト絶縁膜(54)上の前記ゲ
−トライン(52)と前記ドレライン(60)に囲まれ
た領域には、ITOよりなる表示電極(62)が設けら
れている。この表示電極(62)は、前記ソ−ス電極
(61)と電気的に接続されている。
Further, the drain line (60) integrated with the drain electrode (59) is connected to the gate insulating film (54).
It is provided in a direction orthogonal to the gate line (52) above. In addition, a display electrode (62) made of ITO is provided in a region surrounded by the gate line (52) and the drain line (60) on the gate insulating film (54). The display electrode (62) is electrically connected to the source electrode (61).

【0005】続いて、製造方法を説明する。まず、透明
な絶縁性基板(50)上に、Crなどの金属をスパッタ
リングし、パタ−ン化してゲ−ト電極(51)、これと
一体のゲ−トライン(52)、および補助容量電極(5
3)を形成する。次に、SiNxをプラズマCVD法で
成膜してゲ−ト絶縁膜(54)とし、続いて同様にプラ
ズマCVD法でa−SiおよびSiNxを成膜し、Si
Nxをパタ−ン化して半導体保護膜(58)とする。そ
して、N+a−SiをプラズマCVD法で形成した後、
+a−Siおよびa−Siをエッチングして、TFT
のドレイン部、ソ−ス部及びチャンネル部を形成する。
続いて、ITOをスパッタリングしてパタ−ン化し、表
示電極(62)を形成する。そして、Al/Moをスパ
ッタリングして、パターン化しドレイン電極(59)、
これと一体のドレインライン(60)及びソ−ス電極
(61)を形成する。
Next, the manufacturing method will be described. First, a metal such as Cr is sputtered on a transparent insulating substrate (50) and patterned to form a gate electrode (51), a gate line (52) integrated therewith, and an auxiliary capacitance electrode ( 5
3) is formed. Next, SiNx is formed by a plasma CVD method to form a gate insulating film (54), and subsequently a-Si and SiNx are similarly formed by a plasma CVD method to form Si.
Nx is patterned to form a semiconductor protective film (58). Then, after forming N + a-Si by the plasma CVD method,
Etching N + a-Si and a-Si to form a TFT
Forming a drain portion, a source portion and a channel portion.
Subsequently, ITO is sputtered to form a pattern, and a display electrode (62) is formed. Then, Al / Mo is sputtered to form a patterned drain electrode (59),
A drain line (60) and a source electrode (61) are formed integrally therewith.

【0006】[0006]

【発明が解決しようとする課題】図9で示す従来の液晶
表示装置は、その製造方法において、マスク数が5枚以
上になり製造コストが大きかったた。また、製造過程で
異物が存在する場合これがホトリソグラフィ−工程中、
特にレジスト剥離の際にホ−ルとなり、その後、Al,
Crなどをスパッタリングすると、このホ−ルにこれら
の金属が入りこみショ−トの原因となっていった。
In the conventional liquid crystal display device shown in FIG. 9, the number of masks is 5 or more in the manufacturing method, and the manufacturing cost is high. In addition, if foreign matter is present in the manufacturing process, this is due to the photolithography process,
Especially when the resist is peeled off, it becomes a hole, and then Al,
When Cr or the like was sputtered, these metals got into this hole and caused a short.

【0007】[0007]

【課題を解決するための手段】本発明では、a−Si
層、N+a−Si層およびメタルを連続で成膜すること
と、ドレイン電極、ドレインラインおよびソ−ス電極を
表示電極と同一材料で、同一工程によって形成すること
で前述の課題を解決するものである。
According to the present invention, a-Si is used.
The above problem is solved by continuously forming a layer, an N + a-Si layer and a metal, and forming a drain electrode, a drain line and a source electrode with the same material as the display electrode in the same step. It is a thing.

【0008】[0008]

【作用】ゲ−ト絶縁膜、a−Si、N+a−Si、メタ
ルを連続成膜することにより、TFTアイランドの形成
に関してはマスクが2枚ですむことになり、更にこのう
ちの1枚で表示電極をパタ−ン化するので、全工程でも
最低3枚のマスクで十分ということになる。
[Function] By forming the gate insulating film, a-Si, N + a-Si, and metal continuously, only two masks are required for forming TFT islands, and one of them is used. Since the display electrodes are patterned by means of the above, at least three masks are sufficient for all the steps.

【0009】また、メタル形成前にはフォトリソグラフ
ィ−工程が無いため、たとえ異物が存在していても、ホ
−ルが現れることがないので、メタルがホ−ルに入って
ショ−トが起きることを防止できる。更に、本願では表
示電極の形成時に、これと同一材料でドレインライン、
ドレイン電極、ソ−ス電極を同一工程でITOより形成
し、工程数を削減している。これは、TFTの段差によ
るITOの段切れを生ずるという問題を招くが、本発明
では更に、TFTを除く全領域に有機膜を設け、段差を
無くしてからITOを成膜するという方法によりこの問
題を解決している。
Further, since there is no photolithography process before the metal is formed, the holes do not appear even if foreign matter is present, so the metal enters the holes and a short occurs. Can be prevented. Further, in the present application, when the display electrode is formed, the same material as the drain line,
The drain electrode and the source electrode are formed of ITO in the same step, and the number of steps is reduced. This causes a problem that the step of the ITO is broken due to the step of the TFT, but in the present invention, the problem is further solved by providing an organic film in the entire region except the TFT and removing the step before forming the ITO film. Has been resolved.

【0010】[0010]

【実施例】以下、本発明の実施例を詳細に説明する。図
1から図8は、本願実施例の液晶表示装置の製造方法を
示す断面図である。まず、図1で示す如く透明な絶縁性
基板(10)上に、Crを1500Åの厚さで形成しパ
タ−ン化してゲ−ト電極(11),ゲ−トライン(1
2),および補助容量電極(13)を設ける。
EXAMPLES Examples of the present invention will be described in detail below. 1 to 8 are cross-sectional views showing a method of manufacturing a liquid crystal display device according to an embodiment of the present application. First, as shown in FIG. 1, Cr is formed in a thickness of 1500 Å on a transparent insulating substrate (10) and patterned to form a gate electrode (11) and a gate line (1).
2) and the auxiliary capacitance electrode (13) are provided.

【0011】続いて、ゲート絶縁膜として例えばSiN
x膜(14)を4000Å、a−Si膜(15)を10
00〜2000Å、N+a−Si膜(16)を500
Å、Cr膜(17)を1000Åの厚さで連続成膜す
る。そして、図3のようにTFT部を除いた領域のSi
Nx膜(14)、a−Si膜(15)、N+a−Si膜
(16)、Cr膜(17)をエッチング除去する。この
時使用するマスクは一枚である。
Then, for example, SiN is used as a gate insulating film.
x film (14) is 4000 Å, a-Si film (15) is 10
00-2000Å, N + a-Si film (16) 500
Å, Cr film (17) is continuously formed to a thickness of 1000 Å. Then, as shown in FIG. 3, Si in the region excluding the TFT portion
The Nx film (14), the a-Si film (15), the N + a-Si film (16) and the Cr film (17) are removed by etching. Only one mask is used at this time.

【0012】次に、アクリル樹脂系有機膜(18)を、
TFTを除く全面に被覆する工程がある。まず、アクリ
ル樹脂を、スピンコ−タで基板全面に約3000Åの膜
厚で塗布して、窒素雰囲気中でベ−キングしてアクリル
樹脂膜を形成する。ベ−キングはTFTへの影響と熱処
理効果を考慮して200℃、30分間で行う。また、ホ
ットプレ−トで2〜3分間加熱してもよい。そして、ラ
イトアッシングでアクリル樹脂膜を平坦化しTFT部の
表面を露出させ、図4のようにTFT部の表面とアクリ
ル樹脂系有機膜の表面がなだらかにつながるようにする
また、平坦化の方法としては、有機膜がネガ形の場合、
前記Cr膜(17)をマスクとして背面露光を行い、T
FT上の有機膜を除去する方法もある。
Next, the acrylic resin type organic film (18) is
There is a step of covering the entire surface except the TFT. First, an acrylic resin is applied to the entire surface of the substrate with a spin coater to a thickness of about 3000 Å and baked in a nitrogen atmosphere to form an acrylic resin film. The baking is performed at 200 ° C. for 30 minutes in consideration of the influence on the TFT and the heat treatment effect. Moreover, you may heat for 2-3 minutes with a hot plate. Then, the acrylic resin film is flattened by light ashing so that the surface of the TFT section is exposed so that the surface of the TFT section and the surface of the acrylic resin-based organic film are smoothly connected, as shown in FIG. If the organic film is negative,
Back exposure is performed using the Cr film (17) as a mask, and T
There is also a method of removing the organic film on the FT.

【0013】続いて、前の工程までで、なめらかになっ
た基板表面を下地にしてITO(19)を1000Åの
膜厚で全面に形成し、ドレイン電極(23)、ドレイン
ライン(24)、ソ−ス電極(25)、表示電極(2
6)の各領域にレジスト(20)を被覆して(図5)、
エッチングして図6の構造を得る。この時も、一枚のマ
スクで、ITO(19)、Cr(17)、N+a−Si
(16)をエッチングしていく。
Then, up to the previous step, ITO (19) is formed on the entire surface with a film thickness of 1000 Å using the smoothed substrate surface as a base, and the drain electrode (23), drain line (24), and so on. -Display electrode (25), display electrode (2
Each region of 6) is coated with a resist (20) (FIG. 5),
Etch to obtain the structure of FIG. Also at this time, with one mask, ITO (19), Cr (17), N + a-Si
(16) is etched.

【0014】更に、図7のように表示電極(26)の領
域にレジスト(21)を塗布して、ITOで成るドレイ
ン電極(23)、ドレインライン(24)およびソ−ス
電極(25)の表面にニッケル(22)をメッキする。
ニッケル(22)のメッキは塩化パラジウム中でITO
表面にPdを還元析出させた後、硫酸ニッケル、塩化ニ
ッケル、スルファミン酸ニッケル、塩化アンモニウム、
ほう酸、光沢剤、ピット防止剤等のメッキ液中で、Pd
を触媒にしてNiを折出させてなされる。ITOは抵抗
が大きく電極配線には向けていない。そのため、ITO
で成るドレイン電極(23)ドレインライン(24)、
ソ−ス電極(25)の表面をNiで被覆して電導性を高
めているのである。なお、ニッケルに限らずアルミニウ
ム、モリブデン、チタンなどの金属でもよい。
Further, as shown in FIG. 7, a resist (21) is applied to the area of the display electrode (26) to form a drain electrode (23) made of ITO, a drain line (24) and a source electrode (25). The surface is plated with nickel (22).
Nickel (22) plating is ITO in palladium chloride
After reducing and depositing Pd on the surface, nickel sulfate, nickel chloride, nickel sulfamate, ammonium chloride,
Pd in a plating solution such as boric acid, brightener, pit preventive
Is used as a catalyst and Ni is extruded. ITO has a large resistance and is not aimed at the electrode wiring. Therefore, ITO
A drain electrode (23) consisting of a drain line (24),
The surface of the source electrode (25) is coated with Ni to improve the electrical conductivity. The material is not limited to nickel, but may be a metal such as aluminum, molybdenum, or titanium.

【0015】最後に、レジスト(21)を剥離(図8)
し、図では省略したが、パシベ−ション膜、配向膜を設
け、対向電極が備えられた対向基板と貼り合せ、間に液
晶を注入して本発明の液晶表示装置が完成する。本発明
の特徴は、第1に、SiNx膜(14)a−Si膜(1
5)、N+a−Si膜(16)、Cr膜(17)を連続
成膜し、少なくともCr膜(17)成膜直前に、フォト
リソグラフィ−が行われない製造方法にある。これによ
り、ホ−ルが生じて、そこに電極材料が入り込むことに
よるゲ−ト・ドレイン間およびゲ−ト・ソ−ス間のショ
−トを防ぐことができる。つまり、Cr膜(17)は、
電極であると同時に、a−Si膜(15)、N+a−S
i(16)の保護膜でもある。特にCrが用いられてい
るのは、強度やエッチングの際の耐薬品性を考慮にいれ
てのことである。Crが保護膜となってレジストの塗布
と剥離、およびエッチングの際に異物が存在している場
合、これらがとれてホ−ルになることを防ぐものであ
る。
Finally, the resist (21) is peeled off (FIG. 8).
Although not shown in the figure, a passivation film and an alignment film are provided, the substrate is bonded to a counter substrate provided with a counter electrode, and liquid crystal is injected therebetween to complete the liquid crystal display device of the present invention. The first feature of the present invention is that the SiNx film (14) a-Si film (1
5), the N + a-Si film (16) and the Cr film (17) are continuously formed, and the photolithography is not performed at least immediately before the formation of the Cr film (17). As a result, it is possible to prevent the short between the gate and the drain and between the gate and the source due to the generation of the hole and the entry of the electrode material into the hole. That is, the Cr film (17) is
At the same time as the electrode, a-Si film (15), N + a-S
It is also a protective film for i (16). In particular, Cr is used in consideration of strength and chemical resistance during etching. When Cr is used as a protective film and foreign matter is present during resist coating, peeling, and etching, it prevents the foreign matter from becoming a hole.

【0016】第2に、表示電極(26)、ドレイン電極
(23)、ソ−ス電極(25)およびドレインライン
(24)を表示電極(26)と同一材料、ここではIT
Oで形成されているところにある。このため、従来例の
ようにメタルで成るソ−ス電極(61)とITOで成る
表示電極(62)の間の電気的コンタクトが、マスク合
せの際のずれてよって失われることを防げる。よって、
マスク合わせ精度の低い安い露光機が使用でき、低コス
ト化が可能となる。また、この場合ITOが基板面から
TFTの最上層につながっているため、TFTの段差に
よるITOの段切れが生じやすくなるという問題がおこ
る。図10はアクリル樹脂系有機膜を設けていない場合
の断面図である。図のAの部分でITOの段切れ、Bの
部分では、ITOの下地との接着不良が生じやすい。こ
のため本願では、ITOの下部にアクリル樹脂系有機膜
(18)を設けて段差を無くしてITOの段切れを防い
でいる。
Second, the display electrode (26), the drain electrode (23), the source electrode (25) and the drain line (24) are made of the same material as the display electrode (26), here IT.
It is formed of O. Therefore, it is possible to prevent the electrical contact between the source electrode (61) made of metal and the display electrode (62) made of ITO as in the conventional example from being lost due to misalignment during mask alignment. Therefore,
An inexpensive exposure machine with low mask alignment accuracy can be used, and the cost can be reduced. Further, in this case, since the ITO is connected to the uppermost layer of the TFT from the surface of the substrate, there is a problem that the step of the ITO is likely to be broken due to the step of the TFT. FIG. 10 is a cross-sectional view when the acrylic resin-based organic film is not provided. In the portion A in the drawing, the ITO step is broken, and in the portion B, defective adhesion of the ITO to the base is likely to occur. Therefore, in the present application, an acrylic resin organic film (18) is provided below the ITO to eliminate the step and prevent the ITO from breaking.

【0017】第3に、前述の製造工程の説明から明らか
なように本実施例のTFT基板の製造に要するマスクは
3枚と、従来に比べて著しく少なくなっている。
Thirdly, as is clear from the above description of the manufacturing process, the number of masks required for manufacturing the TFT substrate of this embodiment is three, which is significantly smaller than the conventional mask.

【0018】[0018]

【発明の効果】以上の説明から明らかなように、本発明
の構造およびその製造方法により、TFT基板の製造に
要するマスクは端子部のコンタクトホ−ル形成用のマス
クも含めて最低4枚に減った。これは、マスク合せの際
のずれが原因の不良が、減少することになった。また、
ホトレジストを剥離する回数が減り、ショートの防止に
つながり、歩留まりが向上した。
As is apparent from the above description, by the structure and the manufacturing method of the present invention, the number of masks required for manufacturing the TFT substrate is at least four, including the mask for forming the contact hole of the terminal portion. decreased. This reduces defects caused by misalignment during mask alignment. Also,
The number of times the photoresist is peeled off has been reduced, leading to the prevention of short circuits and improving the yield.

【0019】更に、絶縁性基板上のTFTを除く全領域
にアクリル樹脂系有機膜を設けることによりTFTの突
出がなくなり、本願の特徴の1つがあるところの、表示
電極、ドレインラインおよびドレイン電極が一体でIT
Oより成っている構成において、表示電極とソ−ス電
極、およびドレインラインとドレイン電極が、極端な湾
曲がなく、なめらかにつながることになった。これによ
りITOの段切れが無くなり、歩留まりが向上した。
Further, by providing an acrylic resin type organic film on the entire area of the insulating substrate except the TFT, the projection of the TFT is eliminated, and the display electrode, the drain line and the drain electrode, which is one of the features of the present invention, are formed. IT in one
In the structure made of O, the display electrode and the source electrode, and the drain line and the drain electrode are smoothly connected without any extreme curvature. As a result, the ITO breakage was eliminated and the yield was improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の製造工程の断面図である。FIG. 1 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【図2】本発明の実施図の製造工程の断面図である。FIG. 2 is a cross-sectional view of a manufacturing process according to an embodiment of the present invention.

【図3】本発明の実施例の製造工程の断面図である。FIG. 3 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【図4】本発明の実施例の製造工程の断面図である。FIG. 4 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【図5】本発明の実施例の製造工程の断面図である。FIG. 5 is a cross-sectional view of the manufacturing process of the example of the present invention.

【図6】本発明の実施例の製造工程の断面図である。FIG. 6 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【図7】本発明の実施例の製造工程の断面図である。FIG. 7 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【図8】本発明の実施例の製造工程の断面図である。FIG. 8 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【図9】従来の液晶表示装置の断面図である。FIG. 9 is a cross-sectional view of a conventional liquid crystal display device.

【図10】従来の液晶表示装置の断面図である。FIG. 10 is a cross-sectional view of a conventional liquid crystal display device.

【符号の説明】[Explanation of symbols]

10 絶縁性基板 11 ゲ−ト電極 12 ゲ−トライン 13 補助容量電極 14 SiNa 15 a−Si 16 N+a−Si 17 Cr 18 アクリル樹脂系有機膜 19 ITO 20,21 レジスト 22 Ni 23 ドレイン電極 24 ドレインライン 25 ソ−ス電極 26 表示電極10 Insulating Substrate 11 Gate Electrode 12 Gate Line 13 Auxiliary Capacitance Electrode 14 SiNa 15 a-Si 16 N + a-Si 17 Cr 18 Acrylic Resin Organic Film 19 ITO 20, 21 Resist 22 Ni 23 Drain Electrode 24 Drain Line 25 Source electrode 26 Display electrode

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 透明な絶縁性基板と、この上に設けられ
た複数のゲ−トラインと、このゲ−トラインと直行する
方向に設けられた複数のドレインラインと、前記ゲ−ト
ラインとドレインラインの交点にマトリクス状に設けら
れたTFTスイッチング素子と表示電極とを少なくとも
有する液晶表示装置において、 前記TFTは、前記ゲ−トラインと一体のゲ−ト電極
と、このゲ−ト電極を覆うようにして前記絶縁性基板上
に設けられたゲ−ト絶縁膜と、この上に設けられたアモ
ルファスシリコン活性層と、この上に互いに離間して設
けられた二つのアモルファスシリコンコンタクト層と、
これの上に設けられた二つのメタル層と、このうち一方
のメタル層上に、前記表示電極と一体で形成されるソ−
ス電極と、もう一方のメタル層上に前記ドレイラインと
一体であり、前記表示電極と同一材料で成るドレイン電
極から成り、 前記表示電極の下に前記TFTを除く前記絶縁性基板全
域にわたって、前記TFTと同程度の膜厚の有機膜が設
けられていることを特徴とした液晶表示装置。
1. A transparent insulating substrate, a plurality of gate lines provided thereon, a plurality of drain lines provided in a direction perpendicular to the gate lines, the gate lines and the drain lines. In a liquid crystal display device having at least a TFT switching element and a display electrode provided in a matrix at intersections of the above, the TFT has a gate electrode integral with the gate line, and covers the gate electrode. A gate insulating film provided on the insulating substrate, an amorphous silicon active layer provided on the gate insulating film, and two amorphous silicon contact layers provided apart from each other on the active layer.
Two metal layers provided on top of this, and a source formed integrally with the display electrode on one of the metal layers.
A drain electrode that is integral with the drain line on the other metal layer and is made of the same material as the display electrode, and is formed under the display electrode over the entire insulating substrate except the TFT. A liquid crystal display device, characterized in that an organic film having a film thickness similar to that of a TFT is provided.
【請求項2】 前記表示電極はITOよりなり、前記ソ
−ス電極、前記ドレイン電極および前記ドレインライン
表面には抵抗の低い導電材料が形成されていることを特
徴とした請求項1記載の液晶表示装置
2. The liquid crystal according to claim 1, wherein the display electrode is made of ITO, and a conductive material having a low resistance is formed on the surface of the source electrode, the drain electrode and the surface of the drain line. Display device
【請求項3】 前記導電材料は、ニッケルを使用するこ
とを特徴とした請求項2記載の液晶表示装置。
3. The liquid crystal display device according to claim 2, wherein the conductive material is nickel.
【請求項4】 前記有機膜はアクリル樹脂系有機膜から
なることを特徴とする請求項1、請求項2、または請求
項3記載の液晶表示装置。
4. The liquid crystal display device according to claim 1, wherein the organic film is an acrylic resin-based organic film.
【請求項5】 透明な絶縁性基板上に、ゲ−ト電極およ
びゲ−トラインを形成する工程と、このゲ−ト電極を少
なくとも覆うゲ−ト絶縁膜を形成する工程とこの絶縁膜
上の前記ゲ−ト電極に対応する領域に、アモルファスシ
リコン活性層アモルファスシリコンコンタクト層および
メタル層より成るTFTを形成する工程と、このTFT
を除いた前記絶縁性基板上全面に、このTFTと同程度
の厚さの有機膜を設ける工程と、この有機膜上の前記ゲ
−トラインと前記ドレインラインに囲まれた領域に設け
られ、前記メタル層のソ−ス部と電気的に接続する表示
電極と、この表示電極と同一材料で成り、前記メタル層
のドレイン部と電気的に接続するドレインラインを前記
ゲ−トラインと交差する方向に設ける工程を少なくとも
有する液晶表示装置の製造方法。
5. A step of forming a gate electrode and a gate line on a transparent insulating substrate, a step of forming a gate insulating film which covers at least the gate electrode, and a step of forming a gate insulating film on the insulating film. Forming a TFT composed of an amorphous silicon active layer, an amorphous silicon contact layer and a metal layer in a region corresponding to the gate electrode;
A step of forming an organic film having the same thickness as this TFT on the entire surface of the insulating substrate except for the above, and a step of forming an organic film on the organic film in a region surrounded by the gate line and the drain line. A display electrode electrically connected to the source portion of the metal layer, and a drain line made of the same material as the display electrode and electrically connected to the drain portion of the metal layer are arranged in a direction intersecting the gate line. A method for manufacturing a liquid crystal display device, which comprises at least a step of providing.
【請求項6】 前記表示電極の材料はITOを使用し、
前記ソ−ス部、前記ドレイン部および前記ドレインライ
ン表面には抵抗の低い導電材料を形成する工程があるこ
とを特徴とした請求項5記載の液晶表示装置の製造方
法。
6. The material of the display electrode is ITO,
6. The method of manufacturing a liquid crystal display device according to claim 5, wherein there is a step of forming a conductive material having low resistance on the surface of the source portion, the drain portion and the surface of the drain line.
【請求項7】 前記導電材料はニッケルを使用すること
を特徴とした請求項6記載の液晶表示装置の製造方法。
7. The method for manufacturing a liquid crystal display device according to claim 6, wherein the conductive material is nickel.
【請求項8】 前記有機膜はアクリル樹脂系有機膜を使
用することを特徴とする請求項5、請求項6または請求
項7記載の液晶表示装置の製造方法。
8. The method for manufacturing a liquid crystal display device according to claim 5, wherein the organic film is an acrylic resin-based organic film.
JP1639593A 1993-02-03 1993-02-03 Liquid crystal display device and its production Pending JPH06230425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1639593A JPH06230425A (en) 1993-02-03 1993-02-03 Liquid crystal display device and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1639593A JPH06230425A (en) 1993-02-03 1993-02-03 Liquid crystal display device and its production

Publications (1)

Publication Number Publication Date
JPH06230425A true JPH06230425A (en) 1994-08-19

Family

ID=11915061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1639593A Pending JPH06230425A (en) 1993-02-03 1993-02-03 Liquid crystal display device and its production

Country Status (1)

Country Link
JP (1) JPH06230425A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09105925A (en) * 1995-10-12 1997-04-22 Hitachi Ltd Liquid crystal display device and its production
JP2000194012A (en) * 1998-12-25 2000-07-14 Fujitsu Ltd Production of thin-film transistor matrix and thin-film transistor matrix
JP2003157027A (en) * 2001-07-27 2003-05-30 Semiconductor Energy Lab Co Ltd Semiconductor device and light emitting device
US6730970B1 (en) * 1999-11-16 2004-05-04 Nec Lcd Technologies, Ltd. Thin film transistor and fabrication method of the same
JP2006227649A (en) * 2006-05-17 2006-08-31 Advanced Display Inc Liquid crystal display and manufacturing method therefor
JP2006227648A (en) * 2006-05-17 2006-08-31 Advanced Display Inc Liquid crystal display and manufacturing method therefor
US8149346B2 (en) 2005-10-14 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09105925A (en) * 1995-10-12 1997-04-22 Hitachi Ltd Liquid crystal display device and its production
JP2000194012A (en) * 1998-12-25 2000-07-14 Fujitsu Ltd Production of thin-film transistor matrix and thin-film transistor matrix
US6730970B1 (en) * 1999-11-16 2004-05-04 Nec Lcd Technologies, Ltd. Thin film transistor and fabrication method of the same
JP2003157027A (en) * 2001-07-27 2003-05-30 Semiconductor Energy Lab Co Ltd Semiconductor device and light emitting device
JP2004061825A (en) * 2001-07-27 2004-02-26 Semiconductor Energy Lab Co Ltd Method for manufacturing semiconductor device and light emitting device
US6929986B2 (en) 2001-07-27 2005-08-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and method of manufacturing the same
US8576347B2 (en) 2005-10-14 2013-11-05 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US8149346B2 (en) 2005-10-14 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US8885114B2 (en) 2005-10-14 2014-11-11 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US9773818B2 (en) 2005-10-14 2017-09-26 Semiconductor Energy Laboratory Co., Ltd. Display device having transparent conductive film and metal film
US10847547B2 (en) 2005-10-14 2020-11-24 Semiconductor Energy Laboratory Co., Ltd. Display device having transparent conductive film and metal film
US11296124B2 (en) 2005-10-14 2022-04-05 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US11901370B2 (en) 2005-10-14 2024-02-13 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2006227648A (en) * 2006-05-17 2006-08-31 Advanced Display Inc Liquid crystal display and manufacturing method therefor
JP2006227649A (en) * 2006-05-17 2006-08-31 Advanced Display Inc Liquid crystal display and manufacturing method therefor

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