JPS61164267A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS61164267A JPS61164267A JP608585A JP608585A JPS61164267A JP S61164267 A JPS61164267 A JP S61164267A JP 608585 A JP608585 A JP 608585A JP 608585 A JP608585 A JP 608585A JP S61164267 A JPS61164267 A JP S61164267A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- thin film
- film transistor
- semiconductor film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims abstract description 70
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000001590 oxidative effect Effects 0.000 claims abstract description 8
- 239000005360 phosphosilicate glass Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract 3
- 239000011574 phosphorus Substances 0.000 abstract 3
- 239000005368 silicate glass Substances 0.000 abstract 3
- 239000006185 dispersion Substances 0.000 abstract 1
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910017604 nitric acid Inorganic materials 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- FGIUAXJPYTZDNR-UHFFFAOYSA-N potassium nitrate Chemical compound [K+].[O-][N+]([O-])=O FGIUAXJPYTZDNR-UHFFFAOYSA-N 0.000 description 2
- 235000014548 Rubus moluccanus Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004323 potassium nitrate Substances 0.000 description 1
- 235000010333 potassium nitrate Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、液晶表示装置に用いられる薄膜トランジスタ
の製造方法に関し特に、トランジスタ特性が均一で信頼
性の高い薄膜トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film transistor used in a liquid crystal display device, and particularly to a method for manufacturing a thin film transistor with uniform transistor characteristics and high reliability.
（従来技術とその問題点）
近年、オフィスオートメーションの進展に伴い、マンマ
シンインターフヱイスとしての表示テハイスの画素数の
大容量化が活発に進められている。(Prior art and its problems) In recent years, with the progress of office automation, efforts have been made to increase the number of pixels in display technologies used as man-machine interfaces.
液晶ティスプレィにおいても液晶をスイッチングするだ
めの薄膜トランジスタの開発が盛んである。In the field of liquid crystal displays, thin film transistors for switching liquid crystals are being actively developed.
従来の液晶表示用薄膜トランジスタの製造方法の１例と
して特公昭５６−１３５９６８に示されたものが知られ
ている。第２図に前記従来の製造方法による薄膜トラン
ジスタの断面を示す模式図を示す。As an example of a conventional method for manufacturing a thin film transistor for liquid crystal display, the method disclosed in Japanese Patent Publication No. 56-135968 is known. FIG. 2 is a schematic diagram showing a cross section of a thin film transistor manufactured by the conventional manufacturing method.
この従来の薄膜トランジスタの製造方法は、絶縁基板１
上にゲート電極２、ゲート絶縁膜３．シリコン半導体膜
４、ｎ１シリコン膜を順次形成し、チャンネルとなるシ
リコン半導体膜４上のｎ“シリコン膜をフッ酸、硝酸、
酢酸の混合液にょシエッチングして除去し第１のｎ１シ
リコン膜５と第２のｎ＋シリコン膜６とを電気的に分離
し、第１のｎ＋シリコン膜５にドレイン電極７ｆ：電気
的に接続し、第２のｎ’／リコン膜６にソース電極８と
液晶表示のだめの透明電極９とを電気的に接続するもの
である。従来の薄膜トランジスタの製造方法ではチャン
ネルとなる半導体膜４上のｎ１シリコン膜をフッ酸、硝
酸、酢酸の混合液でエツチングするため。This conventional thin film transistor manufacturing method consists of an insulating substrate 1
A gate electrode 2, a gate insulating film 3. A silicon semiconductor film 4 and an n1 silicon film are sequentially formed, and the n" silicon film on the silicon semiconductor film 4, which will become a channel, is treated with hydrofluoric acid, nitric acid,
The first n1 silicon film 5 and the second n+ silicon film 6 are electrically separated by etching with a mixed solution of acetic acid, and the drain electrode 7f is electrically connected to the first n+ silicon film 5. The source electrode 8 and the transparent electrode 9 of the liquid crystal display are electrically connected to the second n'/recon film 6. In the conventional manufacturing method of thin film transistors, the n1 silicon film on the semiconductor film 4, which becomes the channel, is etched with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid.
ｎシリコン膜とシリコン半導体膜とのエツチングスピー
ドがほぼ等しくｎ＋シリコン膜のみを選択的にエツチン
グすることができない。したがって液晶ディスプレイに
用いるような大面積の基板を均一にエツチングするのが
困難である。薄膜トランジスタ特性はシリコン半導体膜
の膜厚に対して影響を受けるためＴＰＴ特性は不均一と
なシこのため液晶ディスプレイの表示特性は劣化すると
いう欠点があったコまたシリコン半導体上部は、エツチ
ングしたため多数の欠陥が生じ、この欠陥のためＴＰＴ
特性の信頼性は低下するという欠点があった。この欠陥
はエツチング後にパッシベーション膜を形成することに
よジ減少できるが、シリコン半導体膜とパッシベーショ
ン膜との界面には多数の界面準位が生じ薄膜トランジス
タの特性はばらつくという欠点があった。Since the etching speed of the n silicon film and the silicon semiconductor film are almost equal, it is not possible to selectively etch only the n+ silicon film. Therefore, it is difficult to uniformly etch large-area substrates such as those used in liquid crystal displays. Since the thin film transistor characteristics are affected by the thickness of the silicon semiconductor film, the TPT characteristics are not uniform, which has the disadvantage of deteriorating the display characteristics of the liquid crystal display.Also, the upper part of the silicon semiconductor has been etched, resulting in a large number of defects. A defect occurs and due to this defect TPT
There was a drawback that the reliability of the characteristics decreased. Although this defect can be reduced by forming a passivation film after etching, there is a drawback that a large number of interface states are generated at the interface between the silicon semiconductor film and the passivation film, resulting in variations in the characteristics of the thin film transistor.
（発明の目的）
本発明は、このような従来の欠点を除去し、トランジス
タ特性が均一で信頼性の高い薄膜トランジスタの製造方
法を提供することにある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a thin film transistor having uniform transistor characteristics and high reliability by eliminating such conventional drawbacks.
（発明の構成）
本発明は、絶縁基板上にゲート電極を形成する工程と、
ゲート絶縁膜を形成する工程と、シリコン半導体膜を形
成する工程と、該シリコン半導体膜上にｎ＋シリコン膜
を形成し、該ｎ１シリコン膜を第１のｎ＋シリコン膜と
第２のｎ“シリコン膜に電気的に分離する工程と、前記
第１のｎ”シリコン膜に、（３）
ドレイン電極を前記第２のｎ＋シリコン膜にソース電極
をそれぞれ電気的に接続する工程とから少なくともなる
薄膜トランジスタの製造方法において、ｎ゛シリコン膜
酸化させて形成したリンシリケイトガラスを用いて前記
第１および第２のｎ１シリコン膜を電気的に分離する方
法を用いることを特徴とする薄膜トランジスタの製造方
法である。(Structure of the Invention) The present invention includes a step of forming a gate electrode on an insulating substrate;
a step of forming a gate insulating film; a step of forming a silicon semiconductor film; forming an n+ silicon film on the silicon semiconductor film; and (3) electrically connecting a drain electrode and a source electrode to the second n+ silicon film, respectively. The method of manufacturing a thin film transistor is characterized in that the first and second n1 silicon films are electrically isolated using phosphosilicate glass formed by oxidizing an n1 silicon film.
さらに前記ｎ１シリコン膜を酸化させてリンシリケイト
ガラスを形成する方法として陽極酸化法を用いるとよい
。Further, it is preferable to use an anodic oxidation method as a method for oxidizing the n1 silicon film to form phosphosilicate glass.
（構成の詳細な説明）
本発明は、上述の方法を用いることにより従来技術の問
題点を解決した。本発明の製造方法による薄膜トランジ
スタの断面を示す模式図を第１図に示す口車発明のトラ
ンジスタの製造方法によればｎ９シリコン膜を酸化させ
てリンシリケイトガラス１０を形成するため、シリコン
半導体膜４との界面にはほとんど界面準位が発生しない
。またｎ＋シリコン膜はシリコン半導体膜よりも電気抵
抗が極めて低いため選択的にｎ＋シリコン膜のみを酸化
できる。このためシリコン半導体膜の厚みは大面積にわ
たシ均一となシ薄膜トランジスタの特性のバラツキはほ
とんどない。(Detailed Description of Configuration) The present invention solves the problems of the prior art by using the above method. A schematic diagram showing a cross section of a thin film transistor according to the manufacturing method of the present invention is shown in FIG. Almost no interface states are generated at the interface with. Furthermore, since the n+ silicon film has an extremely lower electrical resistance than the silicon semiconductor film, only the n+ silicon film can be selectively oxidized. Therefore, the thickness of the silicon semiconductor film is uniform over a large area, and there is almost no variation in the characteristics of the thin film transistor.
（実施例）
以下本発明の実施例について第１図を参照して詳細に説
明する。ガラス基板１上にクロムｖｉｏｏ。(Example) Hereinafter, an example of the present invention will be described in detail with reference to FIG. Chrome vioo on glass substrate 1.
＾蒸着し、フォトレジスト法により所定パターンにエツ
チングしてゲート電極２を形成した後、ゲート絶縁膜３
として窒化シリコンを３０００１．半導体膜４としてア
モルファスシリコンを３０００Ｘ％♂シリコン膜として
リンドープアモルファスシリコン５００１ｅプラズマＣ
ＶＤ法により連続形成した。After forming the gate electrode 2 by vapor depositing and etching into a predetermined pattern using a photoresist method, a gate insulating film 3 is formed.
Silicon nitride as 30001. Amorphous silicon is used as the semiconductor film 4, and phosphorus-doped amorphous silicon 5001e is used as the 3000X%♂♂ silicon film, plasma C.
Continuous formation was performed by the VD method.
ノンドープアモＡ／７アスシリコンの比抵抗は１０麺程
度、リンドープアモルファスシリコンの比抵抗は１０３
ｒＬｃｒｎ程度であった。その後ｎ１シリコン膜。The specific resistance of non-doped amorphous silicon is about 10, and the specific resistance of phosphorus-doped amorphous silicon is 103.
It was about rLcrn. Then n1 silicon film.
半導体膜４を液晶ディスプレイを透過型とするためおよ
び寄生薄膜トランジスタが生じないように所定パターン
に加工しその上面にクロムｅ２０００＾蒸着しバター二
′ングしてドレイン電極７、ソース電極８を形成した後
、Ｉ Ｔ Ｏ１０００ｉｔｌ−Ａｒスバッタしパターニ
ングして透明電極９を形成した。After processing the semiconductor film 4 into a predetermined pattern in order to make the liquid crystal display transparent and to prevent the generation of parasitic thin film transistors, chromium e2000^ is deposited on the upper surface and buttered to form a drain electrode 7 and a source electrode 8. , I TO 1000 itl-Ar sputtering and patterning to form a transparent electrode 9.
その後チャンネルとなるノンドープアモルファスシリコ
ン上のリンドープアモルファスシリコン全陽極酸化し、
第１のｎ＋シリコン膜５と第２のｎ＋シリコン膜６と全
電気的に分離形成した。陽極酸化は、エチレングリコー
ル１１！中に硝酸カリウム１０ｇを溶かした溶液中でド
レイン電極に電圧１００〜２００ｉ−印加し、ＡＭＩの
白色光音り／ドープアモルファスシリコンに照射して行
なった。このようにして製造した薄膜トランジスタと従
来の薄膜トランジスタを比較するためチャンネルとなる
ノンドープアモルファスシリコン上のリンドープアモル
ファスシリコン全フッ酸、硝酸、酢酸の混合液を用いて
エツチング除去したものも同様のプロセスで製造した。After that, the phosphorus-doped amorphous silicon is fully anodized on the non-doped amorphous silicon that will become the channel.
The first n+ silicon film 5 and the second n+ silicon film 6 were formed to be completely electrically separated. Anodic oxidation is ethylene glycol 11! A voltage of 100 to 200 i was applied to the drain electrode in a solution containing 10 g of potassium nitrate, and the white light of the AMI/doped amorphous silicon was irradiated. In order to compare thin film transistors manufactured in this way with conventional thin film transistors, phosphorus-doped amorphous silicon on non-doped amorphous silicon that will serve as a channel was etched away using a mixture of hydrofluoric acid, nitric acid, and acetic acid, and was also manufactured using the same process. did.
トランジスタ特性測定は５００×５００素子のマトリク
スアレイについて行った。The transistor characteristics were measured on a matrix array of 500×500 elements.
従来の薄膜トランジスタの特性は、 Ｉｏｎ、 Ｉ
ｏｆｆとも±２０％程度のばらつきが見られたが、本発
明の薄膜トランジスタでは±２％以内であった。これは
、フッ酸、硝酸、酢酸の混合液を用いてリンドープアモ
ルファスシリコンをエツチングする場合ノンドープ膜と
のエツチング選択比がとれずノンドープ膜もエツチング
されてしまうため、エツチング速度のばらつきがえのま
まトランジスタ特性に影響を与えるためである。一方直
流電圧をゲートおよびドレイン・ソース間にそれぞれ１
５Ｖ印加した場合のドレイン・ソース間電流の変化を初
期値’ｉｌ＋ｏｏ％ととし９０％となる時間を測定した
。The characteristics of conventional thin film transistors are Ion, I
Although a variation of about ±20% was observed for both off and off, the variation was within ±2% in the thin film transistor of the present invention. This is because when etching phosphorous-doped amorphous silicon using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, the etching selectivity with the non-doped film cannot be maintained and the non-doped film is also etched, resulting in variations in the etching rate. This is because it affects transistor characteristics. On the other hand, a DC voltage of 1 is applied between the gate and the drain and source.
The change in the drain-source current when 5V was applied was set to the initial value 'il+oo%, and the time to reach 90% was measured.
従来の薄膜トランジスタでは１０時間程度でありたが本
発明の薄膜トランジスタでは１０００時間程度と大幅に
信頼性が向上した。これは ’ｈ、ｙ リコンを酸化さ
せてチャンネルとなるアモルファスシリコン上にリンシ
リケイトガラスを形成したため界面準位が大巾に減少し
たためである。The reliability of the conventional thin film transistor was approximately 10 hours, but the reliability of the thin film transistor of the present invention was significantly improved to approximately 1000 hours. This is because 'h,y silicon is oxidized to form phosphosilicate glass on the amorphous silicon that serves as the channel, and the interface level is greatly reduced.
（発明の効果）
本発明による薄膜トランジスタの製造方法を用いれば薄
膜トランジスタ特性が均一で信頼性の高い薄膜トランジ
スタを製造できる。これはｎシリコン膜を酸化させてリ
ンシリケイトガラスを製造するためチャンネル層上の半
導体膜の膜厚が均一となシまた半導体膜とリンシリケイ
トガラスとの界面準位も非常に少なくなるためである。(Effects of the Invention) By using the method for manufacturing a thin film transistor according to the present invention, a thin film transistor with uniform thin film transistor characteristics and high reliability can be manufactured. This is because phosphosilicate glass is manufactured by oxidizing the n-silicon film, so the thickness of the semiconductor film on the channel layer is not uniform, and the interface states between the semiconductor film and the phosphosilicate glass are also very small. .
以上詳細に述べた通り、本発明による薄膜トランジスタ
の製造方法を用いれば特性が均一で信頼性の高い薄膜ト
ランジスタを提供できる。As described above in detail, by using the method for manufacturing a thin film transistor according to the present invention, a thin film transistor with uniform characteristics and high reliability can be provided.
第１図は本発明の製造方法による薄膜トランジスタの断
面を示す模式図、第２図は従来の製造方法による薄膜ト
ランジスタの断面を示す模式図である。
図において、１・・・絶縁基板、２・・・ゲート電極、
３・・・ゲート絶縁膜、４・・・シリコン半導体膜、訃
・・第１のｎシリコン膜、６・・・第２のｎ／リコン膜
、７・・・ドレイン電極、８・・・ソニス電極、９・・
・透明電極、１０・・・ｎシリコン膜を酸化させて形成
したリンシリケイトガラスをそれぞれ示す。
第１図
第２図FIG. 1 is a schematic diagram showing a cross section of a thin film transistor manufactured by the manufacturing method of the present invention, and FIG. 2 is a schematic diagram showing a cross section of a thin film transistor manufactured by a conventional manufacturing method. In the figure, 1... insulating substrate, 2... gate electrode,
3... Gate insulating film, 4... Silicon semiconductor film, D... First n silicon film, 6... Second n/recon film, 7... Drain electrode, 8... Sonis Electrode, 9...
・Transparent electrode, phosphosilicate glass formed by oxidizing a 10...n silicon film is shown. Figure 1 Figure 2
Claims (2)
ト絶縁膜を形成する工程と、シリコン半導体膜を形成す
る工程と、該シリコン半導体膜上にｎ＾＋シリコン膜を
形成し該ｎ＾＋シリコン膜を第１のｎ＾＋シリコン膜と
第２のｎ＾＋シリコン膜に電気的に分離する工程と、前
記第１のｎ＾＋シリコン膜にドレイン電極を前記第２の
ｎ＾＋シリコン膜にソース電極をそれぞれ電気的に接続
する工程とから少なくともなる薄膜トランジスタの製造
方法において、ｎ＾＋シリコン膜を酸化させて形成した
リンシリケイトガラスを用いて前記第１および第２のｎ
＾＋シリコン膜を電気的に分離する方法を用いることを
特徴とする薄膜トランジスタの製造方法。(1) A step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film, a step of forming a silicon semiconductor film, a step of forming an n^+ silicon film on the silicon semiconductor film, and a step of forming the n^+ silicon film on the silicon semiconductor film. + electrically separating the silicon film into a first n^+ silicon film and a second n^+ silicon film, and connecting a drain electrode to the first n^+ silicon film to the second n^+ silicon film; In the method for manufacturing a thin film transistor, which comprises at least the step of electrically connecting a source electrode to a silicon film, the first and second n
^+ A method for manufacturing a thin film transistor characterized by using a method of electrically isolating a silicon film.
トガラスを形成する方法として陽極酸化法を用いること
を特徴とする前記第１項記載の薄膜トランジスタの製造
方法。(2) The method for manufacturing a thin film transistor according to item 1, wherein an anodic oxidation method is used as a method for oxidizing the n^+ silicon film to form phosphosilicate glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP608585A JPS61164267A (en) | 1985-01-17 | 1985-01-17 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP608585A JPS61164267A (en) | 1985-01-17 | 1985-01-17 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61164267A true JPS61164267A (en) | 1986-07-24 |
Family
ID=11628703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP608585A Pending JPS61164267A (en) | 1985-01-17 | 1985-01-17 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61164267A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0361609A2 (en) * | 1988-09-30 | 1990-04-04 | Philips Electronics Uk Limited | Thin-film transistors, their method of manufacture, and display device using such transistors |
| JPH0669233A (en) * | 1991-12-03 | 1994-03-11 | Samsung Electron Co Ltd | Manufacture of semiconductor device |
| US5334859A (en) * | 1991-09-05 | 1994-08-02 | Casio Computer Co., Ltd. | Thin-film transistor having source and drain electrodes insulated by an anodically oxidized film |
| FR2718885A1 (en) * | 1994-04-15 | 1995-10-20 | Thomson Lcd | Method for manufacturing a reverse stage TFT. |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57103358A (en) * | 1980-12-18 | 1982-06-26 | Matsushita Electric Ind Co Ltd | Manufacture of amorphous silicon mosfet |
| JPS57128382A (en) * | 1981-02-02 | 1982-08-09 | Canon Kk | Electrooptical display device |
| JPS587873A (en) * | 1981-07-07 | 1983-01-17 | Matsushita Electric Ind Co Ltd | Diode and manufacture thereof |
| JPS58112365A (en) * | 1981-12-26 | 1983-07-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS58212177A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
-
1985
- 1985-01-17 JP JP608585A patent/JPS61164267A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57103358A (en) * | 1980-12-18 | 1982-06-26 | Matsushita Electric Ind Co Ltd | Manufacture of amorphous silicon mosfet |
| JPS57128382A (en) * | 1981-02-02 | 1982-08-09 | Canon Kk | Electrooptical display device |
| JPS587873A (en) * | 1981-07-07 | 1983-01-17 | Matsushita Electric Ind Co Ltd | Diode and manufacture thereof |
| JPS58112365A (en) * | 1981-12-26 | 1983-07-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS58212177A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0361609A2 (en) * | 1988-09-30 | 1990-04-04 | Philips Electronics Uk Limited | Thin-film transistors, their method of manufacture, and display device using such transistors |
| US5334859A (en) * | 1991-09-05 | 1994-08-02 | Casio Computer Co., Ltd. | Thin-film transistor having source and drain electrodes insulated by an anodically oxidized film |
| JPH0669233A (en) * | 1991-12-03 | 1994-03-11 | Samsung Electron Co Ltd | Manufacture of semiconductor device |
| FR2718885A1 (en) * | 1994-04-15 | 1995-10-20 | Thomson Lcd | Method for manufacturing a reverse stage TFT. |
| WO1995028738A3 (en) * | 1994-04-15 | 1995-12-07 | Thomson Lcd | Method for making an inverted-type thin-film transistor |
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