JPS61161764A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS61161764A JPS61161764A JP275685A JP275685A JPS61161764A JP S61161764 A JPS61161764 A JP S61161764A JP 275685 A JP275685 A JP 275685A JP 275685 A JP275685 A JP 275685A JP S61161764 A JPS61161764 A JP S61161764A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- metal thin
- electrode
- semiconductor layer
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 10
- 230000007547 defect Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、液晶表示装置に用いられる薄膜トランジスタ
アレイの製造方法に関し、特に製造工程数が少なく歩留
シの高い薄膜トランジスタアレイの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film transistor array used in a liquid crystal display device, and particularly to a method for manufacturing a thin film transistor array with a small number of manufacturing steps and a high yield.
（従来技術とその問題点）
近年、オフィスオートメーションの進展に伴い、マンマ
シンインターフェイスとしての表示デバイス画素数の大
容量化研究開発が活発に進められている。液晶ディスプ
レイにおいても液晶をスイッチングするための薄膜トラ
ンジスタアレイの開発が盛んである。(Prior Art and its Problems) In recent years, with the progress of office automation, research and development on increasing the pixel count of display devices used as man-machine interfaces has been actively conducted. In the field of liquid crystal displays, thin film transistor arrays for switching liquid crystals are being actively developed.
従来の液晶表示用薄膜トランジスタアレイの製造方法の
１例として特願昭５８−１２６７２５に示されたものが
知られている。第２図ｆａ）〜（ｈｌに、前記従来の薄
膜トランジスタの製造方法を説明するためＫ、その製造
方法を工程順に表わした断面図を示す。As an example of a conventional method for manufacturing a thin film transistor array for a liquid crystal display, the method disclosed in Japanese Patent Application No. 126,725/1980 is known. In order to explain the manufacturing method of the conventional thin film transistor, FIGS. 2(a) to 2(hl) are cross-sectional views showing the manufacturing method in the order of steps.
この製造方法は絶縁基板１上にゲート電極２を形成し〔
第２図（ａｔ １ 、所定のパターンにエツチングする
〔第２図（ｂ）］。その後、その上にゲート絶縁膜３及
び半導体＠４を形成し〔第２図（ｃ）〕、半導体膜を所
定パターンにエツチングする〔第２図（ｄ）〕。その後
、全土面にドレイン及びソース電極となる金属薄膜５を
形成し〔第２図（ｅ）〕、チチヤネルとなる半導体ｒｆ
ｉＪを覆う部分に金属薄膜５を〔第２図（ｇ）〕。そし
て最後にエツチングにょシ透明電極６を所望パターンに
エツチングすると同時にチャンネルとしての半導体＋１
４上の金属薄膜５を除去し、ドレイン電極７とソース電
極８とを形成する〔第２図（ｈ）〕ことから構成される
。In this manufacturing method, a gate electrode 2 is formed on an insulating substrate 1 [
FIG. 2 (at 1) is etched into a predetermined pattern [FIG. 2 (b)]. Thereafter, a gate insulating film 3 and a semiconductor@4 are formed thereon [FIG. 2 (c)], and the semiconductor film is formed. It is etched into a predetermined pattern [Fig. 2 (d)]. After that, a metal thin film 5 that will become the drain and source electrodes is formed on the entire surface [Fig. 2 (e)], and a semiconductor rf that will become the channel is formed.
A metal thin film 5 is placed on the portion covering iJ [Fig. 2(g)]. Finally, the transparent electrode 6 is etched into a desired pattern, and at the same time the semiconductor +1 as a channel is etched.
The metal thin film 5 on the electrode 4 is removed, and a drain electrode 7 and a source electrode 8 are formed [FIG. 2(h)].
従来の製造方法では、ゲート電極のエツチング〔第２図
（ｂ） ） 、半導体膜のエツチング〔第２図（ｄ）〕
、金属薄膜のエツチング〔第２図（ｆ）〕およびチャン
ネル上のＩＴｏ、金属薄膜のエツチング〔第２図回
（ｈ）〕と〕構の７オトレジストエ程が必要である。Conventional manufacturing methods involve etching the gate electrode [Figure 2(b)] and etching the semiconductor film [Figure 2(d)].
, etching the metal thin film [FIG. 2(f)], and etching the ITO and metal thin film on the channel [FIG. 2(h)].
薄膜トランジスタの製造においては、フォトレジスト工
程を少なくすることが歩留りを良くするのに不可決であ
る。In manufacturing thin film transistors, it is essential to reduce the number of photoresist steps in order to improve yield.
（発明の目的）
本発明は、このような従来の欠点を除去し、製造工穆数
が少なく歩留夛の高い薄膜トランジスタの製造方法を提
供することにある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a thin film transistor with a small number of manufacturing steps and a high yield by eliminating such conventional drawbacks.
（発明の構成）
本発明は、絶縁体基板の上にゲート電極を所望パターン
に形成する工程と、該ゲート電極を覆うようにゲート絶
縁体層、半導体層、ドレイン及びソース電極となる金属
薄膜を順次形成する工程と、チャンネルとなる半導体層
を覆う部分とドレイン及びソース電極となる部分を残し
てその他の不要部分の金属薄膜および前記不要部分の金
属薄膜下の半導体層を除去する工程と、透明導電膜を形
成し該透明導電膜をパターニングし透明電極とすると同
時にチャンネルとしての半導体層上の金属薄膜を除去し
、ドレイン電極とソース電極を形成する工程を少なくと
も含むことを特徴とする薄膜トランジスタの製造方法で
ある。(Structure of the Invention) The present invention includes a step of forming a gate electrode in a desired pattern on an insulating substrate, and forming a metal thin film that will become a gate insulating layer, a semiconductor layer, and a drain and source electrode so as to cover the gate electrode. a step of sequentially forming a metal thin film, a step of removing a metal thin film in unnecessary parts and a semiconductor layer under the metal thin film in the unnecessary parts, leaving a part covering the semiconductor layer to become a channel and a part to become a drain and source electrode; Manufacturing a thin film transistor characterized by at least the steps of forming a conductive film, patterning the transparent conductive film to form a transparent electrode, and simultaneously removing a metal thin film on a semiconductor layer serving as a channel to form a drain electrode and a source electrode. It's a method.
（構成の詳細な説明）
本発明は、上述の構成をとることによシ従来技術の問題
点を解決した。本発明を薄膜トランジスタの製造工程順
に示した断面図第１図（ａｔ〜（ｆ）により説明する。(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-mentioned configuration. The present invention will be explained with reference to cross-sectional views of FIGS. 1(a-f) showing the steps of manufacturing a thin film transistor.
この製造方法は絶縁基板１上にゲート電極２を形成し〔
第１図（ａ）〕、所定のパターンにエツチングする〔第
１図（ｂ）〕。その後その上にゲート絶縁膜３、半導体
膜４および金属薄膜５を形成し〔第１図（ｃｌ ） 、
金属薄膜５訃よび半導体膜４を所定パターンにエツチン
グする〔第１図（ｄ）〕。In this manufacturing method, a gate electrode 2 is formed on an insulating substrate 1 [
Fig. 1(a)] and etching into a predetermined pattern [Fig. 1(b)]. Thereafter, a gate insulating film 3, a semiconductor film 4, and a metal thin film 5 are formed thereon [FIG. 1 (cl),
The metal thin film 5 and the semiconductor film 4 are etched into a predetermined pattern [FIG. 1(d)].
その後、全上面に透明電極６を形成する〔第１図（ｅ）
〕。そして最後にエツチングによシ透明電極６を所望パ
ターンにエツチングすると同時にチャンネルとしての半
導体層４上の金属薄膜５を除去し、ドレイン電極７とソ
ース’ｔ［！８とを形成する〔第１図（ｆ）〕ことから
構成されている。したがって本発明の製造方法では、ゲ
ート電極のエツチング〔第１図ｊｂ） ） 、金属薄膜
および半導体膜のエッチよび金属Ｎ １１％のエツチン
グ〔第１図（ｆ）〕と〕構のフォトレジスト工程で薄膜
トランジスタアレイが製造できる。After that, a transparent electrode 6 is formed on the entire upper surface [Fig. 1(e)
]. Finally, the transparent electrode 6 is etched into a desired pattern, and at the same time the metal thin film 5 on the semiconductor layer 4 serving as a channel is removed, and the drain electrode 7 and the source 't[! 8 [FIG. 1(f)]. Therefore, in the manufacturing method of the present invention, the photoresist process consists of etching the gate electrode (FIG. 1(f)), etching the metal thin film and semiconductor film, and etching 11% metal N (FIG. 1(f)). Thin film transistor arrays can be manufactured.
（実施例）
以下本発明の実施例について第１図（ａｌ〜（ｆｌを参
照して詳細に説明する。ガラス基板１にゲート電極用メ
タル２としてチタンを１ｏｏｏＸ蒸着し〔第１図（ａ）
〕、フォトレジスト法により所定のパターンにエツチン
グした〔第１図（ｂ）〕。その後その上にゲート絶縁膜
３として窒化シリコン喚２５００Ｘ半導体層４としてア
モルファスシリコンａを３００ＯＡプラズマＣＭＤ法に
よ多連続形成し、続いてその上に金属薄膜５としてチタ
ンを２０００＾蒸着した〔第１図（Ｃ）〕。フォトレジ
スト法によシチタンおよびアモルファスシリコン膜を所
定パターンにドライエツチングした〔第１図（ｄ）〕。(Example) An example of the present invention will be described in detail below with reference to FIGS.
], and was etched into a predetermined pattern by a photoresist method [FIG. 1(b)]. Thereafter, multiple layers of silicon nitride (2,500×) as a gate insulating film 3 and amorphous silicon (a) as a semiconductor layer (4) were successively formed using a 300 OA plasma CMD method. Figure (C)]. The titanium and amorphous silicon films were dry-etched into a predetermined pattern by a photoresist method [FIG. 1(d)].
エエラチンはＣ（Ｊ、 を圧力が０．１ｔｏｒｒになる
ように流し放電電力４００Ｗの条件で行なった。その後
全上面に透明電極６としてＩＴｏ模をｔｏｏｏＸスパッ
タした〔第１図（ｅ）〕。そして最後にエツチングによ
シ透明電極６を所望パターンにエツチングすると同時に
チャンネルとしての半導体層４上の金属薄膜５を除去し
、ドレイン電極７とソース電極８とを形成した〔第１図
（ｆ）〕。比較の九めに第２図（ａｌ〜（ｈ） Ｋ示す
従来の製造方法により薄膜トランジスタを形成した。各
薄情の堆積条件は、本発明の製造方法に用いたのと同一
の条件、エツチングの条件もすべて同一とした。比較し
た薄膜トランジスタアレイの規模はゲートライン５００
本、ドレインライン５００本で素子数は２５０，０００
個である。従来の製造方法によ＃）製造した薄膜トラン
ジスタプレイではゲート２インには断線による線欠陥は
見られなかったが、ドレインラインに社６本穆度以下の
線欠陥があった。また薄膜トランジスタの特性不良によ
る点欠陥は、２００〜３００個あった。これに反し本発
明の製造方法により製造した薄膜トランジスタアレイで
は、線欠陥は見られずまた点欠陥も２０個以下であった
。Eeratin was carried out under the conditions of flowing C (J, ) at a pressure of 0.1 torr and discharging power of 400 W. After that, an ITo pattern was sputtered on the entire upper surface as a transparent electrode 6 [Fig. 1 (e)]. Finally, the transparent electrode 6 was etched into a desired pattern, and at the same time the metal thin film 5 on the semiconductor layer 4 serving as a channel was removed to form a drain electrode 7 and a source electrode 8 [FIG. 1(f)]. For the ninth comparison, thin film transistors were formed by the conventional manufacturing method shown in Figures 2 (al to (h) K).The deposition conditions for each layer were the same as those used in the manufacturing method of the present invention, and the etching All conditions were the same.The scale of the compared thin film transistor array was 500 gate lines.
500 drain lines and 250,000 elements
It is individual. In the thin film transistor layer manufactured by the conventional manufacturing method, no line defect due to disconnection was observed on the gate 2-in, but there was a line defect of less than 6 lines on the drain line. Furthermore, there were 200 to 300 point defects due to poor characteristics of the thin film transistor. On the other hand, in the thin film transistor array manufactured by the manufacturing method of the present invention, no line defects were observed and the number of point defects was 20 or less.
（発明の効果）
本発明による薄膜トランジスタの製造方法を用いれば欠
陥の少ない薄膜トランジスタアレイを製造できる。これ
は、半導体層をエツチングしたあと金属薄膜を形成し、
その後金属薄膜をパターニングするという従来方法を半
導体層と金属薄膜を形成した後に連続して同一マスクで
パターニングするようにしてフォトレジスト工程を１つ
少なくしたことと、半導体層と金属薄膜とを連続して形
成したため相互の接続に断差がなくなったためである。(Effects of the Invention) By using the method for manufacturing a thin film transistor according to the present invention, a thin film transistor array with few defects can be manufactured. This involves forming a thin metal film after etching the semiconductor layer.
The conventional method of patterning the metal thin film was reduced by one photoresist process by forming the semiconductor layer and the metal thin film and then patterning them successively using the same mask. This is because there was no difference in mutual connection because the two were formed by using the same method.
以上詳細に述ぺた通り、本発明によれば製造工程数が少
なく歩留りの高い薄膜トランジスタの製造方法を提供で
きる。As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a thin film transistor with a small number of manufacturing steps and a high yield.
第１図（ａｌ〜（ｆｌは本発明の薄膜トランジスタアレ
イの製造工程を示す断面図、第２図（ａｔ〜（ｈｌは従
来の薄膜トランジスタアレイの製造工程を示す断面図で
ある。
図において、１・・・絶縁基板、２・・・ゲート電極、
３・・・ゲート絶縁膜、４・・・半導体膜、５・・・ド
レイン及びソース電極となる金属薄膜、６・・・透明１
！極、７・・・ドレイン電極、８・・・ソース″Ｍ、極
をそれぞれ示す。
代理人弁理士 内 原 晋１、
ｗＩＡＩ 図FIG. 1 (al~(fl) is a cross-sectional view showing the manufacturing process of the thin film transistor array of the present invention, FIG. 2 (at~(hl) is a cross-sectional view showing the manufacturing process of the conventional thin film transistor array. ...Insulating substrate, 2...Gate electrode,
3... Gate insulating film, 4... Semiconductor film, 5... Metal thin film serving as drain and source electrodes, 6... Transparent 1
! Pole, 7...drain electrode, 8...source"M, poles are shown respectively.Representative Patent Attorney Susumu Uchihara1, wIAI Diagram
Claims (1)
工程と、該ゲート電極を覆うようにゲート絶縁体層、半
導体層、ドレイン及びソース電極となる金属薄膜を順次
形成する工程と、チャンネルとなる半導体層を覆う部分
とドレイン及びソース電極となる部分を残してその他の
不要部分の金属薄膜および前記不要部分の金属薄膜下の
半導体層を同時に除去する工程と、透明導電膜を形成し
該透明導電膜をパターニングし透明電極とすると同時に
チャンネルとしての半導体層上の金属薄膜を除去し、ド
レイン電極とソース電極を形成する工程を少なくとも含
むことを特徴とする薄膜トランジスタの製造方法。A process of forming a gate electrode in a desired pattern on an insulator substrate, a process of sequentially forming a gate insulator layer, a semiconductor layer, a metal thin film that will become a drain and source electrode so as to cover the gate electrode, and a process that will become a channel. A process of simultaneously removing the metal thin film in unnecessary parts and the semiconductor layer under the metal thin film in the unnecessary parts, leaving a part covering the semiconductor layer and a part to become the drain and source electrodes, and forming a transparent conductive film and forming the transparent conductive film. A method for manufacturing a thin film transistor, comprising at least the step of patterning a film to form a transparent electrode and simultaneously removing a metal thin film on a semiconductor layer serving as a channel to form a drain electrode and a source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP275685A JPS61161764A (en) | 1985-01-11 | 1985-01-11 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP275685A JPS61161764A (en) | 1985-01-11 | 1985-01-11 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61161764A true JPS61161764A (en) | 1986-07-22 |
Family
ID=11538184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP275685A Pending JPS61161764A (en) | 1985-01-11 | 1985-01-11 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61161764A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01123475A (en) * | 1987-11-06 | 1989-05-16 | Sharp Corp | Liquid crystal display equipment |
| EP0694804A2 (en) | 1994-07-27 | 1996-01-31 | Hitachi, Ltd. | Liquid crystal display apparatus, semiconductor devices, and manufacturing methods therefor |
| KR100300165B1 (en) * | 1998-08-05 | 2001-09-29 | 마찌다 가쯔히꼬 | Method for fabricating a semiconductor device |
| US6707513B2 (en) | 2000-07-10 | 2004-03-16 | International Business Machines Corporation | Active matrix substrate and manufacturing method thereof |
| JP2009300193A (en) * | 2008-06-12 | 2009-12-24 | Asuka Denshi Kk | Testing connector of electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5623780A (en) * | 1979-07-31 | 1981-03-06 | Sharp Corp | Manufacture of thin film transistor |
| JPS59149060A (en) * | 1983-02-15 | 1984-08-25 | Sharp Corp | Manufacture of thin-film transistor |
-
1985
- 1985-01-11 JP JP275685A patent/JPS61161764A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5623780A (en) * | 1979-07-31 | 1981-03-06 | Sharp Corp | Manufacture of thin film transistor |
| JPS59149060A (en) * | 1983-02-15 | 1984-08-25 | Sharp Corp | Manufacture of thin-film transistor |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01123475A (en) * | 1987-11-06 | 1989-05-16 | Sharp Corp | Liquid crystal display equipment |
| EP0694804A2 (en) | 1994-07-27 | 1996-01-31 | Hitachi, Ltd. | Liquid crystal display apparatus, semiconductor devices, and manufacturing methods therefor |
| US5668379A (en) * | 1994-07-27 | 1997-09-16 | Hitachi, Ltd. | Active matrix crystal display apparatus using thin film transistor |
| KR100300165B1 (en) * | 1998-08-05 | 2001-09-29 | 마찌다 가쯔히꼬 | Method for fabricating a semiconductor device |
| US6707513B2 (en) | 2000-07-10 | 2004-03-16 | International Business Machines Corporation | Active matrix substrate and manufacturing method thereof |
| KR100443804B1 (en) * | 2000-07-10 | 2004-08-09 | 인터내셔널 비지네스 머신즈 코포레이션 | Active matrix substrate and display device |
| US6859252B2 (en) | 2000-07-10 | 2005-02-22 | International Business Machines Corporation | Active matrix substrate and manufacturing method thereof |
| JP2009300193A (en) * | 2008-06-12 | 2009-12-24 | Asuka Denshi Kk | Testing connector of electronic component |
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