JPS63128756A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPS63128756A JPS63128756A JP27612086A JP27612086A JPS63128756A JP S63128756 A JPS63128756 A JP S63128756A JP 27612086 A JP27612086 A JP 27612086A JP 27612086 A JP27612086 A JP 27612086A JP S63128756 A JPS63128756 A JP S63128756A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- film
- electrode
- silicon film
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010409 thin film Substances 0.000 title claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 45
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 238000011109 contamination Methods 0.000 abstract description 3
- 239000010453 quartz Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は液晶ディスプレイ用アクティブマトリックス薄
膜トランジスタ(以下単にTPTと称する)に用いられ
るアモルファスシリコンTPTの製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an amorphous silicon TPT used in an active matrix thin film transistor (hereinafter simply referred to as TPT) for a liquid crystal display.
アモルファスシリコンTPTはアクティブマトリックス
方式の液晶ディスプレイに、その透過型液晶ディスプレ
イへの適合性及び大型ディスプレイへの可能性等の理由
により用いられている。逆スタガゲート型アモルファス
シリコンTPTの一般的な構造を第1図に示すが、その
構造はガラス・石英等の透明基材1上にゲート電極2及
び画素電極用透明電極3、その上にゲート絶縁I!4、
アモルファスシリコン膜5、その上にオーミックコンタ
クト層のn0アモルファスシリコン膜6を介してソース
電極7及びドレイン電極8となっている。また画素電極
用透明電極3はゲート絶縁膜4に設けられたスルーホー
ルによ、リドレイン電極8と接続されている。さらにチ
ャネルの上にはチャネル保護膜9がある。この様なTP
Tの従来の工程を第2図に示す、まず第2図(a)に示
すごとくガラスや石英等の透明基材1上にクロム・チタ
ン等の金属からなるゲート電極2及びITO等の透明電
極からなる画素電極3を形成する0次に第2図(b)に
示すごとくプラズマCVDvtiにより下から窒化シリ
コン・酸化シリコン等の絶縁体からなるゲート絶縁膜4
、アモルファスシリコン膜5、オーミックコンタクト層
のn“アモルファスシリコン膜6を連続して成膜する。Amorphous silicon TPT is used in active matrix liquid crystal displays for reasons such as its suitability for transmissive liquid crystal displays and its possibility of being used for large-sized displays. The general structure of an inverted staggered gate type amorphous silicon TPT is shown in FIG. ! 4,
A source electrode 7 and a drain electrode 8 are formed through an amorphous silicon film 5 and an n0 amorphous silicon film 6 as an ohmic contact layer thereon. Further, the transparent electrode 3 for pixel electrode is connected to the drain electrode 8 through a through hole provided in the gate insulating film 4. Furthermore, a channel protective film 9 is provided on the channel. TP like this
The conventional process of T is shown in FIG. 2. First, as shown in FIG. 2(a), a gate electrode 2 made of a metal such as chromium or titanium and a transparent electrode such as ITO are formed on a transparent base material 1 such as glass or quartz. A gate insulating film 4 made of an insulator such as silicon nitride or silicon oxide is formed from below by plasma CVDvti as shown in FIG. 2(b).
, an amorphous silicon film 5, and an n'' amorphous silicon film 6 as an ohmic contact layer are successively formed.
次にアルミニウム1チタン、ニッケル等の金属または[
TO等の導電膜からなるn゛アモルファスシリコン膜保
護膜10をソース・ドレイン電極相当部分に形成する。Next, metals such as aluminum 1 titanium and nickel or [
An n-amorphous silicon film protection film 10 made of a conductive film such as TO is formed on portions corresponding to the source and drain electrodes.
(第2図(c)参照)次に第2図(d)に示すごとく反
応性イオンエツチング(以下単にRIEと称す)により
口“アモルファスシリコン膜6及びアモルファスシリコ
ン膜5をTPTを構成するアイランドの形状に加工した
後、チャンネル部の09 アモルファスシリコン膜をR
IEにより除去する。次に第2図(e) に示すご゛
と<RIHによりドレイン電極8と画素電極3を導通さ
せるスルーホール11を形成する。その後第2図(f)
に示すごとくアルミニウム等の金属またはITO等の透
明導電膜からなるソース電極7、ドレイン電極8を01
アモルファスシリコン保護膜10上に形成しかつスルー
ホールを介して画素電極3との導通を取る。次に第2図
(g)に示すごとくチャネル部分上にチャネル保護膜9
を形成してアモルファスシリコンTPTが完成する。(See FIG. 2(c)) Next, as shown in FIG. 2(d), the amorphous silicon film 6 and the amorphous silicon film 5 are etched by reactive ion etching (hereinafter simply referred to as RIE) into the islands constituting the TPT. After processing into the shape, the 09 amorphous silicon film in the channel part is R
Remove by IE. Next, a through hole 11 is formed to connect the drain electrode 8 and the pixel electrode 3 by RIH as shown in FIG. 2(e). Then Figure 2(f)
As shown in the figure, a source electrode 7 and a drain electrode 8 made of metal such as aluminum or a transparent conductive film such as ITO are
It is formed on the amorphous silicon protective film 10 and is electrically connected to the pixel electrode 3 via a through hole. Next, as shown in FIG. 2(g), a channel protective film 9 is placed on the channel portion.
is formed to complete an amorphous silicon TPT.
しかし、第2図の従来工程を採った場合、工程(e)に
おいてスルーホール11を形成する際にスルーホール1
1以外の部分がRIEによりエツチングされるのを防ぐ
ために耐RIE膜としてフォトレジスト等を塗布する必
要があるが、チャネル部分がフォトレジストにより汚染
を受はソース・ドレイン間のオフ電流値の増加等が生じ
、TPTの特性が劣化する。これによりTFTアレイに
した場合全体が均一なTPTとならず、歩留り低下の一
つの原因となっていた。However, when the conventional process shown in FIG. 2 is adopted, when forming the through hole 11 in step (e), the through hole 1
In order to prevent parts other than 1 from being etched by RIE, it is necessary to apply a photoresist or the like as an RIE-resistant film, but if the channel part is contaminated by the photoresist, the off-current value between the source and drain increases, etc. occurs, and the characteristics of TPT deteriorate. As a result, when a TFT array is formed, the entire TPT is not uniform, which is one of the causes of a decrease in yield.
以上の問題を解決するには、チャネル部分上のn0アモ
ルファスシリコン膜をRIEで除去後、ただちにチャネ
ル保護膜を形成する必要がある。第2図の工程(d)の
後ただちに保護膜を形成した場合、工程の増加とそれに
伴なうフォトマスクの増加が生じる。そこで本発明では
、第2図(d)の工程でチャネル部分上の01アモルフ
ァスシリコン膜を残し、その後のフォトプロセスにより
汚染を防ぐチャネル保護膜として使用し、工程(f)の
電極とスルーホールの形成後にチャネル部分上の10ア
モルファスシリコン膜を除去しその後チャネル保護膜を
形成する工程を採用するものである。To solve the above problem, it is necessary to form a channel protective film immediately after removing the n0 amorphous silicon film on the channel portion by RIE. If the protective film is formed immediately after step (d) in FIG. 2, the number of steps will increase and the number of photomasks will increase accordingly. Therefore, in the present invention, the 01 amorphous silicon film on the channel portion is left in the step of FIG. After formation, a step of removing the 10 amorphous silicon film on the channel portion and then forming a channel protective film is adopted.
以下本発明の製造方法の実施例を示す第3図を用いて詳
細に説明する。第3図(a)に示すごとく最初にガラス
や石英等の透明基材1上にクロム・チタン等の金属から
なるゲート電極2及びITO等の透明電極からなる画素
電極3を形成する。次に第2図(b)に示すごとくプラ
ズマCVD装置により下から窒化シリコン・酸化シリコ
ン等の絶縁体からなるゲート絶縁膜4、アモルファスシ
リコン膜5、n+アモルファスシリコン膜6を連続して
成膜する。次にアルミニウム・チタン・ニッケル等の金
属またはITO等の導電膜からなるn°アモルファスシ
リコン膜保護膜lOをソース・ドレイン電極相当部分に
成型する。(第3図(c)参照)次に第3図(d)に示
すごと<RYEにより n゛ア7モルフアスシリコン膜
6アモルファスシリコン膜5をTPTを構成するアイラ
ンドの形状に加工する。このときチャネル部のn゛ア7
モルフアスシリコン膜去しない。次に第3図(e)に示
すごと<RIHによりドレイン電極8と画素電極用透明
電極3を導通させるスルーホール11を形成する。Hereinafter, an embodiment of the manufacturing method of the present invention will be explained in detail using FIG. 3. As shown in FIG. 3(a), first, a gate electrode 2 made of a metal such as chromium or titanium, and a pixel electrode 3 made of a transparent electrode such as ITO are formed on a transparent base material 1 made of glass, quartz, or the like. Next, as shown in FIG. 2(b), a gate insulating film 4 made of an insulator such as silicon nitride or silicon oxide, an amorphous silicon film 5, and an n+ amorphous silicon film 6 are successively formed from below using a plasma CVD apparatus. . Next, an n° amorphous silicon film protective film lO made of a metal such as aluminum, titanium, nickel, or a conductive film such as ITO is formed on the portions corresponding to the source and drain electrodes. (See FIG. 3(c)) Next, as shown in FIG. 3(d), the amorphous silicon film 6 is processed into the shape of an island constituting the TPT by <RYE. At this time, nia 7 of the channel part
Do not remove the morphous silicon film. Next, as shown in FIG. 3(e), a through hole 11 is formed by RIH to connect the drain electrode 8 and the transparent electrode 3 for pixel electrode.
その後第3図(f)に示すごとくアルミニウム等の金属
またはITO等の透明導電膜からなるソース電極7、ド
レイン電極8をn+アモルファスシリコン保護膜IO上
に形成しかつスルーホール11を介してドレイン電極8
と画素電極3用透明電極との導通を取る0次に第3図(
g)に示すごとくチャネル部分上の10アモルファスシ
リコン膜をRIEにより除去した後、プラズマCVDに
より窒化シリコン膜または酸化シリコン膜を堆積し、R
IEにより加工してチャネル保護膜9を形成してアモル
ファスシリコンTPTが完成する。(第3図(h)参照
)
〔発明の効果〕
従来法では液晶ディスプレイ用逆スタガゲート型アモル
ファスシリコンTPTアレイの製造工程ではチャネル部
分のフォトプロセスによる汚染が原因となるソース・ド
レイン間のオフ電流の増加等の問題があり、アレイにし
たときの歩留りが悪かった。本発明によればこれらの汚
染を避けることができ、均質なアレイの製造ひいては歩
留りの向上をはかることができる。Thereafter, as shown in FIG. 3(f), a source electrode 7 and a drain electrode 8 made of a metal such as aluminum or a transparent conductive film such as ITO are formed on the n+ amorphous silicon protective film IO, and the drain electrodes are formed through a through hole 11. 8
Figure 3 (
As shown in g), after removing the 10 amorphous silicon film on the channel part by RIE, a silicon nitride film or a silicon oxide film is deposited by plasma CVD, and the R
Processing is performed by IE to form a channel protective film 9 to complete an amorphous silicon TPT. (See Figure 3 (h)) [Effects of the Invention] In the conventional method, in the manufacturing process of inverted staggered gate amorphous silicon TPT arrays for liquid crystal displays, off-current between the source and drain caused by contamination due to the photo process in the channel portion is reduced. There were problems such as an increase in the number of nanometers, and the yield was poor when it was made into an array. According to the present invention, these contaminations can be avoided, and homogeneous arrays can be manufactured, thereby improving yield.
第1図は逆スタガゲート型アモルファスシリコンTPT
の構造を示す断面図であり、第2図(a)〜(g) は
従来法によるアモルファスシリコンTPTの製造方法の
一例を工程順に示す説明図であり、第3図(a)〜(h
)は本発明のアモルファスシリコンTPTの製造方法の
一実施例を工程順に示す説明図である。
■・・・透明基材
2・・・ゲート電極
3・・・画素電極用透明電極
4・・・ゲート絶縁膜
5・・・アモルファスシリコン膜
6・・・n0アモルファスシリコン膜
7・・・ソース電極
8・・・ドレイン電極
9・・・チャネル保護膜
10・・・n0アモルファスシリコン膜保護膜11・・
・スルーホール
特許出願人 凸版印刷株式会社
代 表 者 鈴 木 和 失策1
図
第2図Figure 1 shows an inverted staggered gate type amorphous silicon TPT.
FIGS. 2(a) to 2(g) are explanatory diagrams showing an example of a conventional method for manufacturing amorphous silicon TPT in the order of steps, and FIGS. 3(a) to (h) are cross-sectional views showing the structure of .
) is an explanatory diagram showing one embodiment of the method for manufacturing amorphous silicon TPT of the present invention in the order of steps. ■... Transparent base material 2... Gate electrode 3... Transparent electrode for pixel electrode 4... Gate insulating film 5... Amorphous silicon film 6... n0 amorphous silicon film 7... Source electrode 8...Drain electrode 9...Channel protective film 10...n0 amorphous silicon film protective film 11...
・Through hole patent applicant Toppan Printing Co., Ltd. Representative Kazu Suzuki Mistake 1
Figure 2
Claims (1)
リコン薄膜トランジスタを製造する方法において、チャ
ネルのアモルファスシリコン層に損傷を与える惧れのあ
る工程の際、その上に形成されるn^+アモルファスシ
リコン膜を表面保護膜として使用することを特徴とする
薄膜トランジスタの製造方法。In a method for manufacturing an inverted staggered gate type amorphous silicon thin film transistor for liquid crystal displays, the n^+ amorphous silicon film formed on the channel amorphous silicon layer is used as a surface protection film during a process that may damage the amorphous silicon layer of the channel. A method for manufacturing a thin film transistor, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27612086A JPS63128756A (en) | 1986-11-19 | 1986-11-19 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27612086A JPS63128756A (en) | 1986-11-19 | 1986-11-19 | Manufacture of thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63128756A true JPS63128756A (en) | 1988-06-01 |
Family
ID=17565071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27612086A Pending JPS63128756A (en) | 1986-11-19 | 1986-11-19 | Manufacture of thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63128756A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4990460A (en) * | 1989-01-27 | 1991-02-05 | Nec Corporation | Fabrication method for thin film field effect transistor array suitable for liquid crystal display |
US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
US5166086A (en) * | 1985-03-29 | 1992-11-24 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor array and method of manufacturing same |
US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
US5320973A (en) * | 1986-07-11 | 1994-06-14 | Fuji Xerox Co., Ltd. | Method of fabricating a thin-film transistor and wiring matrix device |
US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
-
1986
- 1986-11-19 JP JP27612086A patent/JPS63128756A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166086A (en) * | 1985-03-29 | 1992-11-24 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor array and method of manufacturing same |
US5320973A (en) * | 1986-07-11 | 1994-06-14 | Fuji Xerox Co., Ltd. | Method of fabricating a thin-film transistor and wiring matrix device |
US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
US4990460A (en) * | 1989-01-27 | 1991-02-05 | Nec Corporation | Fabrication method for thin film field effect transistor array suitable for liquid crystal display |
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