JPS6184066A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS6184066A JPS6184066A JP20411484A JP20411484A JPS6184066A JP S6184066 A JPS6184066 A JP S6184066A JP 20411484 A JP20411484 A JP 20411484A JP 20411484 A JP20411484 A JP 20411484A JP S6184066 A JPS6184066 A JP S6184066A
- Authority
- JP
- Japan
- Prior art keywords
- source
- gate
- electrode
- film
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 13
- 239000011521 glass Substances 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 239000010453 quartz Substances 0.000 abstract description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 2
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 abstract 3
- 235000006408 oxalic acid Nutrition 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000011651 chromium Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 241000972773 Aulopiformes Species 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012153 distilled water Substances 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000019515 salmon Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は薄膜トランジスタ(以下TPTと略す)の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film transistor (hereinafter abbreviated as TPT).
(従来の技術) 従来のTPTの要部断面図を第1図に示す。(Conventional technology) FIG. 1 shows a cross-sectional view of the main parts of a conventional TPT.
この製造方法としては第1図に示す如く、ガラス基板又
はアルミナ基板等1上に、ニクロム(NiCr )、タ
ングステン(W)、モリブデン(MO)クロム(Cr
)等よシなるケ゛−ト電極金属層を電子ビーム蒸着法ま
たはス・ぐツタ法によシ被着形成し、所定のi4ターン
に加工してy−上電極2を形成する。その上にデート絶
縁層3となるスリコン酸化・(5inX)膜またはシリ
コン窒化(5iNX)膜をそれぞれ、N20とSiH4
、NH,と5in4を主成分ガスとしてグロー放電法に
より堆積させ、さらに活性層4となる、非晶質シリコン
半導体層をS r Haのグロー放電法により堆積させ
る。As shown in Fig. 1, this manufacturing method involves coating nichrome (NiCr), tungsten (W), molybdenum (MO), chromium (Cr) on a glass substrate or alumina substrate 1.
), etc., is deposited using an electron beam evaporation method or a sputtering method, and processed into a predetermined i4 turn to form the y-upper electrode 2. On top of that, a silicon oxide (5inX) film or a silicon nitride (5iNX) film, which will become the date insulating layer 3, are deposited with N20 and SiH4, respectively.
, NH, and 5in4 as main component gases by a glow discharge method, and further an amorphous silicon semiconductor layer, which will become the active layer 4, is deposited by a glow discharge method using S r Ha.
次にTPTとなる部分以外は加工し除去して、島状にパ
ターンニングしダート絶縁層3と活性層4を形成する。Next, the portion other than the portion that will become TPT is processed and removed, and patterned into an island shape to form a dart insulating layer 3 and an active layer 4.
次に、ソース電極5、ドレイン電極6となるアルミ(A
t )層を真空蒸着法と加工によシ形成することでTP
Tが完成する。Next, aluminum (A
t) layer by vacuum evaporation method and processing.
T is completed.
(発明が解決しようとする問題点)
しかしながら従来の技術では、前記2のr−上電極(第
1図の8)による段差のためダート電極とソース電極、
またはr−上電極とドレイン電極間のリークが発生しや
すいので、ケ0−ト絶縁膜3を厚くする必要があった。(Problems to be Solved by the Invention) However, in the conventional technology, due to the step difference caused by the above-mentioned 2 r-upper electrodes (8 in FIG. 1), the dirt electrode and the source electrode,
Alternatively, since leakage between the r-upper electrode and the drain electrode is likely to occur, it is necessary to increase the thickness of the ketone insulating film 3.
このため作業性が悪く、かつ小型で信頼性の高いTPT
を実現するのが困難であった。Therefore, it is difficult to work with TPT, which is small and highly reliable.
was difficult to realize.
またデート絶縁膜が厚くなるため必然的にトランジスタ
のスレッンユホールド電圧(Vth )を高めてしまう
欠点があった。Furthermore, since the date insulating film becomes thicker, the threshold voltage (Vth) of the transistor inevitably increases.
本発明は、以上述べたダート電極の段差部分で発生する
リーク電流を防止し、信頼性の高いTPTを歩留シ良く
製造することを目的とする。An object of the present invention is to prevent the leakage current generated at the step portion of the dirt electrode described above and to manufacture a highly reliable TPT with a high yield.
(問題点を解決するための手段)
本発明は、まず基板要部全面にソース電極及びドレイン
電(至)材としての金属を被着し、次いで、その金属層
をソース電極及びドレイン電極の予定領域を除いて、酸
化することによってソース電極及びドレイン電極を選択
的に形成し、その後、半導体薄膜、ケ゛−ト酸化膜を被
着し、又ケゝ−ト電極を形成するようにしたものである
。(Means for Solving the Problems) The present invention first deposits metal as a source electrode and drain electrode material on the entire surface of the main part of the substrate, and then uses the metal layer as the source electrode and drain electrode material. A source electrode and a drain electrode are selectively formed by oxidation except for the region, and then a semiconductor thin film and a gate oxide film are deposited, and a gate electrode is formed. be.
(作用)
このように、ソース電極及びドレイン電極となる部分以
外を酸化することによって両電極を選択的に形成してい
るため、段差のない構造とな9、比較的薄いダート酸化
膜で、ケ゛−ト電極とソース電極間のリーク電流などを
おさえることができる。(Function) In this way, since both electrodes are selectively formed by oxidizing the parts other than those that will become the source and drain electrodes, a structure with no steps can be achieved9. - Leakage current between the source electrode and the source electrode can be suppressed.
(実施レリ)
まずガラス基板または石英基板1上の要部全面に、電子
ビーム蒸着法あるいはスパッタ法によりタンタル(Ta
)膜を100〜1000λ被着形成する。(Implementation) First, tantalum (Ta) is applied to the entire main part of the glass substrate or quartz substrate 1 by electron beam evaporation or sputtering.
) A film with a thickness of 100 to 1000λ is deposited.
その後レノスト等でソース電極及びドレイン電極となる
部分のみをおおったパターンニング加工を行い、そのの
ち蒸留水にし乃う酸を添加した溶液に入れ、メンタル側
を陽極として数十〜数百ボルトの直流電圧を印加するこ
とで陽極酸化(化成)を行ない、露出したタンタル部分
全体を五酸fヒタンタル(Ta205)とし絶縁層12
とする。After that, a patterning process is performed to cover only the parts that will become the source and drain electrodes using a lennost, etc., and then the electrodes are placed in a solution of distilled water with an acid added, and a direct current of several tens to hundreds of volts is applied using the mental side as the anode. By applying a voltage, anodic oxidation (chemical formation) is performed, and the entire exposed tantalum portion is converted into tantalum pentaoxide (Ta205) to form the insulating layer 12.
shall be.
その後、不用となったレノスト等を除去することで、所
定の・ぐターンに形成されたソース電極13とドレイン
電極14が形成される。Thereafter, the source electrode 13 and drain electrode 14 formed in predetermined patterns are formed by removing unnecessary renost and the like.
次にチャンネル層(活性層)15となる、非晶質ンリコ
ン半導体層をS I I(aのグロー放電法により堆積
させ、さらにケ゛−ト絶R膜I6となるシリコン酸化(
5inx)膜またはシリコン窒化(SiNyC)膜をそ
九ぞれ、N20とF3iH4,NH3とS iH4を主
成分ガスとしてグロー放電法によシ堆積させる。Next, an amorphous silicon semiconductor layer, which will become the channel layer (active layer) 15, is deposited by the glow discharge method of SII (a), and then silicon oxide (which will become the gate isolation R film I6) is deposited.
A 5inx) film or a silicon nitride (SiNyC) film is deposited by a glow discharge method using N20 and F3iH4, NH3 and SiH4 as main component gases, respectively.
次にTPTとなる部分以外は加工し除去して島状にノぞ
ターンニングする。Next, the parts other than those that will become TPT are processed and removed, and the grooves are turned into an island shape.
最後に、ダート電極17となるニクロム(NiCr)ク
ロム(Cr)、タングステン(W)、モリブデン(Mo
)等よりなる金属層を真空蒸着法と加工により形成す
ることでTPTが完成する。Finally, the dart electrode 17 is made of nichrome (NiCr), chromium (Cr), tungsten (W), and molybdenum (Mo).
) etc. by vacuum evaporation and processing to complete the TPT.
ソースとドレイン金属の酸化法としては、陽極酸化法の
ほかに、0□グラズマによるプラズマ酸化法を用いても
同様のことが可能である。As a method for oxidizing the source and drain metals, in addition to the anodic oxidation method, the same effect can be achieved by using a plasma oxidation method using 0□ glazma.
また第1の実施例としてタンタルを用いたが、チタン(
Ti )または、アルミニウム(At)またはタングス
テン(W)をソース電極、ドレイン電極の材料として用
い、不用の部分をそれぞれ陽極酸化またはプラズマ酸化
して、それぞれチタン酸化物層(TlO2)、アルミニ
ウム酸化物層(At203)タングステン酸化物層(W
O2)を形成しても同様にTPTが完成する。Furthermore, although tantalum was used in the first embodiment, titanium (
Ti) or aluminum (At) or tungsten (W) is used as the material for the source and drain electrodes, and the unnecessary parts are anodized or plasma oxidized to form a titanium oxide layer (TlO2) and an aluminum oxide layer, respectively. (At203) Tungsten oxide layer (W
Even if O2) is formed, TPT is completed in the same way.
(発明の効果)
以上のように本発明によれば、ソース電極、ドレイン電
極形成時に陽極酸化またはプラズマ酸化を行ない不用の
ソース電極とドレイン電極の部分を酸化し絶縁物化した
ことにより、ケ゛−ト電極の膜厚による段差のない平坦
なTPTが形成可能となった。(Effects of the Invention) As described above, according to the present invention, anodic oxidation or plasma oxidation is performed when forming the source and drain electrodes, and unnecessary portions of the source and drain electrodes are oxidized and made into insulators. It has become possible to form a flat TPT with no steps due to the thickness of the electrode.
したがってダート電極とソース電極、ケ゛−ト電極とド
レイン電極間のリーク電流を微少におさえることができ
、かつ小型TPTが形成可能となる。Therefore, leakage current between the dirt electrode and the source electrode, and between the gate electrode and the drain electrode can be suppressed to a minimum, and a small TPT can be formed.
またこの作成法によれば高価な装置は必要なく、通常の
工程で製造できるため安価となる。Furthermore, this manufacturing method does not require expensive equipment and can be manufactured using normal processes, resulting in low cost.
また、ステップカパレーノが問題にならないため、高い
信頼性が期待される。In addition, high reliability is expected because step caperno is not a problem.
図は本発明によって得られたTPTの1例を示す断面図
である。
l・−・絶縁物基板、2・・・絶縁層、3・・・ソース
電極、4・・・ドレイン電極、5・・・チャンネル層、
6・・・り゛−ト絶縁層、7・・・ケ゛−ト電極。
ソースtモジ
手続補正書(鮭)
1、事件の表示
昭和59年 特 許 願第204114 号2 発明
の名称
薄膜トランノスタの製造方法
3 補正をする者
事件との関係 特 許 出 願 人任 所
(〒105) 東京都港区虎ノ門1丁目7番12号4
代理人
住 所(〒105) 東京都港区虎ノ門1丁目7番1
2号6 補正の内容
1、 明細言第・1頁第2行目にある「(実施例)」と
第3行目にある「まずガラス基板・・」とある間に次の
文を挿入する。
「不発明のTPTの要部断面図を第2図に示也」2 同
書第6頁第15行目に「図は本発明に」とある前に「第
1図は従来のTPTの要部断面ズ、第2」という文を挿
入する。
31司頁第17行目から@19行目に「l・・・絶縁物
基板、・・・・・7・ゲート電極。」とあるのを下記の
通り補正する。
「1〜絶縁物基板、12・・絶縁層、ノ3・・ソース電
瞑、11・・トンイン電匝、15・・チャ/ 不 ル層
、 j 6− ケ゛ −ト 絶縁層 、 ノ 7
・・ケゝ−ドア1Lぢ穿(。」
41 図を「第2図」として別紙の通り補正するとと
もに「第1図」全別紙の通り追加可6゜オ芝束、1TF
Tの竿部断面図
第1図
本発明のTPTのキ部曲面図
第2図The figure is a sectional view showing an example of TPT obtained by the present invention. l... Insulator substrate, 2... Insulating layer, 3... Source electrode, 4... Drain electrode, 5... Channel layer,
6... Straight insulating layer, 7... Kate electrode. Source tMoji procedural amendment (salmon) 1. Indication of the case 1982 Patent Application No. 204114 2 Name of the invention Method for manufacturing thin film transnostar 3 Person making the amendment Relationship with the case Patent application Person in charge Place (〒 105) 1-7-12-4 Toranomon, Minato-ku, Tokyo
Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2 No. 6 Contents of amendment 1: Insert the following sentence between "(Example)" on the second line of page 1 of the specification and "First, glass substrate..." on the third line. . ``A sectional view of the main parts of the uninvented TPT is shown in Figure 2.'' 2 On page 6, line 15 of the same book, before it says ``The figure is in accordance with the present invention,'' it says ``Figure 1 shows the main parts of the conventional TPT.'' Insert the sentence "Cross section, 2nd". On page 31, lines 17 to 19, the statement ``l... insulator substrate, 7... gate electrode.'' is corrected as follows. 1 - Insulator substrate, 12... Insulating layer, No. 3... Source voltage, 11... Thin-in electric drop, 15... Cha/ruin layer, j 6- Case insulation layer, No. 7
...Ke-Door 1L pierced (.) 41 The figure can be corrected as "Figure 2" as per the attached sheet, and "Figure 1" can be added as per the attached sheet.
Figure 1 is a sectional view of the rod of the T. Figure 2 is a curved view of the part of the TPT of the present invention.
Claims (1)
層を形成し、次いでソース電極とドレイン電極となる部
分以外を酸化することによってソース電極とドレイン電
極を選択的に形成したことを特徴とする薄膜トランジス
タの製造方法。A thin film transistor characterized in that the source electrode and the drain electrode are selectively formed by forming a metal layer that will become the source electrode and the drain electrode on the surface of the substrate, and then oxidizing the parts other than the parts that will become the source electrode and the drain electrode. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20411484A JPS6184066A (en) | 1984-10-01 | 1984-10-01 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20411484A JPS6184066A (en) | 1984-10-01 | 1984-10-01 | Manufacture of thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6184066A true JPS6184066A (en) | 1986-04-28 |
Family
ID=16485039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20411484A Pending JPS6184066A (en) | 1984-10-01 | 1984-10-01 | Manufacture of thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6184066A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62216372A (en) * | 1986-03-18 | 1987-09-22 | Fujitsu Ltd | A-si thin film transistor |
JPH0449625A (en) * | 1990-06-19 | 1992-02-19 | Nec Corp | Thin-film transistor and its manufacturing method |
EP0506117A2 (en) * | 1991-03-29 | 1992-09-30 | Casio Computer Company Limited | Thin-film transistor |
EP1691340A1 (en) * | 2003-11-28 | 2006-08-16 | OHMI, Tadahiro | Thin film transistor integrated circuit device, active matrix display device, and manufacturing method of the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51150986A (en) * | 1975-06-19 | 1976-12-24 | Mitsubishi Electric Corp | Fabrication method of semiconductor device |
JPS5721867A (en) * | 1980-06-02 | 1982-02-04 | Xerox Corp | Planar thin film transistor array and method of producing same |
JPS58124228A (en) * | 1982-01-21 | 1983-07-23 | Nec Corp | Manufacture of semiconductor device |
JPS5994438A (en) * | 1982-11-19 | 1984-05-31 | Tdk Corp | Forming method of patterned aluminum layer |
-
1984
- 1984-10-01 JP JP20411484A patent/JPS6184066A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51150986A (en) * | 1975-06-19 | 1976-12-24 | Mitsubishi Electric Corp | Fabrication method of semiconductor device |
JPS5721867A (en) * | 1980-06-02 | 1982-02-04 | Xerox Corp | Planar thin film transistor array and method of producing same |
JPS58124228A (en) * | 1982-01-21 | 1983-07-23 | Nec Corp | Manufacture of semiconductor device |
JPS5994438A (en) * | 1982-11-19 | 1984-05-31 | Tdk Corp | Forming method of patterned aluminum layer |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62216372A (en) * | 1986-03-18 | 1987-09-22 | Fujitsu Ltd | A-si thin film transistor |
JPH0449625A (en) * | 1990-06-19 | 1992-02-19 | Nec Corp | Thin-film transistor and its manufacturing method |
EP0506117A2 (en) * | 1991-03-29 | 1992-09-30 | Casio Computer Company Limited | Thin-film transistor |
EP0506117A3 (en) * | 1991-03-29 | 1995-09-27 | Casio Computer Co Ltd | Thin-film transistor |
EP1691340A1 (en) * | 2003-11-28 | 2006-08-16 | OHMI, Tadahiro | Thin film transistor integrated circuit device, active matrix display device, and manufacturing method of the same |
EP1691340A4 (en) * | 2003-11-28 | 2012-06-27 | Tadahiro Ohmi | Thin film transistor integrated circuit device, active matrix display device, and manufacturing method of the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4746628A (en) | Method for making a thin film transistor | |
US5306653A (en) | Method of making thin film transistors | |
JPH0828510B2 (en) | Method of forming thin film transistor | |
JPS6184066A (en) | Manufacture of thin film transistor | |
JPS6184065A (en) | Manufacture of thin film transistor | |
JP3094610B2 (en) | Method for manufacturing thin film transistor | |
JPH0640585B2 (en) | Thin film transistor | |
JPS63177472A (en) | Thin-film transistor | |
JP3114303B2 (en) | Thin film transistor panel and method of manufacturing the same | |
JP2000232227A (en) | Manufacture of thin film transistor | |
JP3168648B2 (en) | Method for manufacturing thin film transistor panel | |
KR100302999B1 (en) | Thin film transistor using double gate | |
JP3599174B2 (en) | Thin film transistor panel and method of manufacturing the same | |
JPH0353787B2 (en) | ||
JPS6347981A (en) | Thin film transistor and manufacture thereof | |
JP2503269B2 (en) | Method for forming gate electrode of field effect transistor | |
JPS6132421A (en) | Manufacture of semiconductor device | |
JPH04302474A (en) | Thin-film transistor | |
JPH05251701A (en) | Formation of thin film transistor | |
JP3149034B2 (en) | Thin film transistor | |
JP2527579B2 (en) | Method for manufacturing thin film transistor | |
JPH04302438A (en) | Thin-film transistor | |
JPH05203990A (en) | Thin film transistor panel | |
KR940005446B1 (en) | Method of manufacturing electrode of semiconductor device | |
JPS5975668A (en) | Manufacture of thin film transistor |