JPS58124228A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58124228A JPS58124228A JP815582A JP815582A JPS58124228A JP S58124228 A JPS58124228 A JP S58124228A JP 815582 A JP815582 A JP 815582A JP 815582 A JP815582 A JP 815582A JP S58124228 A JPS58124228 A JP S58124228A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- photoresist
- aluminum metal
- electrode wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000002274 desiccant Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 11
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- 235000006408 oxalic acid Nutrition 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- 238000007743 anodising Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、アルミニウム金属音用いた半導体装置の陽
極酸化法による電極配線形成方法に明する。DETAILED DESCRIPTION OF THE INVENTION The present invention discloses a method for forming electrode wiring by anodizing a semiconductor device using aluminum metallurgy.
従来の陽他酸化の技術を篇１図（ａ）、 （ｂｌを用い
て説明する。半導体基板上、もしくは絶縁膜基板４上に
、アルミニウム金属３を蒸着した後、アルミニウム金属
表面を薄くアルミナ２に変質させた後、フォトレジスト
１の電極配線のパターンニングを行なう（第１図（ａ）
）。The conventional anodic oxidation technique will be explained using Figure 1 (a) and (bl). After depositing aluminum metal 3 on a semiconductor substrate or an insulating film substrate 4, the aluminum metal surface is thinly coated with alumina 2. After the photoresist 1 is changed in quality, the electrode wiring of the photoresist 1 is patterned (Fig. 1(a)).
).
次に蓚漬水溶液を用いて、陽極１化すると、フォトレジ
スト１を塗布した部分以外のアルミニウム金属３ば、ア
ルミナ５に変わり、アルミニウム金属電極配線６が選択
的に形成される（第１図（ｂ））。Next, when the anode 1 is formed using an aqueous soaking solution, the aluminum metal 3 other than the area coated with the photoresist 1 changes to alumina 5, and an aluminum metal electrode wiring 6 is selectively formed (see Fig. 1). b)).
この様な、従来の陽極酸化法による電極配線形成方法で
は次の二つの問題が生じる。すなわち、フォトレジスト
１とアルミニウム金属表面の密着性を良くするために、
アルミニウム金属表面全薄くアルミナ２に変質させる必
要がある。さらに、二層配線を形成する場合、配線上の
アルミナと層間絶縁膜の二つの部分にわたって開孔する
必要がある。The following two problems arise in such a conventional electrode wiring formation method using the anodic oxidation method. That is, in order to improve the adhesion between the photoresist 1 and the aluminum metal surface,
It is necessary to transform the entire aluminum metal surface into alumina 2. Furthermore, when forming a two-layer wiring, it is necessary to open holes across two parts: the alumina on the wiring and the interlayer insulating film.
従って、本発明の目的は、作業効率の改善にある。Therefore, an object of the present invention is to improve work efficiency.
本発明は、半導体もしくは絶縁膜基板上にアルミニウム
金属の電極配線を陽極酸化法によシ、形成する工程に於
て、フォトレジス［用いずに、酸化膜や霊化膜などの絶
縁Ｍをマスクにして電極配線形成を行なう方法で、更に
、その絶縁膜全電極配綜都のカバーに用いる事を特徴と
する。In the process of forming aluminum metal electrode wiring on a semiconductor or insulating film substrate by an anodizing method, the present invention uses a photoresist (without using a photoresist) to mask an insulating layer such as an oxide film or an atomized film. This method is characterized in that the insulating film is used as a cover for all electrode wiring.
以下、本発明の実施例を第２図（ａｌ、 （ｂｌ、 （
Ｃ１を用いて説明する。Embodiments of the present invention will be described below with reference to FIG. 2 (al, (bl, ()).
This will be explained using C1.
半導体もしくば、絶縁膜基板４上にアルミニウム金属３
を蒸着した後、絶縁膜７とＩ−てＣＶＤ酸化膜を薄く成
長させ、フォトレジスト１の電極配線のパターンニング
を行なう（第２図（ａ））。Aluminum metal 3 on semiconductor or insulating film substrate 4
After depositing the insulating film 7, a thin CVD oxide film is grown on the insulating film 7, and patterning of the electrode wiring of the photoresist 1 is performed (FIG. 2(a)).
次に、フォトレジスト１會マスクにして絶縁膜７ｔドラ
イエツチし、パターンニング＋行なう（第２図（ｂ））
。Next, 7t of insulating films are dry-etched using a photoresist mask, and patterning is performed (Fig. 2(b)).
.
更に、フォトレジスト１を除去１．た後、蓚酸水溶液を
用いて、陽極酸化を行なうと、絶縁膜７′がある部分以
外のアルミニウム金属３はアルミナ５に変わり、アルミ
ニウム金属３は、アルミナ５に変わり、アルミニウム電
極配線６が選択的に形成される。Furthermore, photoresist 1 is removed 1. After that, when anodic oxidation is performed using an oxalic acid aqueous solution, the aluminum metal 3 other than the part where the insulating film 7' is present changes to alumina 5, the aluminum metal 3 changes to alumina 5, and the aluminum electrode wiring 6 is selectively oxidized. is formed.
かかる本発明によれば第１図（ａｌに於て、アルミニウ
ム金属３表面を薄くアルミナ２に変質させる必要もなく
、２属構造を造る場合に、１層配線と２層配線全接続す
るための開孔が１回で容易にできる。According to the present invention, there is no need to transform the surface of the aluminum metal 3 into a thin layer of alumina 2 as shown in FIG. Holes can be easily drilled in one go.
更に、一層配線だけの場合でも、第２１凶ｆｃ）の絶縁
膜７′會配隷カバーとして使用できる。Furthermore, even in the case of only one layer of wiring, it can be used as a 21st layer fc) insulating film 7' support cover.
以上説明した様に、本づろ明の製造方法によると、電極
配線形成のために、アルミニウム金属表面全アルミナに
変質させる必要もなく、更に、マスクとして用いた絶縁
膜全配線カバーあるいは、層間絶縁膜として使用でき、
作業性の向上が期待できる。As explained above, according to Honzuromei's manufacturing method, there is no need to transform the aluminum metal surface into all-alumina in order to form electrode wiring, and there is no need to completely cover the wiring with the insulating film used as a mask, or to use interlayer insulation. Can be used as a membrane,
It can be expected to improve work efficiency.
第１図（ａｌ、 （ｂｌは従来のアルミニウム金属電極
配線形成方法全説明する断面図であり、第２図（ａ）〜
（Ｃ１は、本発明実施例の電極配線形成方法を説明する
断面図である。
尚、図に於て、
１・・・・・・フォトレジスト、２・・・・・・薄いア
ルミナ、３・・・・・・アルミニウム金属、４・・・・
・・半導体もしくは絶縁膜基板、５・・・・・・アルミ
ナ、６・・・・・・アルミニウム電極配線、７．７’・
・・・・・薄い絶縁膜、である。
５−
ｒ ｆ図ｔｂ）
第２図（（１）
第２図（１））Figure 1 (al, (bl) is a sectional view illustrating the entire conventional aluminum metal electrode wiring forming method, and Figures 2 (a) to 2)
(C1 is a cross-sectional view illustrating the electrode wiring forming method of the embodiment of the present invention. In the figure, 1... photoresist, 2... thin alumina, 3... ...Aluminum metal, 4...
... Semiconductor or insulating film substrate, 5 ... Alumina, 6 ... Aluminum electrode wiring, 7.7'.
...A thin insulating film. 5- r f diagram tb) Figure 2 ((1) Figure 2 (1))
Claims (1)
線を陽極数比法で形成する工程に焚で、アルミニウム電
極配線？パターンニングする際のマスクに液化膜または
望化膜を含む絶縁膜を用い、更に、該絶縁膜を配線カバ
ー、あるいは、層間絶縁膜として用いる事會特徴とする
半導体装置の製造方法。Aluminum electrode wiring is formed by burning in the process of forming aluminum electrode wiring on a semiconductor or insulating film substrate using the anodic ratio method? A method for manufacturing a semiconductor device, characterized in that an insulating film containing a liquefied film or a desiccant film is used as a mask during patterning, and the insulating film is further used as a wiring cover or an interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP815582A JPS58124228A (en) | 1982-01-21 | 1982-01-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP815582A JPS58124228A (en) | 1982-01-21 | 1982-01-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58124228A true JPS58124228A (en) | 1983-07-23 |
Family
ID=11685427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP815582A Pending JPS58124228A (en) | 1982-01-21 | 1982-01-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58124228A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184065A (en) * | 1984-10-01 | 1986-04-28 | Oki Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPS6184066A (en) * | 1984-10-01 | 1986-04-28 | Oki Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPS6189673A (en) * | 1984-10-09 | 1986-05-07 | Matsushita Electric Ind Co Ltd | Manufacture of thin film semiconductor device |
| RU2739750C1 (en) * | 2019-12-16 | 2020-12-28 | Федеральное государственное бюджетное учреждение науки Новосибирский институт органической химии им. Н.Н. Ворожцова Сибирского отделения Российской академии наук (НИОХ СО РАН) | Method of producing micron electrically conducting tracks on anodised aluminium substrates |
-
1982
- 1982-01-21 JP JP815582A patent/JPS58124228A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184065A (en) * | 1984-10-01 | 1986-04-28 | Oki Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPS6184066A (en) * | 1984-10-01 | 1986-04-28 | Oki Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPS6189673A (en) * | 1984-10-09 | 1986-05-07 | Matsushita Electric Ind Co Ltd | Manufacture of thin film semiconductor device |
| RU2739750C1 (en) * | 2019-12-16 | 2020-12-28 | Федеральное государственное бюджетное учреждение науки Новосибирский институт органической химии им. Н.Н. Ворожцова Сибирского отделения Российской академии наук (НИОХ СО РАН) | Method of producing micron electrically conducting tracks on anodised aluminium substrates |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS58124228A (en) | Manufacture of semiconductor device | |
| JPH07288247A (en) | Dry etching method for silicon oxide film | |
| JPS6345835A (en) | Semiconductor device | |
| JPS62242337A (en) | Formation of metal film for multilayer interconnection | |
| JPS5871642A (en) | Semiconductor device | |
| JP2946590B2 (en) | Method for manufacturing semiconductor device | |
| JPS6241419B2 (en) | ||
| JPS5963746A (en) | Semiconductor device having multi-layer wiring | |
| JPS58210168A (en) | Etching method of two-layered film | |
| JPS62291943A (en) | Manuafcture of semiconductor device | |
| JPS581544B2 (en) | Manufacturing method of semiconductor device | |
| JPS6193629A (en) | Manufacture of semiconductor device | |
| JPH02113566A (en) | Semiconductor integrated circuit | |
| JPS60762A (en) | Manufacture of hybrid integrated circuit | |
| JPS60147137A (en) | Forming process of multilayered metallic wiring | |
| JPS6236842A (en) | Manufacture of semiconductor device | |
| JPS59114839A (en) | Manufacture of semiconductor device | |
| JPH11204532A (en) | Method for forming wiring of semiconductor element | |
| JPS55118652A (en) | Manufacture of semiconductor device | |
| JPS6325519B2 (en) | ||
| JPH05109901A (en) | Semiconductor device with multilayer interconnection structure and its production | |
| JPS5477590A (en) | Production of semiconductor device | |
| JPS60262442A (en) | Manufacture of semiconductor device | |
| JPH0291968A (en) | Manufacture of memory device | |
| JPH03211834A (en) | Formation of wiring pattern |