JPS60262442A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60262442A
JPS60262442A JP11772884A JP11772884A JPS60262442A JP S60262442 A JPS60262442 A JP S60262442A JP 11772884 A JP11772884 A JP 11772884A JP 11772884 A JP11772884 A JP 11772884A JP S60262442 A JPS60262442 A JP S60262442A
Authority
JP
Japan
Prior art keywords
layer
wiring
film
ion milling
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11772884A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Miyazaki
宮崎 光広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11772884A priority Critical patent/JPS60262442A/en
Publication of JPS60262442A publication Critical patent/JPS60262442A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To shorten a through-hole boring process by boring openings to an alumina layer as first layer wiring and an inter-layer insulating film through one- time ion milling and attaching and forming a second layer metal through sputtering in a device. CONSTITUTION:First layer Al wiring 13 and a thick alumina film 12 and a thin alumina film 12' on the wiring 13 through an anodizing method are formed onto a semiconductor substrate 11. An inter-layer insulating film 14 is grown on the films 12, 12', and a photo-resist 16 for forming a through-hole is attached and patterned. The film 14 and the film 12' are tapered and bored through one-time ion milling by an ion milling device. The resist 16 can also be removed through etching at the same time. Targets are exchanged and Al is attached through sputtering as a second layer metal in said device, the photo-resist is patterned, and a second layer Al wiring 15 is formed through etching. Accordingly, a manufacturing process can be shortened while a breaking at the stepped section of the second layer Al wiring can be prevented.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置の製造方法に関し、特に一層目配線
を陽極酸化法により形成した場合の一層目配綜上の蒋い
アルミナ層と層間絶縁膜の開孔方法と二層目耐線金rの
付着力法に関する。
Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a flexible alumina layer on a first-layer wiring board and interlayer insulation when the first-layer wiring is formed by an anodizing method. This article relates to the method of opening holes in the membrane and the method of adhesion of the second layer of wire-resistant metal r.

(従来技術) 従来の半導体装置の層間絶縁膜のスルーホールを開孔し
第一層目と第二層目の配線を接訃1・する方法を第3図
(a)〜(d)を用いて説明する。
(Prior art) A conventional method of opening through holes in the interlayer insulating film of a semiconductor device and connecting the first and second layer wiring is shown in FIGS. 3(a) to 3(d). I will explain.

先ず、第3図(alに示すように、半導体基板1に一層
目l!iil!線のために、アルミニウム3を付着し1
、次いで陽極酸化法にまり6i1線を形成する。一層目
のアルミニウム配線表面上の薄いアルミナ膜2′に開孔
するためホトレジス)64’jよりパター ンニングを
行う。
First, as shown in FIG. 3 (al), aluminum 3 is attached to the semiconductor substrate 1 for the first layer l!
Then, a 6i1 line is formed using an anodic oxidation method. Patterning is performed using photoresist (64'j) to open holes in the thin alumina film 2' on the surface of the first layer of aluminum wiring.

次に、第3図(b)に示すように、アルミナ膜2′をエ
ツチングした稜に層間絶縁膜4を半導体基板表面上に成
長させ、開孔のためにホトレジスト6′によりパターン
ニングする。
Next, as shown in FIG. 3(b), an interlayer insulating film 4 is grown on the surface of the semiconductor substrate along the etched edges of the alumina film 2', and patterned with photoresist 6' to form holes.

次に、舘3図(C)に示すように、庖間絶縁願4をウェ
ットエツチングし、開孔しfc 稜s半導体基板上に二
層目のアルミニウム配線圏5を付着させ、しかる後配線
形成のためにホトレジスト6“によリパターンニングす
る。
Next, as shown in Figure 3 (C), the insulation layer 4 is wet-etched to form holes, and a second layer of aluminum wiring layer 5 is deposited on the semiconductor substrate, after which wiring is formed. For this purpose, repatterning is performed using photoresist 6''.

次に、第3図(dlに示すように、ホトレジスト6”を
マスクとしてエツチングし、しかるのちホトレジスト6
“を除去すれば二層配線構造の半導体装置が得られる。
Next, as shown in FIG.
By removing ", a semiconductor device with a two-layer wiring structure can be obtained.

以上により得られた半導体装置では次のよう々問題があ
る。
The semiconductor device obtained as described above has the following problems.

(1)一層目のアルミニウム配線上の漫いアルミナ膜を
開孔する工程及び層間絶縁膜成長後に再び同一箇所に開
孔する工程が必要となり工程が禅雑となる。
(1) The process becomes complicated because it requires a step of opening a hole in the round alumina film on the first layer of aluminum wiring and a step of opening the hole again at the same location after the growth of the interlayer insulating film.

(2)薄いアルミナ層と層間の絶縁膜をウェットエツチ
ングにより開孔するため、及び二層のホトレジストのパ
ターンニングで目合せにずれが生ずるとスルーホールの
段がかなり急峻となるため、二層目配線のアルミニウム
を付着した後にスルーホール部で段切れを生ずる。
(2) Because holes are formed in the thin alumina layer and the insulating film between the layers by wet etching, and if there is a misalignment in patterning the two layers of photoresist, the steps of the through holes will become quite steep. After the aluminum wiring is attached, a break occurs at the through-hole area.

(発明の目的) 本発明の目的は、上記欠点を除去し、スルーホール開孔
工程の短縮化り二層目アルミニウム配線 3− のスルーホール部での段切れを防止できる半導体装置の
製造方法を提供することにある。
(Object of the Invention) The object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, shortens the through-hole drilling process, and prevents breakage at the through-hole portion of the second layer aluminum wiring. It is about providing.

(発明の構成) 本発明の半導体装置の製造方法は、一層目配線と二層目
配線の接続を層間絶縁膜に開孔、形成したスルーホール
により行う二層配線構造の半導体装置の製造方法におい
て、一層目配線上の薄いアルミナ層と層間絶縁膜を一回
のイオンミーリングにより、テーパーをつけて開孔する
工程と、更に同装置内でターゲットを交換してアルミニ
ウムを二層目金、属としてスパッタ((より付着形成す
る工程とを含んで構成される。
(Structure of the Invention) A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a two-layer wiring structure, in which a first layer wiring and a second layer wiring are connected by a through hole formed in an interlayer insulating film. , the process of forming a tapered hole in the thin alumina layer on the first layer wiring and the interlayer insulating film by one-time ion milling, and then changing the target in the same equipment and forming the aluminum as the second layer metal. It is composed of sputtering ((a step of forming an adhesion layer).

(実施例) 以下、本発明の実施例について、図面をtI積して説明
する。第1図(a)〜(C)は本発明の一実施例を説明
するために工程順に示した断面図であり、第2区(a)
 、 (b) 、 (c)はイオンミーリングの説明図
で、 1第2図(a)はイオンミーリンクの原理説明図
、第2図fb)はイオンミーリングによる半導体基板の
層間絶縁膜エツチング時の装置内部説明図、第2図(C
) 4 − はイオンミーリングによる半導体基板上へアルミニウム
のスパック時の装置内部の説明図でt)る。
(Example) Examples of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(C) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention, and the second section (a)
, (b) and (c) are explanatory diagrams of ion milling. 1 Figure 2 (a) is an explanatory diagram of the principle of ion milling, and Figure 2 (fb) is an illustration of the etching of an interlayer insulating film of a semiconductor substrate by ion milling. Explanatory diagram of the inside of the device, Figure 2 (C
) 4- is an explanatory diagram of the inside of the apparatus when spun aluminum onto a semiconductor substrate by ion milling.

先ず、第1図(a) K示すように、半導体基板bl上
に一層目のアルミニウム配線13を形成する8なお12
は陽極酸化法により形成された厚いアルミナ膜、12′
はアルミニウム配線上の薄いアルミナ膜である。次いで
、アルミナ膜12.12’上に層間絶縁膜14を成長し
た後、スルーホール形成のためのホトレジスト16を付
着、パターンニングする。
First, as shown in FIG. 1(a), the first layer of aluminum wiring 13 is formed on the semiconductor substrate bl.
is a thick alumina film formed by anodic oxidation, 12'
is a thin alumina film on aluminum wiring. Next, after an interlayer insulating film 14 is grown on the alumina film 12, 12', a photoresist 16 for forming through holes is deposited and patterned.

次に、第2図(a) 、 (blに示すようにホトレジ
スト16のパターンニングの終了した半導体基板25を
イオンミルリング装置27内のホルダー18にセットし
、ホルダー18を図示のように00傾斜させ、イオン化
しlとArw、子19をウェーハにあてる。イオンミー
リンク中はホルダー8をホルダーの法線に対し回転させ
る。ホルダー8を回転させることにより、ウェーハ内及
びホルダー内のエツチングのバラツキを少なくできる。
Next, as shown in FIGS. 2A and 2B, the semiconductor substrate 25 on which the patterning of the photoresist 16 has been completed is set in the holder 18 in the ion milling device 27, and the holder 18 is tilted at a 00 angle as shown in the figure. The wafer is ionized, and the wafer is exposed to the wafer.During the ionization process, the holder 8 is rotated relative to the normal line of the holder.By rotating the holder 8, variations in etching within the wafer and within the holder can be reduced. You can do less.

イオンミーリングはAr 9による物理的カエッ 5− チングであるため、ホトレジスト16の膜厚を適切に選
び、しかもホルダーを傾斜させることにより第1図(b
)に示す スルーホールtでテーパーkhけてエツチン
グすることができ、同時にホトレジスト16もエツチン
グ除去できる1、エツチング中はイオンミーリング装置
^のアルミニウムターゲットのシャッター22は閉ぢて
おく。
Since ion milling is physical etching using Ar 9, by appropriately selecting the film thickness of the photoresist 16 and tilting the holder, it is possible to achieve
) It is possible to perform etching through the taper kh with the through hole t, and at the same time, the photoresist 16 can also be removed by etching 1. During etching, the shutter 22 of the aluminum target of the ion milling device is kept closed.

次に、第2図(c)に示すように、スルーホールを開孔
した半導体基板25′なぞのままホルダー18にセット
した状態でイオ〉・ソース2】及びグリッド23を角度
をθ0傾斜させAr 9をアルミニウムターゲラl−2
0に向ける。次いでアルミニウムターゲット20のシャ
ッター22を開けるとAr 19がアルミニウムターゲ
ット20に衝突し、それによりアルミニウム原子24が
飛び出し、早尋体男二板25′に伺弘する。所定の時間
つ′ルミニウム奮付着した後、取り出し二m配線のホト
レジストパターンニングを行い、しかる後エツチングを
行うと第1図(C) (tこ示すような、二層目のアル
ミニウム配線15が形成でき、その結釆、本発明により
 6 − 二層配線構造の半導体装置が得られる。
Next, as shown in FIG. 2(c), while the semiconductor substrate 25' with the through-holes is set in the holder 18, the ion source 2 and the grid 23 are tilted at an angle of θ0. 9 aluminum targera l-2
Point towards 0. Next, when the shutter 22 of the aluminum target 20 is opened, Ar 19 collides with the aluminum target 20, whereby aluminum atoms 24 are ejected and propagated into the fastening body plate 25'. After the aluminum has been deposited for a predetermined period of time, photoresist patterning is performed to take out the 2m wiring, and then etching is performed to form the second layer of aluminum wiring 15 as shown in Figure 1(C). As a result, according to the present invention, a semiconductor device having a 6-two-layer wiring structure can be obtained.

(発明の効果) 以上説明したように本発明によれば、半導体基板上に一
層目配線形成後、層間絶縁膜にスルーホールをイオンミ
ーリングによりテーパーをつけて一回の工程でエツチン
グでき、しかもホトレジストも除去でき、更に同一装置
内で二層目配線用のアルミニウム金属をスパッタにより
付着することができる。
(Effects of the Invention) As explained above, according to the present invention, after the first layer wiring is formed on a semiconductor substrate, a through hole can be formed in an interlayer insulating film by ion milling to form a taper and then etched in a single process. Furthermore, aluminum metal for second layer wiring can be deposited by sputtering in the same device.

従って、二層目アルミニウム配線の段切れを防止できる
と共に、製造工程を大幅に短縮することが出来る。
Therefore, it is possible to prevent breakage of the second layer aluminum wiring, and to significantly shorten the manufacturing process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(c)は本発明の一実施例を説明するた
めに工程順に示した断面図、第2図(al〜(c)は本
発明の実施に使用するイオンソ−リングの説明図で、第
2図(a)は原理説明図、第2図(blは半導体基板上
の層間絶縁膜のイオンミーリング時のイオンミーリング
装置内部説明図、第2図(C1はイオンミーリングによ
る半導体基板上へアルミニウムのスパッタ時の装置内部
説明図、第3図fal〜(coは従来の半導体装置の製
造方法を説明するために一工程順に示した断面図である
。 1.11・・・・・・半導体基板、2,12申°°・ア
ルミナ、2’、12’・・・・・・一層目アルミニウム
配線上の薄いアルミナ膜、3,13・・・・・・一層目
アルミニウム配線、4,14・・・・・・絶縁膜、5,
15・・・・・・二層目アルミニウム配線、6.6’、
6“、16・・・・・・ホトレジスト、18・・・・・
・半導体基板セット用ホルダー、19・・・・・・Ar
イオン、20・・・・・・アルミニウムターゲット、2
1・・・・・・イオンソース、22・・・・・・アルミ
ニウムターゲット用シャッター、23・・・・・・グリ
ッ)”、24・・・・・・アルミニウム原子、25・・
・・・・スルーホールを開孔する半導体基板、25′・
・・・・・スルーホールを開孔した半導体基板、26・
・・・・・排気口、27°°°゛°°ミ一リ2グ装置本
体・ 5” −at d リ 第2 図 −222− 茅3I¥J
FIGS. 1(a) to (c) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention, and FIGS. 2(a) to (c) are sectional views of the ion-soring process used to implement the present invention. Figure 2 (a) is an explanatory diagram of the principle, Figure 2 (bl is an explanatory diagram of the inside of the ion milling apparatus during ion milling of an interlayer insulating film on a semiconductor substrate, and Figure 2 (C1 is an illustration of the inside of the ion milling apparatus during ion milling of an interlayer insulating film on a semiconductor substrate). Fig. 3 is an explanatory view of the inside of the apparatus during sputtering of aluminum onto a substrate, and Figs.・・Semiconductor substrate, 2,12°・Alumina, 2′, 12′・・・・・・Thin alumina film on first layer aluminum wiring, 3,13・・・・First layer aluminum wiring, 4 , 14... Insulating film, 5,
15... Second layer aluminum wiring, 6.6',
6", 16... photoresist, 18...
・Holder for semiconductor board set, 19...Ar
Ion, 20... Aluminum target, 2
1... Ion source, 22... Aluminum target shutter, 23... Grit), 24... Aluminum atom, 25...
... Semiconductor substrate with through holes, 25'.
...Semiconductor substrate with through holes, 26.
...Exhaust port, 27°°°゛°° Milling device body・5”

Claims (1)

【特許請求の範囲】[Claims] 一凧゛目配線と二層目配線の接続を層り絶縁膜に開孔、
形成したスルーホールにより行う二層配線構造の半導体
装置の99造方法において、一層目配線上の薄いアルミ
ナt−と層間絶縁膜を一回のイオンミーリングにより、
テーパーをつけて開孔する工程と、更に同装置内でター
ゲットを9換してアルミニウムを二層目金属としてスパ
ッタにより付着形成する工程とを含むことを特徴とする
半導体装置の製造方法。
Layer the connection between the first layer wiring and the second layer wiring, and open a hole in the insulating film.
In the 99 manufacturing method of a semiconductor device with a two-layer wiring structure using the formed through-hole, the thin alumina T- layer on the first layer wiring and the interlayer insulating film are removed by one ion milling.
A method for manufacturing a semiconductor device, comprising the steps of forming a hole with a taper, and further changing the target to 9 in the same apparatus and depositing aluminum as a second layer metal by sputtering.
JP11772884A 1984-06-08 1984-06-08 Manufacture of semiconductor device Pending JPS60262442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11772884A JPS60262442A (en) 1984-06-08 1984-06-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11772884A JPS60262442A (en) 1984-06-08 1984-06-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60262442A true JPS60262442A (en) 1985-12-25

Family

ID=14718812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11772884A Pending JPS60262442A (en) 1984-06-08 1984-06-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60262442A (en)

Similar Documents

Publication Publication Date Title
JPH0519818B2 (en)
JPH04249321A (en) Manufacture of semiconductor device
JP2720023B2 (en) Method for manufacturing semiconductor device
JPS60262442A (en) Manufacture of semiconductor device
JPS5999718A (en) Semiconductor device
JP2738682B2 (en) Wiring formation method
JPS6379347A (en) Manufacture of semiconductor device
JPH0212827A (en) Manufacture of semiconductor device
JPH0435048A (en) Forming method for multilayer wiring of semiconductor device
JPH10189606A (en) Bump of semiconductor device and manufacture thereof
JPS58124228A (en) Manufacture of semiconductor device
JPH06104206A (en) Method and apparatus for manufacturing semiconductor device
JPS5877246A (en) Formation of multilayer wiring structure
JPS62120046A (en) Manufacture of semiconductor device
JPH01119042A (en) Manufacture of semiconductor device
JPH05308182A (en) Manufacture of film circuit board
JPS6193629A (en) Manufacture of semiconductor device
JPS6028237A (en) Manufacture of semiconductor device
JPH07106419A (en) Fabrication of semiconductor device
JPH04207054A (en) Manufacture of semiconductor device
JPH01255246A (en) Manufacture of semiconductor device
JPS6092633A (en) Manufacture of semiconductor device
JPS6148942A (en) Method of forming electrode of semiconductor device
JPH023926A (en) Forming method of wiring
JPS60147137A (en) Forming process of multilayered metallic wiring