JPS6345835A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the step coverage and to prevent the generation of microcracks by a method wherein the part vertical to the semiconductor substrate located on the side face of the contact window, with which the upper wiring and the lower wiring will be connected, is formed in a height of 200 nm or less. CONSTITUTION:A contact window is perforated on the oxide film 3a and the nitride film 3b, with which the Al wiring 2 of the lower layer on a semiconductor substrate 1 is covered, by performing isotropic and anisotropic etching respectively. Besides, a plurality of metal layers such as a Ti layer 6a, a Pt layer 6b and an Au layer 6c, with which the contact window is covered, are provided. At this point, when the film thickness (d) of the oxide film 3a is formed at 200 nm or less, at 100 nm or thereabout, for example, the height of the part vertical to the side face of the contact window is formed at 100 nm or thereabout. Accordingly, the contact window is formed into the shape with which the step coverage of the upper layer of metal layer is improved. As a result, the generation of microcracks can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including multilayer wiring.

[Conventional technology]

In general, methods for opening contact windows for wiring in semiconductor devices with multilayer wiring include methods that use isotropic etching, methods that use anisotropic etching, and methods that use a combination of the two. be. Among these methods, a method in which the hole is opened halfway by isotropic etching and then completely opened by anisotropic etching has a pattern accuracy that is comparable to that of conventional semiconductor devices.

[Problem that the invention seeks to solve]

The anisotropically etched portion of the contact window in the conventional semiconductor device described above is often set to several hundred nm (for example, 500 nm) from the point of view of pattern size, and the upper layer wiring is deposited by sputtering. In the case of a metal such as aluminum, the step coverage was sufficient.

However, in semiconductor devices that require extremely high speed and high reliability, a plurality of metal layers such as titanium-platinum-gold or titanium-palladium-gold are often used for upper layer wiring. In this case, the first layer of metal that initially covers the contact window is often titanium, titanium alloy, or titanium compound, but the vertical portion of the side surface formed by anisotropic etching of the contact window is usually 100 nm
In particular, when the thickness is 200 nm or more, the coating properties are extremely poor, resulting in a disadvantage that the manufacturing yield and quality of semiconductor devices are reduced.

This problem shows that simply depositing the first metal layer thickly does not improve the step coverage; if it is too thick, stress in the film will be applied to the interlayer insulating film. In addition, there was even the inconvenience of generating microcracks.

[Means for solving problems]

The semiconductor device of the present invention is a multilayer wiring type semiconductor device comprising lower and upper conductor layers stacked via an interlayer insulating film and connected through a contact window opened in the interlayer insulating film. The conductor layer is comprised of a plurality of conductor layers including a first metal layer for adhesion to the lower conductor layer and a second metal layer for diffusion prevention, and the vertical portion of the side surface of the contact window is less than 200 nm. It has a predetermined height.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention.

In this embodiment, a contact window is formed by isotropic and anisotropic etching, respectively, in an oxide film 3a and a nitride film 3b that sequentially cover a lower layer Ae wiring 2 formed on a semiconductor substrate 1. Ti layer 6a covering the window, Pt
The structure includes a plurality of metal layers including an upper layer b and an Au layer 6C. Here, the film thickness d of oxidized fil 3 a is set to 200
If it is less than nm, for example, about 1100n, the height of the vertical part of the side surface of the contact window will be about 1100n, and the contact window will have a shape that improves the step coverage of the upper metal layer. .

FIGS. 2(a) to 2(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention.

In this embodiment, first, as shown in FIG. 2(a), Ae
Approximately 1100 nm is placed on the semiconductor substrate 1 on which the wiring 2 is formed.
An oxide film M3a having a thickness of 1 and a nitride film 3b thereon are successively formed.

Next, as shown in FIG. 2(b), after forming a photoresist film 4 having an opening for forming a contact window, first, nitriding is performed by isotropic plasma etching using the photoresist film 4 as a mask. The film 3b is removed and a contact window 5a is opened.

At this time, the etching rates of the nitride film and the oxide film in isotropic plasma etching are quite different, so it is relatively easy to terminate the isotropic plasma etching when only the nitride film has been removed. can.

In this way, after opening the contact window 5a in the nitride film 3b by isotropic plasma etching, as shown in FIG.
), the oxide film 3a is etched by anisotropic etching.
A hole is opened in the contact window 5b. Therefore, of the height removed by anisotropic etching, the height of the contact window perpendicular to the semiconductor substrate is controlled to a value approximately equal to the thickness of the oxide film 3a, in this case approximately 1100n. be able to.

Next, after removing the photoresist film 4, a Ti layer 6a, which is an upper metal layer, and a PT upper layer b are first deposited.In the present invention, the shape of the contact window is extremely easy to coat. Therefore, the Ti layer 6a and the PT upper layer b
Even with such a metal layer with poor coating properties, a sufficient coating state can be obtained. After that, dry etching etc.
After patterning the i layer 6a and the Pt upper layer b, an Au layer 6c is deposited by plating or the like to complete an embodiment of the semiconductor device of the present invention.

In fact, a semiconductor device in which the vertical portion of the contact window was 200 nm or more was prototyped, but microcracks and the like were generated and the step coverage was not good.

The above describes a method in which the present invention is applied to a multilayer wiring type semiconductor device including wiring of Ti-Pt-Au layers.
It is obvious that the present invention can be similarly implemented in other semiconductor devices having similar structures.

〔Effect of the invention〕

As explained above, the present invention has a structure in which the side surface of the contact window that connects the upper layer wiring and the lower layer wiring is made so that the part perpendicular to the semiconductor substrate has a predetermined height of less than 200 nm. Even with metals that have difficulty covering steps (step coverage), contact windows can be sufficiently covered and processed without sacrificing pattern accuracy, making it possible to manufacture high-performance multilayer wiring semiconductor devices with high yields. It has the advantage of being able to be manufactured with high quality.

[Brief explanation of drawings]

FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIG.
Figures (a) to (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Ae wiring, 3a... Oxide film, 3b... Nitride film, 4... Photoresist film, 5
a. 5b... Contact window, 6a... Ti layer, 6b...
...pt layer, 6c...-A u layer.

Claims (1)

[Claims] In a multilayer wiring type semiconductor device comprising lower and upper conductor layers stacked via an interlayer insulating film and connected through a contact window opened in the interlayer insulating film, the upper conductor layer is connected to the lower conductor layer. The contact window is made up of a plurality of conductor layers including a first metal layer for adhesion to the contact layer and a second metal layer for diffusion prevention, and the vertical portion of the side surface of the contact window is 2.
A semiconductor device having a predetermined height of less than 00 nm.